From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 28 Sep 2017 19:40:52 +0200 (CEST) Received: from mail-sn1nam01on0042.outbound.protection.outlook.com ([104.47.32.42]:33276 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S23992348AbdI1RjIKYOAF (ORCPT ); Thu, 28 Sep 2017 19:39:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=BRlfQZ6c279OTiyUi1BpcQpZO3qF08d1H8Y0yPoLnf0=; b=P1CMRVapp92onDiiA0kWpPiVZ2g2g4vsQslqO4h3lUAzcwxLKxsO3344CXjj0hAvB75WMj/s3n0eZoa72MsVaML0K+BJfvsv8UytfXl2XnlJnUGYYJBM22pYxAxwuEX5+TCtTwFVLLD6+o5BwqOZsSv5FR2sBDWgGqqcZp33ouY= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Steven.Hill@cavium.com; Received: from black.inter.net (173.18.42.219) by SN4PR0701MB3807.namprd07.prod.outlook.com (2603:10b6:803:4e::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7; Thu, 28 Sep 2017 17:39:00 +0000 From: "Steven J. Hill" To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH v2 05/12] MIPS: Octeon: Header and file cleaning. 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Hill" In preparation for new hotplug CPU, some housekeeping: * Clean-up header file dependencies, specifically move inclusion of some headers to only the files that need them. * Remove usage of arch/mips/cavium-octeon/octeon_boot.h * Clean-ups from checkpatch in arch/mips/cavium-octeon/setup.c * Add defining of NR_IRQS_LEGACY for completeness. * Move CVMX_TMP_STR macros from top level to cvmx-asm.h * Update some copyright dates. * Add some missing register include files to top level. Signed-off-by: Steven J. Hill Acked-by: David Daney --- .../cavium-octeon/executive/cvmx-helper-board.c | 2 +- .../cavium-octeon/executive/cvmx-helper-jtag.c | 1 + .../cavium-octeon/executive/cvmx-helper-rgmii.c | 1 + .../cavium-octeon/executive/cvmx-helper-sgmii.c | 1 + .../mips/cavium-octeon/executive/cvmx-helper-spi.c | 1 + .../cavium-octeon/executive/cvmx-helper-xaui.c | 1 + arch/mips/cavium-octeon/executive/cvmx-helper.c | 1 + arch/mips/cavium-octeon/executive/cvmx-pko.c | 1 + arch/mips/cavium-octeon/executive/cvmx-spi.c | 1 + arch/mips/cavium-octeon/octeon-platform.c | 1 + arch/mips/cavium-octeon/octeon_boot.h | 95 ---------------------- arch/mips/cavium-octeon/setup.c | 10 ++- arch/mips/cavium-octeon/smp.c | 17 ++-- arch/mips/include/asm/mach-cavium-octeon/irq.h | 8 ++ arch/mips/include/asm/octeon/cvmx-asm.h | 6 +- arch/mips/include/asm/octeon/cvmx-sysinfo.h | 4 +- arch/mips/include/asm/octeon/cvmx.h | 10 +-- 17 files changed, 42 insertions(+), 119 deletions(-) delete mode 100644 arch/mips/cavium-octeon/octeon_boot.h diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c index ab8362e..22d46fe 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -32,7 +32,7 @@ */ #include -#include +#include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c index 607b4e6..e417037 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c @@ -33,6 +33,7 @@ */ #include +#include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c index d18ed5a..2d84490 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c @@ -30,6 +30,7 @@ * and monitoring. */ #include +#include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 5782833..a25275d 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -31,6 +31,7 @@ */ #include +#include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index ef16aa0..d9dac21 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -34,6 +34,7 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index); * and monitoring. */ #include +#include #include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index 19d54e0..d692638 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -32,6 +32,7 @@ */ #include +#include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 75108ec..1e807f8 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -31,6 +31,7 @@ * */ #include +#include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c index 676fab5..ec5b013 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-pko.c +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -30,6 +30,7 @@ */ #include +#include #include #include diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c index f51957a..d346ea7 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c @@ -30,6 +30,7 @@ * Support library for the SPI */ #include +#include #include diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 8505db4..a605191 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -13,6 +13,7 @@ #include #include +#include #include #ifdef CONFIG_USB diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h deleted file mode 100644 index a6ce7c4..0000000 --- a/arch/mips/cavium-octeon/octeon_boot.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2004, 2005 Cavium Networks - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __OCTEON_BOOT_H__ -#define __OCTEON_BOOT_H__ - -#include - -struct boot_init_vector { - /* First stage address - in ram instead of flash */ - uint64_t code_addr; - /* Setup code for application, NOT application entry point */ - uint32_t app_start_func_addr; - /* k0 is used for global data - needs to be passed to other cores */ - uint32_t k0_val; - /* Address of boot info block structure */ - uint64_t boot_info_addr; - uint32_t flags; /* flags */ - uint32_t pad; -}; - -/* similar to bootloader's linux_app_boot_info but without global data */ -struct linux_app_boot_info { -#ifdef __BIG_ENDIAN_BITFIELD - uint32_t labi_signature; - uint32_t start_core0_addr; - uint32_t avail_coremask; - uint32_t pci_console_active; - uint32_t icache_prefetch_disable; - uint32_t padding; - uint64_t InitTLBStart_addr; - uint32_t start_app_addr; - uint32_t cur_exception_base; - uint32_t no_mark_private_data; - uint32_t compact_flash_common_base_addr; - uint32_t compact_flash_attribute_base_addr; - uint32_t led_display_base_addr; -#else - uint32_t start_core0_addr; - uint32_t labi_signature; - - uint32_t pci_console_active; - uint32_t avail_coremask; - - uint32_t padding; - uint32_t icache_prefetch_disable; - - uint64_t InitTLBStart_addr; - - uint32_t cur_exception_base; - uint32_t start_app_addr; - - uint32_t compact_flash_common_base_addr; - uint32_t no_mark_private_data; - - uint32_t led_display_base_addr; - uint32_t compact_flash_attribute_base_addr; -#endif -}; - -/* If not to copy a lot of bootloader's structures - here is only offset of requested member */ -#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c - -/* hardcoded in bootloader */ -#define LABI_ADDR_IN_BOOTLOADER 0x700 - -#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot" - -#define LABI_SIGNATURE 0xAABBCC01 - -/* from uboot-headers/octeon_mem_map.h */ -#define EXCEPTION_BASE_INCR (4 * 1024) - /* Increment size for exception base addresses (4k minimum) */ -#define EXCEPTION_BASE_BASE 0 -#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800) -#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE) - -#endif /* __OCTEON_BOOT_H__ */ diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index a8034d0..2085138 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -39,6 +39,7 @@ #include #include +#include #include #include @@ -165,6 +166,7 @@ static int octeon_kexec_prepare(struct kimage *image) int argc = 0, offt; char *str = (char *)image->segment[i].buf; char *ptr = strchr(str, ' '); + while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { *ptr = '\0'; if (ptr[1] != ' ') { @@ -357,6 +359,7 @@ void octeon_write_lcd(const char *s) ioremap_nocache(octeon_bootinfo->led_display_base_addr, 8); int i; + for (i = 0; i < 8; i++, s++) { if (*s) iowrite8(*s, lcd_address + i); @@ -429,6 +432,7 @@ static void octeon_restart(char *command) /* Disable all watchdogs before soft reset. They don't get cleared */ #ifdef CONFIG_SMP int cpu; + for_each_online_cpu(cpu) cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); #else @@ -715,11 +719,13 @@ void __init prom_init(void) if (OCTEON_IS_OCTEON2()) { /* I/O clock runs at a different rate than the CPU. */ union cvmx_mio_rst_boot rst_boot; + rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; } else if (OCTEON_IS_OCTEON3()) { /* I/O clock runs at a different rate than the CPU. */ union cvmx_rst_boot rst_boot; + rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; } else { @@ -927,6 +933,7 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) { if (addr > *mem && addr < *mem + *size) { u64 inc = addr - *mem; + add_memory_region(*mem, inc, BOOT_MEM_RAM); *mem += inc; *size -= inc; @@ -947,6 +954,7 @@ void __init fw_init_cmdline(void) for (i = 0; i < octeon_boot_desc_ptr->argc; i++) { const char *arg = cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); + if (strlen(arcs_cmdline) + strlen(arg) + 1 < sizeof(arcs_cmdline) - 1) { strcat(arcs_cmdline, " "); @@ -1202,7 +1210,7 @@ void __init device_tree_init(void) init_octeon_system_type(); } -static int __initdata disable_octeon_edac_p; +static int disable_octeon_edac_p __initdata; static int __init disable_octeon_edac(char *str) { diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 75e7c86..01da400 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -24,11 +24,11 @@ #include "octeon_boot.h" -volatile unsigned long octeon_processor_boot = 0xff; -volatile unsigned long octeon_processor_sp; -volatile unsigned long octeon_processor_gp; +unsigned long octeon_processor_boot = 0xff; +unsigned long octeon_processor_sp; +unsigned long octeon_processor_gp; #ifdef CONFIG_RELOCATABLE -volatile unsigned long octeon_processor_relocated_kernel_entry; +unsigned long octeon_processor_relocated_kernel_entry; #endif /* CONFIG_RELOCATABLE */ #ifdef CONFIG_HOTPLUG_CPU @@ -36,8 +36,6 @@ uint64_t octeon_bootloader_entry_addr; EXPORT_SYMBOL(octeon_bootloader_entry_addr); #endif -extern void kernel_entry(unsigned long arg1, ...); - static void octeon_icache_flush(void) { asm volatile ("synci 0($0)\n"); @@ -98,10 +96,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id) void octeon_send_ipi_single(int cpu, unsigned int action) { int coreid = cpu_logical_map(cpu); - /* - pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, - coreid, action); - */ + cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); } @@ -148,7 +143,7 @@ static void __init octeon_smp_setup(void) #endif /* The present CPUs are initially just the boot cpu (CPU 0). */ - for (id = 0; id < NR_CPUS; id++) { + for (id = 0; id < num_possible_cpus(); id++) { set_cpu_possible(id, id == 0); set_cpu_present(id, id == 0); } diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 64b86b9..7c2bf76 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -11,6 +11,14 @@ #define NR_IRQS OCTEON_IRQ_LAST #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 +/* + * 0 - unused. + * 1..8 - MIPS + * + * For a total of 9 + */ +#define NR_IRQS_LEGACY 9 + enum octeon_irq { /* 1 - 8 represent the 8 MIPS standard interrupt sources */ OCTEON_IRQ_SW0 = 1, diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h index 31eacc2..0c6ae93 100644 --- a/arch/mips/include/asm/octeon/cvmx-asm.h +++ b/arch/mips/include/asm/octeon/cvmx-asm.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2017 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -32,7 +32,9 @@ #ifndef __CVMX_ASM_H__ #define __CVMX_ASM_H__ -#include +/* turn the variable name into a string */ +#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) +#define CVMX_TMP_STR2(x) #x /* other useful stuff */ #define CVMX_SYNC asm volatile ("sync" : : : "memory") diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h index c6c3ee3..ea1381a 100644 --- a/arch/mips/include/asm/octeon/cvmx-sysinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2016 Cavium, Inc. + * Copyright (c) 2003-2017 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -32,7 +32,7 @@ #ifndef __CVMX_SYSINFO_H__ #define __CVMX_SYSINFO_H__ -#include "cvmx-coremask.h" +#include #define OCTEON_SERIAL_LEN 20 /** diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index 25854abc..392556a 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h @@ -54,8 +54,7 @@ enum cvmx_mips_space { #endif #include -#include -#include +#include #include #include @@ -68,8 +67,9 @@ enum cvmx_mips_space { #include #include #include +#include +#include -#include #include #include @@ -102,10 +102,6 @@ static inline uint32_t cvmx_get_proc_id(void) return id; } -/* turn the variable name into a string */ -#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) -#define CVMX_TMP_STR2(x) #x - /** * Builds a bit mask given the required size in bits. * -- 2.1.4