* [PATCH libdrm 1/4] amdgpu: add sync_file import and export functions
@ 2017-09-28 22:10 Marek Olšák
[not found] ` <1506636659-24517-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Marek Olšák @ 2017-09-28 22:10 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Marek Olšák <marek.olsak@amd.com>
v2: update amdgpu-symbol-check
---
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++
amdgpu/amdgpu_cs.c | 20 ++++++++++++++++++++
3 files changed, 52 insertions(+)
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index c5b85b5..bc9ed3f 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -33,20 +33,22 @@ amdgpu_cs_ctx_create
amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
+amdgpu_cs_syncobj_export_sync_file
+amdgpu_cs_syncobj_import_sync_file
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
amdgpu_device_initialize
amdgpu_get_marketing_name
amdgpu_query_buffer_size_alignment
amdgpu_query_crtc_from_id
amdgpu_query_firmware_version
amdgpu_query_gds_info
amdgpu_query_gpu_info
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 238b1aa..b44b9b6 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1376,20 +1376,50 @@ int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
int shared_fd,
uint32_t *syncobj);
/**
+ * Export kernel sync object to a sync_file.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [in] sync object handle
+ * \param sync_file_fd - \c [out] sync_file file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd);
+
+/**
+ * Import kernel sync object from a sync_file.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [in] sync object handle
+ * \param sync_file_fd - \c [in] sync_file file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
* \param context - \c [in] context handle for context id
* \param bo_list_handle - \c [in] request bo list handle (0 for none)
* \param num_chunks - \c [in] number of CS chunks to submit
* \param chunks - \c [in] array of CS chunks
* \param seq_no - \c [out] output sequence number for submission.
*
* \return 0 on success\n
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index dfba875..4a05536 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -628,20 +628,40 @@ int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
int shared_fd,
uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
}
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
amdgpu_context_handle context,
amdgpu_bo_list_handle bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no)
{
union drm_amdgpu_cs cs = {0};
uint64_t *chunk_array;
int i, r;
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper
[not found] ` <1506636659-24517-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-09-28 22:10 ` Marek Olšák
[not found] ` <1506636659-24517-2-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-28 22:10 ` [PATCH libdrm 3/4] amdgpu: add amdgpu_cs_syncobj_wait Marek Olšák
2017-09-28 22:10 ` [PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle Marek Olšák
2 siblings, 1 reply; 8+ messages in thread
From: Marek Olšák @ 2017-09-28 22:10 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Marek Olšák <marek.olsak@amd.com>
---
include/drm/drm.h | 24 ++++++++++++++++++++++++
xf86drm.c | 22 ++++++++++++++++++++++
xf86drm.h | 3 +++
3 files changed, 49 insertions(+)
diff --git a/include/drm/drm.h b/include/drm/drm.h
index bf3674a..4da1667 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -687,38 +687,57 @@ struct drm_prime_handle {
/** Flags.. only applicable for handle->fd */
__u32 flags;
/** Returned dmabuf file descriptor */
__s32 fd;
};
struct drm_syncobj_create {
__u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
__u32 flags;
};
struct drm_syncobj_destroy {
__u32 handle;
__u32 pad;
};
#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
struct drm_syncobj_handle {
__u32 handle;
__u32 flags;
__s32 fd;
__u32 pad;
};
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct drm_syncobj_wait {
+ __u64 handles;
+ /* absolute timeout */
+ __s64 timeout_nsec;
+ __u32 count_handles;
+ __u32 flags;
+ __u32 first_signaled; /* only valid when not waiting all */
+ __u32 pad;
+};
+
+struct drm_syncobj_array {
+ __u64 handles;
+ __u32 count_handles;
+ __u32 pad;
+};
+
#if defined(__cplusplus)
}
#endif
#include "drm_mode.h"
#if defined(__cplusplus)
extern "C" {
#endif
@@ -827,20 +846,23 @@ extern "C" {
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
+#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
+#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
* Generic IOCTLS restart at 0xA0.
*
* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
* drmCommandReadWrite().
*/
#define DRM_COMMAND_BASE 0x40
@@ -869,20 +891,21 @@ struct drm_event {
struct drm_event_vblank {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 sequence;
__u32 crtc_id; /* 0 on older kernels that do not support this */
};
/* typedef area */
+#ifndef __KERNEL__
typedef struct drm_clip_rect drm_clip_rect_t;
typedef struct drm_drawable_info drm_drawable_info_t;
typedef struct drm_tex_region drm_tex_region_t;
typedef struct drm_hw_lock drm_hw_lock_t;
typedef struct drm_version drm_version_t;
typedef struct drm_unique drm_unique_t;
typedef struct drm_list drm_list_t;
typedef struct drm_block drm_block_t;
typedef struct drm_control drm_control_t;
typedef enum drm_map_type drm_map_type_t;
@@ -910,16 +933,17 @@ typedef struct drm_draw drm_draw_t;
typedef struct drm_update_draw drm_update_draw_t;
typedef struct drm_auth drm_auth_t;
typedef struct drm_irq_busid drm_irq_busid_t;
typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
typedef struct drm_agp_buffer drm_agp_buffer_t;
typedef struct drm_agp_binding drm_agp_binding_t;
typedef struct drm_agp_info drm_agp_info_t;
typedef struct drm_scatter_gather drm_scatter_gather_t;
typedef struct drm_set_version drm_set_version_t;
+#endif
#if defined(__cplusplus)
}
#endif
#endif
diff --git a/xf86drm.c b/xf86drm.c
index 6ea0112..8a32717 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4218,10 +4218,32 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd)
memclear(args);
args.fd = -1;
args.handle = handle;
args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE;
ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args);
if (ret)
return ret;
*sync_file_fd = args.fd;
return 0;
}
+
+int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
+{
+ struct drm_syncobj_wait args;
+ int ret;
+
+ memclear(args);
+ args.handles = (intptr_t)handles;
+ args.timeout_nsec = timeout_nsec;
+ args.count_handles = num_handles;
+ args.flags = flags;
+
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args);
+ if (ret < 0)
+ return ret;
+
+ if (first_signaled)
+ *first_signaled = args.first_signaled;
+ return ret;
+}
diff --git a/xf86drm.h b/xf86drm.h
index 2855a3e..ea650ef 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -853,16 +853,19 @@ extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_device
extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b);
extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);
extern int drmSyncobjDestroy(int fd, uint32_t handle);
extern int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd);
extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle);
extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd);
extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd);
+extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled);
#if defined(__cplusplus)
}
#endif
#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH libdrm 3/4] amdgpu: add amdgpu_cs_syncobj_wait
[not found] ` <1506636659-24517-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-28 22:10 ` [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper Marek Olšák
@ 2017-09-28 22:10 ` Marek Olšák
2017-09-28 22:10 ` [PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle Marek Olšák
2 siblings, 0 replies; 8+ messages in thread
From: Marek Olšák @ 2017-09-28 22:10 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Marek Olšák <marek.olsak@amd.com>
v2: update amdgpu-symbol-check
---
amdgpu/amdgpu-symbol-check | 1 +
amdgpu/amdgpu.h | 20 ++++++++++++++++++++
amdgpu/amdgpu_cs.c | 12 ++++++++++++
3 files changed, 33 insertions(+)
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index bc9ed3f..7ecfc98 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -35,20 +35,21 @@ amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
amdgpu_cs_syncobj_export_sync_file
amdgpu_cs_syncobj_import_sync_file
+amdgpu_cs_syncobj_wait
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
amdgpu_device_initialize
amdgpu_get_marketing_name
amdgpu_query_buffer_size_alignment
amdgpu_query_crtc_from_id
amdgpu_query_firmware_version
amdgpu_query_gds_info
amdgpu_query_gpu_info
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index b44b9b6..979acfc 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1347,20 +1347,40 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
* \param syncobj - \c [in] sync object handle
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
uint32_t syncobj);
/**
+ * Wait for one or all sync objects to signal.
+ *
+ * \param dev - \c [in] self-explanatory
+ * \param handles - \c [in] array of sync object handles
+ * \param num_handles - \c [in] self-explanatory
+ * \param timeout_nsec - \c [in] self-explanatory
+ * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
+ * \param first_signaled - \c [in] self-explanatory
+ *
+ * \return 0 on success\n
+ * -ETIME - Timeout
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled);
+
+/**
* Export kernel sync object to shareable fd.
*
* \param dev - \c [in] device handle
* \param syncobj - \c [in] sync object handle
* \param shared_fd - \c [out] shared file descriptor.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 4a05536..2cde7bf 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -608,20 +608,32 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
uint32_t handle)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjDestroy(dev->fd, handle);
}
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjWait(dev->fd, handles, num_handles, timeout_nsec,
+ flags, first_signaled);
+}
+
int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
uint32_t handle,
int *shared_fd)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle
[not found] ` <1506636659-24517-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-28 22:10 ` [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper Marek Olšák
2017-09-28 22:10 ` [PATCH libdrm 3/4] amdgpu: add amdgpu_cs_syncobj_wait Marek Olšák
@ 2017-09-28 22:10 ` Marek Olšák
2 siblings, 0 replies; 8+ messages in thread
From: Marek Olšák @ 2017-09-28 22:10 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Marek Olšák <marek.olsak@amd.com>
v2: update amdgpu-symbol-check
---
amdgpu/amdgpu-symbol-check | 1 +
amdgpu/amdgpu.h | 14 ++++++++++++++
amdgpu/amdgpu_cs.c | 22 ++++++++++++++++++++++
include/drm/amdgpu_drm.h | 21 +++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 7ecfc98..d9f89ef 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -27,20 +27,21 @@ amdgpu_bo_wait_for_idle
amdgpu_create_bo_from_user_mem
amdgpu_cs_chunk_fence_info_to_data
amdgpu_cs_chunk_fence_to_dep
amdgpu_cs_create_semaphore
amdgpu_cs_create_syncobj
amdgpu_cs_ctx_create
amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
+amdgpu_cs_fence_to_handle
amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
amdgpu_cs_syncobj_export_sync_file
amdgpu_cs_syncobj_import_sync_file
amdgpu_cs_syncobj_wait
amdgpu_cs_wait_fences
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 979acfc..23cde10 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1426,20 +1426,34 @@ int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int sync_file_fd);
/**
+ * Export an amdgpu fence as a handle (syncobj or fd).
+ *
+ * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
+ * \param out_handle returned handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ */
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
* \param context - \c [in] context handle for context id
* \param bo_list_handle - \c [in] request bo list handle (0 for none)
* \param num_chunks - \c [in] number of CS chunks to submit
* \param chunks - \c [in] array of CS chunks
* \param seq_no - \c [out] output sequence number for submission.
*
* \return 0 on success\n
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 2cde7bf..9577d5c 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -706,10 +706,32 @@ void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
struct drm_amdgpu_cs_chunk_dep *dep)
{
dep->ip_type = fence->ip_type;
dep->ip_instance = fence->ip_instance;
dep->ring = fence->ring;
dep->ctx_id = fence->context->id;
dep->handle = fence->fence;
}
+
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle)
+{
+ union drm_amdgpu_fence_to_handle fth = {0};
+ int r;
+
+ fth.in.fence.ctx_id = fence->context->id;
+ fth.in.fence.ip_type = fence->ip_type;
+ fth.in.fence.ip_instance = fence->ip_instance;
+ fth.in.fence.ring = fence->ring;
+ fth.in.fence.seq_no = fence->fence;
+ fth.in.what = what;
+
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
+ &fth, sizeof(fth));
+ if (r == 0)
+ *out_handle = fth.out.handle;
+ return r;
+}
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d9aa4a3..00f1b81 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -45,55 +45,59 @@ extern "C" {
#define DRM_AMDGPU_CS 0x04
#define DRM_AMDGPU_INFO 0x05
#define DRM_AMDGPU_GEM_METADATA 0x06
#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
#define DRM_AMDGPU_GEM_VA 0x08
#define DRM_AMDGPU_WAIT_CS 0x09
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
#define DRM_AMDGPU_VM 0x13
+#define DRM_AMDGPU_FENCE_TO_HANDLE 0x15
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
+#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
#define AMDGPU_GEM_DOMAIN_VRAM 0x4
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
/* Flag that CPU access will not work, this VRAM domain is invisible */
#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
/* Flag that USWC attributes should be used for GTT */
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag that the memory should be in VRAM and cleared */
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
/* Flag that create shadow bo(GTT) while allocating vram bo */
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
+/* Flag that BO is always valid in this VM */
+#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
__u64 bo_size;
/** physical start_addr alignment in bytes for some HW requirements */
__u64 alignment;
/** the requested memory domains */
__u64 domains;
/** allocation flags */
__u64 domain_flags;
@@ -506,20 +510,34 @@ struct drm_amdgpu_cs_chunk_dep {
struct drm_amdgpu_cs_chunk_fence {
__u32 handle;
__u32 offset;
};
struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
+
+union drm_amdgpu_fence_to_handle {
+ struct {
+ struct drm_amdgpu_fence fence;
+ __u32 what;
+ } in;
+ struct {
+ __u32 handle;
+ } out;
+};
+
struct drm_amdgpu_cs_chunk_data {
union {
struct drm_amdgpu_cs_chunk_ib ib_data;
struct drm_amdgpu_cs_chunk_fence fence_data;
};
};
/**
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
*
@@ -757,20 +775,21 @@ struct drm_amdgpu_info_device {
__u32 pci_rev;
__u32 family;
__u32 num_shader_engines;
__u32 num_shader_arrays_per_engine;
/* in KHz */
__u32 gpu_counter_freq;
__u64 max_engine_clock;
__u64 max_memory_clock;
/* cu information */
__u32 cu_active_number;
+ /* NOTE: cu_ao_mask is INVALID, DON'T use it */
__u32 cu_ao_mask;
__u32 cu_bitmap[4][4];
/** Render backend pipe mask. One render backend is CB+DB. */
__u32 enabled_rb_pipes_mask;
__u32 num_rb_pipes;
__u32 num_hw_gfx_contexts;
__u32 _pad;
__u64 ids_flags;
/** Starting virtual address for UMDs. */
__u64 virtual_address_offset;
@@ -811,20 +830,22 @@ struct drm_amdgpu_info_device {
__u32 num_cu_per_sh;
/* number of tcc blocks*/
__u32 num_tcc_blocks;
/* gs vgt table depth*/
__u32 gs_vgt_table_depth;
/* gs primitive buffer depth*/
__u32 gs_prim_buffer_depth;
/* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
+ /* always on cu bitmap */
+ __u32 cu_ao_bitmap[4][4];
};
struct drm_amdgpu_info_hw_ip {
/** Version of h/w IP */
__u32 hw_ip_version_major;
__u32 hw_ip_version_minor;
/** Capabilities */
__u64 capabilities_flags;
/** command buffer address start alignment*/
__u32 ib_start_alignment;
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper
[not found] ` <1506636659-24517-2-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-09-29 2:12 ` Chunming Zhou
[not found] ` <942bab23-5052-521a-b213-eaa1658e669d-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Chunming Zhou @ 2017-09-29 2:12 UTC (permalink / raw)
To: Marek Olšák, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 2017年09月29日 06:10, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> ---
> include/drm/drm.h | 24 ++++++++++++++++++++++++
> xf86drm.c | 22 ++++++++++++++++++++++
> xf86drm.h | 3 +++
> 3 files changed, 49 insertions(+)
>
> diff --git a/include/drm/drm.h b/include/drm/drm.h
> index bf3674a..4da1667 100644
> --- a/include/drm/drm.h
> +++ b/include/drm/drm.h
> @@ -687,38 +687,57 @@ struct drm_prime_handle {
>
> /** Flags.. only applicable for handle->fd */
> __u32 flags;
>
> /** Returned dmabuf file descriptor */
> __s32 fd;
> };
>
> struct drm_syncobj_create {
> __u32 handle;
> +#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
> __u32 flags;
> };
>
> struct drm_syncobj_destroy {
> __u32 handle;
> __u32 pad;
> };
>
> #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
> #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
Typo for '(1 << 1)' ?
With that fixes, the set is Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
> struct drm_syncobj_handle {
> __u32 handle;
> __u32 flags;
>
> __s32 fd;
> __u32 pad;
> };
>
> +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
> +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
> +struct drm_syncobj_wait {
> + __u64 handles;
> + /* absolute timeout */
> + __s64 timeout_nsec;
> + __u32 count_handles;
> + __u32 flags;
> + __u32 first_signaled; /* only valid when not waiting all */
> + __u32 pad;
> +};
> +
> +struct drm_syncobj_array {
> + __u64 handles;
> + __u32 count_handles;
> + __u32 pad;
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
>
> #include "drm_mode.h"
>
> #if defined(__cplusplus)
> extern "C" {
> #endif
>
> @@ -827,20 +846,23 @@ extern "C" {
> #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
> #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
> #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
> #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
> #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
>
> #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
> #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
> #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
> #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
> +#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
> +#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
> +#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
>
> /**
> * Device specific ioctls should only be in their respective headers
> * The device specific ioctl range is from 0x40 to 0x9f.
> * Generic IOCTLS restart at 0xA0.
> *
> * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
> * drmCommandReadWrite().
> */
> #define DRM_COMMAND_BASE 0x40
> @@ -869,20 +891,21 @@ struct drm_event {
> struct drm_event_vblank {
> struct drm_event base;
> __u64 user_data;
> __u32 tv_sec;
> __u32 tv_usec;
> __u32 sequence;
> __u32 crtc_id; /* 0 on older kernels that do not support this */
> };
>
> /* typedef area */
> +#ifndef __KERNEL__
> typedef struct drm_clip_rect drm_clip_rect_t;
> typedef struct drm_drawable_info drm_drawable_info_t;
> typedef struct drm_tex_region drm_tex_region_t;
> typedef struct drm_hw_lock drm_hw_lock_t;
> typedef struct drm_version drm_version_t;
> typedef struct drm_unique drm_unique_t;
> typedef struct drm_list drm_list_t;
> typedef struct drm_block drm_block_t;
> typedef struct drm_control drm_control_t;
> typedef enum drm_map_type drm_map_type_t;
> @@ -910,16 +933,17 @@ typedef struct drm_draw drm_draw_t;
> typedef struct drm_update_draw drm_update_draw_t;
> typedef struct drm_auth drm_auth_t;
> typedef struct drm_irq_busid drm_irq_busid_t;
> typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
>
> typedef struct drm_agp_buffer drm_agp_buffer_t;
> typedef struct drm_agp_binding drm_agp_binding_t;
> typedef struct drm_agp_info drm_agp_info_t;
> typedef struct drm_scatter_gather drm_scatter_gather_t;
> typedef struct drm_set_version drm_set_version_t;
> +#endif
>
> #if defined(__cplusplus)
> }
> #endif
>
> #endif
> diff --git a/xf86drm.c b/xf86drm.c
> index 6ea0112..8a32717 100644
> --- a/xf86drm.c
> +++ b/xf86drm.c
> @@ -4218,10 +4218,32 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd)
> memclear(args);
> args.fd = -1;
> args.handle = handle;
> args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE;
> ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args);
> if (ret)
> return ret;
> *sync_file_fd = args.fd;
> return 0;
> }
> +
> +int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
> + int64_t timeout_nsec, unsigned flags,
> + uint32_t *first_signaled)
> +{
> + struct drm_syncobj_wait args;
> + int ret;
> +
> + memclear(args);
> + args.handles = (intptr_t)handles;
> + args.timeout_nsec = timeout_nsec;
> + args.count_handles = num_handles;
> + args.flags = flags;
> +
> + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args);
> + if (ret < 0)
> + return ret;
> +
> + if (first_signaled)
> + *first_signaled = args.first_signaled;
> + return ret;
> +}
> diff --git a/xf86drm.h b/xf86drm.h
> index 2855a3e..ea650ef 100644
> --- a/xf86drm.h
> +++ b/xf86drm.h
> @@ -853,16 +853,19 @@ extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_device
>
> extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b);
>
> extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);
> extern int drmSyncobjDestroy(int fd, uint32_t handle);
> extern int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd);
> extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle);
>
> extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd);
> extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd);
> +extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
> + int64_t timeout_nsec, unsigned flags,
> + uint32_t *first_signaled);
>
> #if defined(__cplusplus)
> }
> #endif
>
> #endif
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper
[not found] ` <942bab23-5052-521a-b213-eaa1658e669d-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-29 12:37 ` Marek Olšák
[not found] ` <CAAxE2A7mqNMJkr2Z0zsJwBqzQWm+a0hqmFn+J5ZnsdF4bW78qQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Marek Olšák @ 2017-09-29 12:37 UTC (permalink / raw)
To: Chunming Zhou; +Cc: amd-gfx mailing list
On Fri, Sep 29, 2017 at 4:12 AM, Chunming Zhou <zhoucm1@amd.com> wrote:
>
>
> On 2017年09月29日 06:10, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak@amd.com>
>>
>> ---
>> include/drm/drm.h | 24 ++++++++++++++++++++++++
>> xf86drm.c | 22 ++++++++++++++++++++++
>> xf86drm.h | 3 +++
>> 3 files changed, 49 insertions(+)
>>
>> diff --git a/include/drm/drm.h b/include/drm/drm.h
>> index bf3674a..4da1667 100644
>> --- a/include/drm/drm.h
>> +++ b/include/drm/drm.h
>> @@ -687,38 +687,57 @@ struct drm_prime_handle {
>> /** Flags.. only applicable for handle->fd */
>> __u32 flags;
>> /** Returned dmabuf file descriptor */
>> __s32 fd;
>> };
>> struct drm_syncobj_create {
>> __u32 handle;
>> +#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
>> __u32 flags;
>> };
>> struct drm_syncobj_destroy {
>> __u32 handle;
>> __u32 pad;
>> };
>> #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
>> #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
>
> Typo for '(1 << 1)' ?
No, this was copied from kernel headers.
>
> With that fixes, the set is Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Thanks.
Marek
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper
[not found] ` <CAAxE2A7mqNMJkr2Z0zsJwBqzQWm+a0hqmFn+J5ZnsdF4bW78qQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-09-30 1:57 ` Chunming Zhou
0 siblings, 0 replies; 8+ messages in thread
From: Chunming Zhou @ 2017-09-30 1:57 UTC (permalink / raw)
To: Marek Olšák; +Cc: amd-gfx mailing list
On 2017年09月29日 20:37, Marek Olšák wrote:
> On Fri, Sep 29, 2017 at 4:12 AM, Chunming Zhou <zhoucm1@amd.com> wrote:
>>
>> On 2017年09月29日 06:10, Marek Olšák wrote:
>>> From: Marek Olšák <marek.olsak@amd.com>
>>>
>>> ---
>>> include/drm/drm.h | 24 ++++++++++++++++++++++++
>>> xf86drm.c | 22 ++++++++++++++++++++++
>>> xf86drm.h | 3 +++
>>> 3 files changed, 49 insertions(+)
>>>
>>> diff --git a/include/drm/drm.h b/include/drm/drm.h
>>> index bf3674a..4da1667 100644
>>> --- a/include/drm/drm.h
>>> +++ b/include/drm/drm.h
>>> @@ -687,38 +687,57 @@ struct drm_prime_handle {
>>> /** Flags.. only applicable for handle->fd */
>>> __u32 flags;
>>> /** Returned dmabuf file descriptor */
>>> __s32 fd;
>>> };
>>> struct drm_syncobj_create {
>>> __u32 handle;
>>> +#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
>>> __u32 flags;
>>> };
>>> struct drm_syncobj_destroy {
>>> __u32 handle;
>>> __u32 pad;
>>> };
>>> #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
>>> #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
>> Typo for '(1 << 1)' ?
> No, this was copied from kernel headers.
Yes, I double checked just now, that's two separate ioctls use them, so
they are safe.
Sorry for noise of this.
David Zhou
>
>> With that fixes, the set is Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
> Thanks.
>
> Marek
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle
2017-09-12 20:43 [PATCH libdrm 1/4] amdgpu: add sync_file import and export functions Marek Olšák
@ 2017-09-12 20:43 ` Marek Olšák
0 siblings, 0 replies; 8+ messages in thread
From: Marek Olšák @ 2017-09-12 20:43 UTC (permalink / raw)
To: dri-devel, amd-gfx
From: Marek Olšák <marek.olsak@amd.com>
---
amdgpu/amdgpu.h | 14 ++++++++++++++
amdgpu/amdgpu_cs.c | 22 ++++++++++++++++++++++
include/drm/amdgpu_drm.h | 21 +++++++++++++++++++++
3 files changed, 57 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 979acfc..23cde10 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1433,6 +1433,20 @@ int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
int sync_file_fd);
/**
+ * Export an amdgpu fence as a handle (syncobj or fd).
+ *
+ * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
+ * \param out_handle returned handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ */
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 2cde7bf..9577d5c 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -713,3 +713,25 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
dep->ctx_id = fence->context->id;
dep->handle = fence->fence;
}
+
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle)
+{
+ union drm_amdgpu_fence_to_handle fth = {0};
+ int r;
+
+ fth.in.fence.ctx_id = fence->context->id;
+ fth.in.fence.ip_type = fence->ip_type;
+ fth.in.fence.ip_instance = fence->ip_instance;
+ fth.in.fence.ring = fence->ring;
+ fth.in.fence.seq_no = fence->fence;
+ fth.in.what = what;
+
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
+ &fth, sizeof(fth));
+ if (r == 0)
+ *out_handle = fth.out.handle;
+ return r;
+}
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d9aa4a3..00f1b81 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -52,6 +52,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
#define DRM_AMDGPU_VM 0x13
+#define DRM_AMDGPU_FENCE_TO_HANDLE 0x15
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -67,6 +68,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
+#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -87,6 +89,8 @@ extern "C" {
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
+/* Flag that BO is always valid in this VM */
+#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -513,6 +517,20 @@ struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
+
+union drm_amdgpu_fence_to_handle {
+ struct {
+ struct drm_amdgpu_fence fence;
+ __u32 what;
+ } in;
+ struct {
+ __u32 handle;
+ } out;
+};
+
struct drm_amdgpu_cs_chunk_data {
union {
struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -764,6 +782,7 @@ struct drm_amdgpu_info_device {
__u64 max_memory_clock;
/* cu information */
__u32 cu_active_number;
+ /* NOTE: cu_ao_mask is INVALID, DON'T use it */
__u32 cu_ao_mask;
__u32 cu_bitmap[4][4];
/** Render backend pipe mask. One render backend is CB+DB. */
@@ -818,6 +837,8 @@ struct drm_amdgpu_info_device {
/* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
+ /* always on cu bitmap */
+ __u32 cu_ao_bitmap[4][4];
};
struct drm_amdgpu_info_hw_ip {
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-09-30 1:57 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-28 22:10 [PATCH libdrm 1/4] amdgpu: add sync_file import and export functions Marek Olšák
[not found] ` <1506636659-24517-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-28 22:10 ` [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper Marek Olšák
[not found] ` <1506636659-24517-2-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-29 2:12 ` Chunming Zhou
[not found] ` <942bab23-5052-521a-b213-eaa1658e669d-5C7GfCeVMHo@public.gmane.org>
2017-09-29 12:37 ` Marek Olšák
[not found] ` <CAAxE2A7mqNMJkr2Z0zsJwBqzQWm+a0hqmFn+J5ZnsdF4bW78qQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-30 1:57 ` Chunming Zhou
2017-09-28 22:10 ` [PATCH libdrm 3/4] amdgpu: add amdgpu_cs_syncobj_wait Marek Olšák
2017-09-28 22:10 ` [PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle Marek Olšák
-- strict thread matches above, loose matches on Subject: below --
2017-09-12 20:43 [PATCH libdrm 1/4] amdgpu: add sync_file import and export functions Marek Olšák
2017-09-12 20:43 ` [PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle Marek Olšák
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