* [PATCH 1/2] drm/amdgpu: move struct amd_powerplay to amdgpu.h
@ 2017-09-29 10:02 Rex Zhu
[not found] ` <1506679340-31261-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Rex Zhu @ 2017-09-29 10:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Iea3b5ab620b5368888d1ab084ffc0859f44ffe7a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 7 -------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9090888..2204ff6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1396,6 +1396,13 @@ struct amdgpu_atcs {
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
+struct amd_powerplay {
+ struct cgs_device *cgs_device;
+ void *pp_handle;
+ const struct amd_ip_funcs *ip_funcs;
+ const struct amd_pm_funcs *pp_funcs;
+};
+
#define AMDGPU_RESET_MAGIC_NUM 64
struct amdgpu_device {
struct device *dev;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 006954e..47478e0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -122,12 +122,5 @@ struct pp_gpu_power {
support << PP_STATE_SUPPORT_SHIFT |\
state << PP_STATE_SHIFT)
-struct amd_powerplay {
- struct cgs_device *cgs_device;
- void *pp_handle;
- const struct amd_ip_funcs *ip_funcs;
- const struct amd_pm_funcs *pp_funcs;
-};
-
#endif /* _AMD_POWERPLAY_H_ */
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h
[not found] ` <1506679340-31261-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-29 10:02 ` Rex Zhu
[not found] ` <1506679340-31261-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Rex Zhu @ 2017-09-29 10:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
move powerplay and amdgpu shared structures
and definitions to kgd_pp_interface.h
Change-Id: I4272b7974edbff3395ba8a6efebb0decd0cdfa12
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 -
drivers/gpu/drm/amd/include/amd_shared.h | 172 -------------
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 289 ++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 93 +------
5 files changed, 293 insertions(+), 267 deletions(-)
create mode 100644 drivers/gpu/drm/amd/include/kgd_pp_interface.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2204ff6..1453aba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -47,6 +47,8 @@
#include <drm/amdgpu_drm.h>
#include <kgd_kfd_interface.h>
+#include "dm_pp_interface.h"
+#include "kgd_pp_interface.h"
#include "amd_shared.h"
#include "amdgpu_mode.h"
@@ -59,7 +61,6 @@
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
#include "amdgpu_vm.h"
-#include "amd_powerplay.h"
#include "amdgpu_dpm.h"
#include "amdgpu_acp.h"
#include "amdgpu_uvd.h"
@@ -67,11 +68,11 @@
#include "amdgpu_vcn.h"
#include "amdgpu_mn.h"
#include "amdgpu_dm.h"
-
#include "gpu_scheduler.h"
#include "amdgpu_virt.h"
#include "amdgpu_gart.h"
+
/*
* Modules parameters.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index f3b23f9..f3afa66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -30,7 +30,6 @@
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
-#include "amd_powerplay.h"
static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 0bcf2bc..3aecf1d 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -27,7 +27,6 @@
#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
-struct seq_file;
/*
* Chip flags
@@ -61,71 +60,12 @@ enum amd_clockgating_state {
AMD_CG_STATE_UNGATE,
};
-enum amd_dpm_forced_level {
- AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
- AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
- AMD_DPM_FORCED_LEVEL_LOW = 0x4,
- AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
- AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
- AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
- AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
-};
enum amd_powergating_state {
AMD_PG_STATE_GATE = 0,
AMD_PG_STATE_UNGATE,
};
-struct amd_vce_state {
- /* vce clocks */
- u32 evclk;
- u32 ecclk;
- /* gpu clocks */
- u32 sclk;
- u32 mclk;
- u8 clk_idx;
- u8 pstate;
-};
-
-
-#define AMD_MAX_VCE_LEVELS 6
-
-enum amd_vce_level {
- AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
- AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
- AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
- AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
- AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
- AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
-};
-
-enum amd_pp_profile_type {
- AMD_PP_GFX_PROFILE,
- AMD_PP_COMPUTE_PROFILE,
-};
-
-struct amd_pp_profile {
- enum amd_pp_profile_type type;
- uint32_t min_sclk;
- uint32_t min_mclk;
- uint16_t activity_threshold;
- uint8_t up_hyst;
- uint8_t down_hyst;
-};
-
-enum amd_fan_ctrl_mode {
- AMD_FAN_CTRL_NONE = 0,
- AMD_FAN_CTRL_MANUAL = 1,
- AMD_FAN_CTRL_AUTO = 2,
-};
-
-enum pp_clock_type {
- PP_SCLK,
- PP_MCLK,
- PP_PCIE,
-};
/* CG flags */
#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
@@ -169,27 +109,6 @@ enum pp_clock_type {
#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
#define AMD_PG_SUPPORT_MMHUB (1 << 13)
-enum amd_pm_state_type {
- /* not used for dpm */
- POWER_STATE_TYPE_DEFAULT,
- POWER_STATE_TYPE_POWERSAVE,
- /* user selectable states */
- POWER_STATE_TYPE_BATTERY,
- POWER_STATE_TYPE_BALANCED,
- POWER_STATE_TYPE_PERFORMANCE,
- /* internal states */
- POWER_STATE_TYPE_INTERNAL_UVD,
- POWER_STATE_TYPE_INTERNAL_UVD_SD,
- POWER_STATE_TYPE_INTERNAL_UVD_HD,
- POWER_STATE_TYPE_INTERNAL_UVD_HD2,
- POWER_STATE_TYPE_INTERNAL_UVD_MVC,
- POWER_STATE_TYPE_INTERNAL_BOOT,
- POWER_STATE_TYPE_INTERNAL_THERMAL,
- POWER_STATE_TYPE_INTERNAL_ACPI,
- POWER_STATE_TYPE_INTERNAL_ULV,
- POWER_STATE_TYPE_INTERNAL_3DPERF,
-};
-
struct amd_ip_funcs {
/* Name of IP block */
char *name;
@@ -233,95 +152,4 @@ struct amd_ip_funcs {
};
-enum amd_pp_task;
-enum amd_pp_clock_type;
-struct pp_states_info;
-struct amd_pp_simple_clock_info;
-struct amd_pp_display_configuration;
-struct amd_pp_clock_info;
-struct pp_display_clock_request;
-struct pp_wm_sets_with_clock_ranges_soc15;
-struct pp_clock_levels_with_voltage;
-struct pp_clock_levels_with_latency;
-struct amd_pp_clocks;
-
-struct amd_pm_funcs {
-/* export for dpm on ci and si */
- int (*pre_set_power_state)(void *handle);
- int (*set_power_state)(void *handle);
- void (*post_set_power_state)(void *handle);
- void (*display_configuration_changed)(void *handle);
- void (*print_power_state)(void *handle, void *ps);
- bool (*vblank_too_short)(void *handle);
- void (*enable_bapm)(void *handle, bool enable);
- int (*check_state_equal)(void *handle,
- void *cps,
- void *rps,
- bool *equal);
-/* export for sysfs */
- int (*get_temperature)(void *handle);
- void (*set_fan_control_mode)(void *handle, u32 mode);
- u32 (*get_fan_control_mode)(void *handle);
- int (*set_fan_speed_percent)(void *handle, u32 speed);
- int (*get_fan_speed_percent)(void *handle, u32 *speed);
- int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
- int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
- int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
- int (*get_sclk_od)(void *handle);
- int (*set_sclk_od)(void *handle, uint32_t value);
- int (*get_mclk_od)(void *handle);
- int (*set_mclk_od)(void *handle, uint32_t value);
- int (*read_sensor)(void *handle, int idx, void *value, int *size);
- enum amd_dpm_forced_level (*get_performance_level)(void *handle);
- enum amd_pm_state_type (*get_current_power_state)(void *handle);
- int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
- int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
- int (*get_pp_table)(void *handle, char **table);
- int (*set_pp_table)(void *handle, const char *buf, size_t size);
- void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
-
- int (*reset_power_profile_state)(void *handle,
- struct amd_pp_profile *request);
- int (*get_power_profile_state)(void *handle,
- struct amd_pp_profile *query);
- int (*set_power_profile_state)(void *handle,
- struct amd_pp_profile *request);
- int (*switch_power_profile)(void *handle,
- enum amd_pp_profile_type type);
-/* export to amdgpu */
- void (*powergate_uvd)(void *handle, bool gate);
- void (*powergate_vce)(void *handle, bool gate);
- struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx);
- int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
- void *input, void *output);
- int (*load_firmware)(void *handle);
- int (*wait_for_fw_loading_complete)(void *handle);
- int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
-/* export to DC */
- u32 (*get_sclk)(void *handle, bool low);
- u32 (*get_mclk)(void *handle, bool low);
- int (*display_configuration_change)(void *handle,
- const struct amd_pp_display_configuration *input);
- int (*get_display_power_level)(void *handle,
- struct amd_pp_simple_clock_info *output);
- int (*get_current_clocks)(void *handle,
- struct amd_pp_clock_info *clocks);
- int (*get_clock_by_type)(void *handle,
- enum amd_pp_clock_type type,
- struct amd_pp_clocks *clocks);
- int (*get_clock_by_type_with_latency)(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_latency *clocks);
- int (*get_clock_by_type_with_voltage)(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_voltage *clocks);
- int (*set_watermarks_for_clocks_ranges)(void *handle,
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
- int (*display_clock_voltage_request)(void *handle,
- struct pp_display_clock_request *clock);
- int (*get_display_mode_validation_clocks)(void *handle,
- struct amd_pp_simple_clock_info *clocks);
-};
-
-
#endif /* __AMD_SHARED_H__ */
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
new file mode 100644
index 0000000..f104668
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __KGD_PP_INTERFACE_H__
+#define __KGD_PP_INTERFACE_H__
+
+extern const struct amd_ip_funcs pp_ip_funcs;
+extern const struct amd_pm_funcs pp_dpm_funcs;
+
+struct amd_vce_state {
+ /* vce clocks */
+ u32 evclk;
+ u32 ecclk;
+ /* gpu clocks */
+ u32 sclk;
+ u32 mclk;
+ u8 clk_idx;
+ u8 pstate;
+};
+
+
+enum amd_dpm_forced_level {
+ AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
+ AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
+ AMD_DPM_FORCED_LEVEL_LOW = 0x4,
+ AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
+ AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
+ AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
+ AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
+};
+
+enum amd_pm_state_type {
+ /* not used for dpm */
+ POWER_STATE_TYPE_DEFAULT,
+ POWER_STATE_TYPE_POWERSAVE,
+ /* user selectable states */
+ POWER_STATE_TYPE_BATTERY,
+ POWER_STATE_TYPE_BALANCED,
+ POWER_STATE_TYPE_PERFORMANCE,
+ /* internal states */
+ POWER_STATE_TYPE_INTERNAL_UVD,
+ POWER_STATE_TYPE_INTERNAL_UVD_SD,
+ POWER_STATE_TYPE_INTERNAL_UVD_HD,
+ POWER_STATE_TYPE_INTERNAL_UVD_HD2,
+ POWER_STATE_TYPE_INTERNAL_UVD_MVC,
+ POWER_STATE_TYPE_INTERNAL_BOOT,
+ POWER_STATE_TYPE_INTERNAL_THERMAL,
+ POWER_STATE_TYPE_INTERNAL_ACPI,
+ POWER_STATE_TYPE_INTERNAL_ULV,
+ POWER_STATE_TYPE_INTERNAL_3DPERF,
+};
+
+#define AMD_MAX_VCE_LEVELS 6
+
+enum amd_vce_level {
+ AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
+ AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
+ AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
+ AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
+ AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
+ AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
+};
+
+enum amd_pp_profile_type {
+ AMD_PP_GFX_PROFILE,
+ AMD_PP_COMPUTE_PROFILE,
+};
+
+struct amd_pp_profile {
+ enum amd_pp_profile_type type;
+ uint32_t min_sclk;
+ uint32_t min_mclk;
+ uint16_t activity_threshold;
+ uint8_t up_hyst;
+ uint8_t down_hyst;
+};
+
+enum amd_fan_ctrl_mode {
+ AMD_FAN_CTRL_NONE = 0,
+ AMD_FAN_CTRL_MANUAL = 1,
+ AMD_FAN_CTRL_AUTO = 2,
+};
+
+enum pp_clock_type {
+ PP_SCLK,
+ PP_MCLK,
+ PP_PCIE,
+};
+
+enum amd_pp_sensors {
+ AMDGPU_PP_SENSOR_GFX_SCLK = 0,
+ AMDGPU_PP_SENSOR_VDDNB,
+ AMDGPU_PP_SENSOR_VDDGFX,
+ AMDGPU_PP_SENSOR_UVD_VCLK,
+ AMDGPU_PP_SENSOR_UVD_DCLK,
+ AMDGPU_PP_SENSOR_VCE_ECCLK,
+ AMDGPU_PP_SENSOR_GPU_LOAD,
+ AMDGPU_PP_SENSOR_GFX_MCLK,
+ AMDGPU_PP_SENSOR_GPU_TEMP,
+ AMDGPU_PP_SENSOR_VCE_POWER,
+ AMDGPU_PP_SENSOR_UVD_POWER,
+ AMDGPU_PP_SENSOR_GPU_POWER,
+};
+
+enum amd_pp_task {
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
+ AMD_PP_TASK_ENABLE_USER_STATE,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ AMD_PP_TASK_COMPLETE_INIT,
+ AMD_PP_TASK_MAX
+};
+
+struct amd_pp_init {
+ struct cgs_device *device;
+ uint32_t chip_family;
+ uint32_t chip_id;
+ bool pm_en;
+ uint32_t feature_mask;
+};
+
+
+
+enum {
+ PP_GROUP_UNKNOWN = 0,
+ PP_GROUP_GFX = 1,
+ PP_GROUP_SYS,
+ PP_GROUP_MAX
+};
+
+struct pp_states_info {
+ uint32_t nums;
+ uint32_t states[16];
+};
+
+struct pp_gpu_power {
+ uint32_t vddc_power;
+ uint32_t vddci_power;
+ uint32_t max_gpu_power;
+ uint32_t average_gpu_power;
+};
+
+#define PP_GROUP_MASK 0xF0000000
+#define PP_GROUP_SHIFT 28
+
+#define PP_BLOCK_MASK 0x0FFFFF00
+#define PP_BLOCK_SHIFT 8
+
+#define PP_BLOCK_GFX_CG 0x01
+#define PP_BLOCK_GFX_MG 0x02
+#define PP_BLOCK_GFX_3D 0x04
+#define PP_BLOCK_GFX_RLC 0x08
+#define PP_BLOCK_GFX_CP 0x10
+#define PP_BLOCK_SYS_BIF 0x01
+#define PP_BLOCK_SYS_MC 0x02
+#define PP_BLOCK_SYS_ROM 0x04
+#define PP_BLOCK_SYS_DRM 0x08
+#define PP_BLOCK_SYS_HDP 0x10
+#define PP_BLOCK_SYS_SDMA 0x20
+
+#define PP_STATE_MASK 0x0000000F
+#define PP_STATE_SHIFT 0
+#define PP_STATE_SUPPORT_MASK 0x000000F0
+#define PP_STATE_SUPPORT_SHIFT 0
+
+#define PP_STATE_CG 0x01
+#define PP_STATE_LS 0x02
+#define PP_STATE_DS 0x04
+#define PP_STATE_SD 0x08
+#define PP_STATE_SUPPORT_CG 0x10
+#define PP_STATE_SUPPORT_LS 0x20
+#define PP_STATE_SUPPORT_DS 0x40
+#define PP_STATE_SUPPORT_SD 0x80
+
+#define PP_CG_MSG_ID(group, block, support, state) \
+ ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
+ (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
+
+struct seq_file;
+enum amd_pp_clock_type;
+struct amd_pp_simple_clock_info;
+struct amd_pp_display_configuration;
+struct amd_pp_clock_info;
+struct pp_display_clock_request;
+struct pp_wm_sets_with_clock_ranges_soc15;
+struct pp_clock_levels_with_voltage;
+struct pp_clock_levels_with_latency;
+struct amd_pp_clocks;
+
+struct amd_pm_funcs {
+/* export for dpm on ci and si */
+ int (*pre_set_power_state)(void *handle);
+ int (*set_power_state)(void *handle);
+ void (*post_set_power_state)(void *handle);
+ void (*display_configuration_changed)(void *handle);
+ void (*print_power_state)(void *handle, void *ps);
+ bool (*vblank_too_short)(void *handle);
+ void (*enable_bapm)(void *handle, bool enable);
+ int (*check_state_equal)(void *handle,
+ void *cps,
+ void *rps,
+ bool *equal);
+/* export for sysfs */
+ int (*get_temperature)(void *handle);
+ void (*set_fan_control_mode)(void *handle, u32 mode);
+ u32 (*get_fan_control_mode)(void *handle);
+ int (*set_fan_speed_percent)(void *handle, u32 speed);
+ int (*get_fan_speed_percent)(void *handle, u32 *speed);
+ int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
+ int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
+ int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
+ int (*get_sclk_od)(void *handle);
+ int (*set_sclk_od)(void *handle, uint32_t value);
+ int (*get_mclk_od)(void *handle);
+ int (*set_mclk_od)(void *handle, uint32_t value);
+ int (*read_sensor)(void *handle, int idx, void *value, int *size);
+ enum amd_dpm_forced_level (*get_performance_level)(void *handle);
+ enum amd_pm_state_type (*get_current_power_state)(void *handle);
+ int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
+ int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
+ int (*get_pp_table)(void *handle, char **table);
+ int (*set_pp_table)(void *handle, const char *buf, size_t size);
+ void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
+
+ int (*reset_power_profile_state)(void *handle,
+ struct amd_pp_profile *request);
+ int (*get_power_profile_state)(void *handle,
+ struct amd_pp_profile *query);
+ int (*set_power_profile_state)(void *handle,
+ struct amd_pp_profile *request);
+ int (*switch_power_profile)(void *handle,
+ enum amd_pp_profile_type type);
+/* export to amdgpu */
+ void (*powergate_uvd)(void *handle, bool gate);
+ void (*powergate_vce)(void *handle, bool gate);
+ struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
+ int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
+ void *input, void *output);
+ int (*load_firmware)(void *handle);
+ int (*wait_for_fw_loading_complete)(void *handle);
+ int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
+/* export to DC */
+ u32 (*get_sclk)(void *handle, bool low);
+ u32 (*get_mclk)(void *handle, bool low);
+ int (*display_configuration_change)(void *handle,
+ const struct amd_pp_display_configuration *input);
+ int (*get_display_power_level)(void *handle,
+ struct amd_pp_simple_clock_info *output);
+ int (*get_current_clocks)(void *handle,
+ struct amd_pp_clock_info *clocks);
+ int (*get_clock_by_type)(void *handle,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
+ int (*get_clock_by_type_with_latency)(void *handle,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_latency *clocks);
+ int (*get_clock_by_type_with_voltage)(void *handle,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks);
+ int (*set_watermarks_for_clocks_ranges)(void *handle,
+ struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+ int (*display_clock_voltage_request)(void *handle,
+ struct pp_display_clock_request *clock);
+ int (*get_display_mode_validation_clocks)(void *handle,
+ struct amd_pp_simple_clock_info *clocks);
+};
+
+#endif
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 47478e0..152e70d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -29,98 +29,7 @@
#include "amd_shared.h"
#include "cgs_common.h"
#include "dm_pp_interface.h"
-
-extern const struct amd_ip_funcs pp_ip_funcs;
-extern const struct amd_pm_funcs pp_dpm_funcs;
-
-enum amd_pp_sensors {
- AMDGPU_PP_SENSOR_GFX_SCLK = 0,
- AMDGPU_PP_SENSOR_VDDNB,
- AMDGPU_PP_SENSOR_VDDGFX,
- AMDGPU_PP_SENSOR_UVD_VCLK,
- AMDGPU_PP_SENSOR_UVD_DCLK,
- AMDGPU_PP_SENSOR_VCE_ECCLK,
- AMDGPU_PP_SENSOR_GPU_LOAD,
- AMDGPU_PP_SENSOR_GFX_MCLK,
- AMDGPU_PP_SENSOR_GPU_TEMP,
- AMDGPU_PP_SENSOR_VCE_POWER,
- AMDGPU_PP_SENSOR_UVD_POWER,
- AMDGPU_PP_SENSOR_GPU_POWER,
-};
-
-enum amd_pp_task {
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
- AMD_PP_TASK_ENABLE_USER_STATE,
- AMD_PP_TASK_READJUST_POWER_STATE,
- AMD_PP_TASK_COMPLETE_INIT,
- AMD_PP_TASK_MAX
-};
-
-struct amd_pp_init {
- struct cgs_device *device;
- uint32_t chip_family;
- uint32_t chip_id;
- bool pm_en;
- uint32_t feature_mask;
-};
-
-
-
-enum {
- PP_GROUP_UNKNOWN = 0,
- PP_GROUP_GFX = 1,
- PP_GROUP_SYS,
- PP_GROUP_MAX
-};
-
-struct pp_states_info {
- uint32_t nums;
- uint32_t states[16];
-};
-
-struct pp_gpu_power {
- uint32_t vddc_power;
- uint32_t vddci_power;
- uint32_t max_gpu_power;
- uint32_t average_gpu_power;
-};
-
-#define PP_GROUP_MASK 0xF0000000
-#define PP_GROUP_SHIFT 28
-
-#define PP_BLOCK_MASK 0x0FFFFF00
-#define PP_BLOCK_SHIFT 8
-
-#define PP_BLOCK_GFX_CG 0x01
-#define PP_BLOCK_GFX_MG 0x02
-#define PP_BLOCK_GFX_3D 0x04
-#define PP_BLOCK_GFX_RLC 0x08
-#define PP_BLOCK_GFX_CP 0x10
-#define PP_BLOCK_SYS_BIF 0x01
-#define PP_BLOCK_SYS_MC 0x02
-#define PP_BLOCK_SYS_ROM 0x04
-#define PP_BLOCK_SYS_DRM 0x08
-#define PP_BLOCK_SYS_HDP 0x10
-#define PP_BLOCK_SYS_SDMA 0x20
-
-#define PP_STATE_MASK 0x0000000F
-#define PP_STATE_SHIFT 0
-#define PP_STATE_SUPPORT_MASK 0x000000F0
-#define PP_STATE_SUPPORT_SHIFT 0
-
-#define PP_STATE_CG 0x01
-#define PP_STATE_LS 0x02
-#define PP_STATE_DS 0x04
-#define PP_STATE_SD 0x08
-#define PP_STATE_SUPPORT_CG 0x10
-#define PP_STATE_SUPPORT_LS 0x20
-#define PP_STATE_SUPPORT_DS 0x40
-#define PP_STATE_SUPPORT_SD 0x80
-
-#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
- block << PP_BLOCK_SHIFT |\
- support << PP_STATE_SUPPORT_SHIFT |\
- state << PP_STATE_SHIFT)
+#include "kgd_pp_interface.h"
#endif /* _AMD_POWERPLAY_H_ */
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* RE: [PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h
[not found] ` <1506679340-31261-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-29 13:11 ` Deucher, Alexander
0 siblings, 0 replies; 3+ messages in thread
From: Deucher, Alexander @ 2017-09-29 13:11 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, Rex
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, September 29, 2017 6:02 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h
>
> move powerplay and amdgpu shared structures
> and definitions to kgd_pp_interface.h
>
> Change-Id: I4272b7974edbff3395ba8a6efebb0decd0cdfa12
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 -
> drivers/gpu/drm/amd/include/amd_shared.h | 172 -------------
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 289
> ++++++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 93 +------
> 5 files changed, 293 insertions(+), 267 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/include/kgd_pp_interface.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 2204ff6..1453aba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -47,6 +47,8 @@
> #include <drm/amdgpu_drm.h>
>
> #include <kgd_kfd_interface.h>
> +#include "dm_pp_interface.h"
> +#include "kgd_pp_interface.h"
>
> #include "amd_shared.h"
> #include "amdgpu_mode.h"
> @@ -59,7 +61,6 @@
> #include "amdgpu_sync.h"
> #include "amdgpu_ring.h"
> #include "amdgpu_vm.h"
> -#include "amd_powerplay.h"
> #include "amdgpu_dpm.h"
> #include "amdgpu_acp.h"
> #include "amdgpu_uvd.h"
> @@ -67,11 +68,11 @@
> #include "amdgpu_vcn.h"
> #include "amdgpu_mn.h"
> #include "amdgpu_dm.h"
> -
> #include "gpu_scheduler.h"
> #include "amdgpu_virt.h"
> #include "amdgpu_gart.h"
>
> +
> /*
> * Modules parameters.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index f3b23f9..f3afa66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -30,7 +30,6 @@
> #include <linux/hwmon.h>
> #include <linux/hwmon-sysfs.h>
>
> -#include "amd_powerplay.h"
>
> static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
>
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index 0bcf2bc..3aecf1d 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -27,7 +27,6 @@
>
> #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
>
> -struct seq_file;
>
> /*
> * Chip flags
> @@ -61,71 +60,12 @@ enum amd_clockgating_state {
> AMD_CG_STATE_UNGATE,
> };
>
> -enum amd_dpm_forced_level {
> - AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
> - AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
> - AMD_DPM_FORCED_LEVEL_LOW = 0x4,
> - AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
> - AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
> - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
> - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
> - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
> - AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
> -};
>
> enum amd_powergating_state {
> AMD_PG_STATE_GATE = 0,
> AMD_PG_STATE_UNGATE,
> };
>
> -struct amd_vce_state {
> - /* vce clocks */
> - u32 evclk;
> - u32 ecclk;
> - /* gpu clocks */
> - u32 sclk;
> - u32 mclk;
> - u8 clk_idx;
> - u8 pstate;
> -};
> -
> -
> -#define AMD_MAX_VCE_LEVELS 6
> -
> -enum amd_vce_level {
> - AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
> - AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
> - AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <=
> 720 */
> - AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080
> >= res > 720 */
> - AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue,
> res <= 720 */
> - AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue,
> 1080 >= res > 720 */
> -};
> -
> -enum amd_pp_profile_type {
> - AMD_PP_GFX_PROFILE,
> - AMD_PP_COMPUTE_PROFILE,
> -};
> -
> -struct amd_pp_profile {
> - enum amd_pp_profile_type type;
> - uint32_t min_sclk;
> - uint32_t min_mclk;
> - uint16_t activity_threshold;
> - uint8_t up_hyst;
> - uint8_t down_hyst;
> -};
> -
> -enum amd_fan_ctrl_mode {
> - AMD_FAN_CTRL_NONE = 0,
> - AMD_FAN_CTRL_MANUAL = 1,
> - AMD_FAN_CTRL_AUTO = 2,
> -};
> -
> -enum pp_clock_type {
> - PP_SCLK,
> - PP_MCLK,
> - PP_PCIE,
> -};
>
> /* CG flags */
> #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
> @@ -169,27 +109,6 @@ enum pp_clock_type {
> #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
> #define AMD_PG_SUPPORT_MMHUB (1 << 13)
>
> -enum amd_pm_state_type {
> - /* not used for dpm */
> - POWER_STATE_TYPE_DEFAULT,
> - POWER_STATE_TYPE_POWERSAVE,
> - /* user selectable states */
> - POWER_STATE_TYPE_BATTERY,
> - POWER_STATE_TYPE_BALANCED,
> - POWER_STATE_TYPE_PERFORMANCE,
> - /* internal states */
> - POWER_STATE_TYPE_INTERNAL_UVD,
> - POWER_STATE_TYPE_INTERNAL_UVD_SD,
> - POWER_STATE_TYPE_INTERNAL_UVD_HD,
> - POWER_STATE_TYPE_INTERNAL_UVD_HD2,
> - POWER_STATE_TYPE_INTERNAL_UVD_MVC,
> - POWER_STATE_TYPE_INTERNAL_BOOT,
> - POWER_STATE_TYPE_INTERNAL_THERMAL,
> - POWER_STATE_TYPE_INTERNAL_ACPI,
> - POWER_STATE_TYPE_INTERNAL_ULV,
> - POWER_STATE_TYPE_INTERNAL_3DPERF,
> -};
> -
> struct amd_ip_funcs {
> /* Name of IP block */
> char *name;
> @@ -233,95 +152,4 @@ struct amd_ip_funcs {
> };
>
>
> -enum amd_pp_task;
> -enum amd_pp_clock_type;
> -struct pp_states_info;
> -struct amd_pp_simple_clock_info;
> -struct amd_pp_display_configuration;
> -struct amd_pp_clock_info;
> -struct pp_display_clock_request;
> -struct pp_wm_sets_with_clock_ranges_soc15;
> -struct pp_clock_levels_with_voltage;
> -struct pp_clock_levels_with_latency;
> -struct amd_pp_clocks;
> -
> -struct amd_pm_funcs {
> -/* export for dpm on ci and si */
> - int (*pre_set_power_state)(void *handle);
> - int (*set_power_state)(void *handle);
> - void (*post_set_power_state)(void *handle);
> - void (*display_configuration_changed)(void *handle);
> - void (*print_power_state)(void *handle, void *ps);
> - bool (*vblank_too_short)(void *handle);
> - void (*enable_bapm)(void *handle, bool enable);
> - int (*check_state_equal)(void *handle,
> - void *cps,
> - void *rps,
> - bool *equal);
> -/* export for sysfs */
> - int (*get_temperature)(void *handle);
> - void (*set_fan_control_mode)(void *handle, u32 mode);
> - u32 (*get_fan_control_mode)(void *handle);
> - int (*set_fan_speed_percent)(void *handle, u32 speed);
> - int (*get_fan_speed_percent)(void *handle, u32 *speed);
> - int (*force_clock_level)(void *handle, enum pp_clock_type type,
> uint32_t mask);
> - int (*print_clock_levels)(void *handle, enum pp_clock_type type,
> char *buf);
> - int (*force_performance_level)(void *handle, enum
> amd_dpm_forced_level level);
> - int (*get_sclk_od)(void *handle);
> - int (*set_sclk_od)(void *handle, uint32_t value);
> - int (*get_mclk_od)(void *handle);
> - int (*set_mclk_od)(void *handle, uint32_t value);
> - int (*read_sensor)(void *handle, int idx, void *value, int *size);
> - enum amd_dpm_forced_level (*get_performance_level)(void
> *handle);
> - enum amd_pm_state_type (*get_current_power_state)(void
> *handle);
> - int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
> - int (*get_pp_num_states)(void *handle, struct pp_states_info
> *data);
> - int (*get_pp_table)(void *handle, char **table);
> - int (*set_pp_table)(void *handle, const char *buf, size_t size);
> - void (*debugfs_print_current_performance_level)(void *handle,
> struct seq_file *m);
> -
> - int (*reset_power_profile_state)(void *handle,
> - struct amd_pp_profile *request);
> - int (*get_power_profile_state)(void *handle,
> - struct amd_pp_profile *query);
> - int (*set_power_profile_state)(void *handle,
> - struct amd_pp_profile *request);
> - int (*switch_power_profile)(void *handle,
> - enum amd_pp_profile_type type);
> -/* export to amdgpu */
> - void (*powergate_uvd)(void *handle, bool gate);
> - void (*powergate_vce)(void *handle, bool gate);
> - struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32
> idx);
> - int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
> - void *input, void *output);
> - int (*load_firmware)(void *handle);
> - int (*wait_for_fw_loading_complete)(void *handle);
> - int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
> -/* export to DC */
> - u32 (*get_sclk)(void *handle, bool low);
> - u32 (*get_mclk)(void *handle, bool low);
> - int (*display_configuration_change)(void *handle,
> - const struct amd_pp_display_configuration *input);
> - int (*get_display_power_level)(void *handle,
> - struct amd_pp_simple_clock_info *output);
> - int (*get_current_clocks)(void *handle,
> - struct amd_pp_clock_info *clocks);
> - int (*get_clock_by_type)(void *handle,
> - enum amd_pp_clock_type type,
> - struct amd_pp_clocks *clocks);
> - int (*get_clock_by_type_with_latency)(void *handle,
> - enum amd_pp_clock_type type,
> - struct pp_clock_levels_with_latency *clocks);
> - int (*get_clock_by_type_with_voltage)(void *handle,
> - enum amd_pp_clock_type type,
> - struct pp_clock_levels_with_voltage *clocks);
> - int (*set_watermarks_for_clocks_ranges)(void *handle,
> - struct pp_wm_sets_with_clock_ranges_soc15
> *wm_with_clock_ranges);
> - int (*display_clock_voltage_request)(void *handle,
> - struct pp_display_clock_request *clock);
> - int (*get_display_mode_validation_clocks)(void *handle,
> - struct amd_pp_simple_clock_info *clocks);
> -};
> -
> -
> #endif /* __AMD_SHARED_H__ */
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> new file mode 100644
> index 0000000..f104668
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -0,0 +1,289 @@
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __KGD_PP_INTERFACE_H__
> +#define __KGD_PP_INTERFACE_H__
> +
> +extern const struct amd_ip_funcs pp_ip_funcs;
> +extern const struct amd_pm_funcs pp_dpm_funcs;
> +
> +struct amd_vce_state {
> + /* vce clocks */
> + u32 evclk;
> + u32 ecclk;
> + /* gpu clocks */
> + u32 sclk;
> + u32 mclk;
> + u8 clk_idx;
> + u8 pstate;
> +};
> +
> +
> +enum amd_dpm_forced_level {
> + AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
> + AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
> + AMD_DPM_FORCED_LEVEL_LOW = 0x4,
> + AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
> + AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
> + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
> + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
> + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
> + AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
> +};
> +
> +enum amd_pm_state_type {
> + /* not used for dpm */
> + POWER_STATE_TYPE_DEFAULT,
> + POWER_STATE_TYPE_POWERSAVE,
> + /* user selectable states */
> + POWER_STATE_TYPE_BATTERY,
> + POWER_STATE_TYPE_BALANCED,
> + POWER_STATE_TYPE_PERFORMANCE,
> + /* internal states */
> + POWER_STATE_TYPE_INTERNAL_UVD,
> + POWER_STATE_TYPE_INTERNAL_UVD_SD,
> + POWER_STATE_TYPE_INTERNAL_UVD_HD,
> + POWER_STATE_TYPE_INTERNAL_UVD_HD2,
> + POWER_STATE_TYPE_INTERNAL_UVD_MVC,
> + POWER_STATE_TYPE_INTERNAL_BOOT,
> + POWER_STATE_TYPE_INTERNAL_THERMAL,
> + POWER_STATE_TYPE_INTERNAL_ACPI,
> + POWER_STATE_TYPE_INTERNAL_ULV,
> + POWER_STATE_TYPE_INTERNAL_3DPERF,
> +};
> +
> +#define AMD_MAX_VCE_LEVELS 6
> +
> +enum amd_vce_level {
> + AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
> + AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
> + AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <=
> 720 */
> + AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080
> >= res > 720 */
> + AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue,
> res <= 720 */
> + AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue,
> 1080 >= res > 720 */
> +};
> +
> +enum amd_pp_profile_type {
> + AMD_PP_GFX_PROFILE,
> + AMD_PP_COMPUTE_PROFILE,
> +};
> +
> +struct amd_pp_profile {
> + enum amd_pp_profile_type type;
> + uint32_t min_sclk;
> + uint32_t min_mclk;
> + uint16_t activity_threshold;
> + uint8_t up_hyst;
> + uint8_t down_hyst;
> +};
> +
> +enum amd_fan_ctrl_mode {
> + AMD_FAN_CTRL_NONE = 0,
> + AMD_FAN_CTRL_MANUAL = 1,
> + AMD_FAN_CTRL_AUTO = 2,
> +};
> +
> +enum pp_clock_type {
> + PP_SCLK,
> + PP_MCLK,
> + PP_PCIE,
> +};
> +
> +enum amd_pp_sensors {
> + AMDGPU_PP_SENSOR_GFX_SCLK = 0,
> + AMDGPU_PP_SENSOR_VDDNB,
> + AMDGPU_PP_SENSOR_VDDGFX,
> + AMDGPU_PP_SENSOR_UVD_VCLK,
> + AMDGPU_PP_SENSOR_UVD_DCLK,
> + AMDGPU_PP_SENSOR_VCE_ECCLK,
> + AMDGPU_PP_SENSOR_GPU_LOAD,
> + AMDGPU_PP_SENSOR_GFX_MCLK,
> + AMDGPU_PP_SENSOR_GPU_TEMP,
> + AMDGPU_PP_SENSOR_VCE_POWER,
> + AMDGPU_PP_SENSOR_UVD_POWER,
> + AMDGPU_PP_SENSOR_GPU_POWER,
> +};
> +
> +enum amd_pp_task {
> + AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
> + AMD_PP_TASK_ENABLE_USER_STATE,
> + AMD_PP_TASK_READJUST_POWER_STATE,
> + AMD_PP_TASK_COMPLETE_INIT,
> + AMD_PP_TASK_MAX
> +};
> +
> +struct amd_pp_init {
> + struct cgs_device *device;
> + uint32_t chip_family;
> + uint32_t chip_id;
> + bool pm_en;
> + uint32_t feature_mask;
> +};
> +
> +
> +
> +enum {
> + PP_GROUP_UNKNOWN = 0,
> + PP_GROUP_GFX = 1,
> + PP_GROUP_SYS,
> + PP_GROUP_MAX
> +};
> +
> +struct pp_states_info {
> + uint32_t nums;
> + uint32_t states[16];
> +};
> +
> +struct pp_gpu_power {
> + uint32_t vddc_power;
> + uint32_t vddci_power;
> + uint32_t max_gpu_power;
> + uint32_t average_gpu_power;
> +};
> +
> +#define PP_GROUP_MASK 0xF0000000
> +#define PP_GROUP_SHIFT 28
> +
> +#define PP_BLOCK_MASK 0x0FFFFF00
> +#define PP_BLOCK_SHIFT 8
> +
> +#define PP_BLOCK_GFX_CG 0x01
> +#define PP_BLOCK_GFX_MG 0x02
> +#define PP_BLOCK_GFX_3D 0x04
> +#define PP_BLOCK_GFX_RLC 0x08
> +#define PP_BLOCK_GFX_CP 0x10
> +#define PP_BLOCK_SYS_BIF 0x01
> +#define PP_BLOCK_SYS_MC 0x02
> +#define PP_BLOCK_SYS_ROM 0x04
> +#define PP_BLOCK_SYS_DRM 0x08
> +#define PP_BLOCK_SYS_HDP 0x10
> +#define PP_BLOCK_SYS_SDMA 0x20
> +
> +#define PP_STATE_MASK 0x0000000F
> +#define PP_STATE_SHIFT 0
> +#define PP_STATE_SUPPORT_MASK 0x000000F0
> +#define PP_STATE_SUPPORT_SHIFT 0
> +
> +#define PP_STATE_CG 0x01
> +#define PP_STATE_LS 0x02
> +#define PP_STATE_DS 0x04
> +#define PP_STATE_SD 0x08
> +#define PP_STATE_SUPPORT_CG 0x10
> +#define PP_STATE_SUPPORT_LS 0x20
> +#define PP_STATE_SUPPORT_DS 0x40
> +#define PP_STATE_SUPPORT_SD 0x80
> +
> +#define PP_CG_MSG_ID(group, block, support, state) \
> + ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT
> | \
> + (support) << PP_STATE_SUPPORT_SHIFT | (state) <<
> PP_STATE_SHIFT)
> +
> +struct seq_file;
> +enum amd_pp_clock_type;
> +struct amd_pp_simple_clock_info;
> +struct amd_pp_display_configuration;
> +struct amd_pp_clock_info;
> +struct pp_display_clock_request;
> +struct pp_wm_sets_with_clock_ranges_soc15;
> +struct pp_clock_levels_with_voltage;
> +struct pp_clock_levels_with_latency;
> +struct amd_pp_clocks;
> +
> +struct amd_pm_funcs {
> +/* export for dpm on ci and si */
> + int (*pre_set_power_state)(void *handle);
> + int (*set_power_state)(void *handle);
> + void (*post_set_power_state)(void *handle);
> + void (*display_configuration_changed)(void *handle);
> + void (*print_power_state)(void *handle, void *ps);
> + bool (*vblank_too_short)(void *handle);
> + void (*enable_bapm)(void *handle, bool enable);
> + int (*check_state_equal)(void *handle,
> + void *cps,
> + void *rps,
> + bool *equal);
> +/* export for sysfs */
> + int (*get_temperature)(void *handle);
> + void (*set_fan_control_mode)(void *handle, u32 mode);
> + u32 (*get_fan_control_mode)(void *handle);
> + int (*set_fan_speed_percent)(void *handle, u32 speed);
> + int (*get_fan_speed_percent)(void *handle, u32 *speed);
> + int (*force_clock_level)(void *handle, enum pp_clock_type type,
> uint32_t mask);
> + int (*print_clock_levels)(void *handle, enum pp_clock_type type,
> char *buf);
> + int (*force_performance_level)(void *handle, enum
> amd_dpm_forced_level level);
> + int (*get_sclk_od)(void *handle);
> + int (*set_sclk_od)(void *handle, uint32_t value);
> + int (*get_mclk_od)(void *handle);
> + int (*set_mclk_od)(void *handle, uint32_t value);
> + int (*read_sensor)(void *handle, int idx, void *value, int *size);
> + enum amd_dpm_forced_level (*get_performance_level)(void
> *handle);
> + enum amd_pm_state_type (*get_current_power_state)(void
> *handle);
> + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
> + int (*get_pp_num_states)(void *handle, struct pp_states_info
> *data);
> + int (*get_pp_table)(void *handle, char **table);
> + int (*set_pp_table)(void *handle, const char *buf, size_t size);
> + void (*debugfs_print_current_performance_level)(void *handle,
> struct seq_file *m);
> +
> + int (*reset_power_profile_state)(void *handle,
> + struct amd_pp_profile *request);
> + int (*get_power_profile_state)(void *handle,
> + struct amd_pp_profile *query);
> + int (*set_power_profile_state)(void *handle,
> + struct amd_pp_profile *request);
> + int (*switch_power_profile)(void *handle,
> + enum amd_pp_profile_type type);
> +/* export to amdgpu */
> + void (*powergate_uvd)(void *handle, bool gate);
> + void (*powergate_vce)(void *handle, bool gate);
> + struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32
> idx);
> + int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
> + void *input, void *output);
> + int (*load_firmware)(void *handle);
> + int (*wait_for_fw_loading_complete)(void *handle);
> + int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
> +/* export to DC */
> + u32 (*get_sclk)(void *handle, bool low);
> + u32 (*get_mclk)(void *handle, bool low);
> + int (*display_configuration_change)(void *handle,
> + const struct amd_pp_display_configuration *input);
> + int (*get_display_power_level)(void *handle,
> + struct amd_pp_simple_clock_info *output);
> + int (*get_current_clocks)(void *handle,
> + struct amd_pp_clock_info *clocks);
> + int (*get_clock_by_type)(void *handle,
> + enum amd_pp_clock_type type,
> + struct amd_pp_clocks *clocks);
> + int (*get_clock_by_type_with_latency)(void *handle,
> + enum amd_pp_clock_type type,
> + struct pp_clock_levels_with_latency *clocks);
> + int (*get_clock_by_type_with_voltage)(void *handle,
> + enum amd_pp_clock_type type,
> + struct pp_clock_levels_with_voltage *clocks);
> + int (*set_watermarks_for_clocks_ranges)(void *handle,
> + struct pp_wm_sets_with_clock_ranges_soc15
> *wm_with_clock_ranges);
> + int (*display_clock_voltage_request)(void *handle,
> + struct pp_display_clock_request *clock);
> + int (*get_display_mode_validation_clocks)(void *handle,
> + struct amd_pp_simple_clock_info *clocks);
> +};
> +
> +#endif
> \ No newline at end of file
Missing newline.
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> index 47478e0..152e70d 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> @@ -29,98 +29,7 @@
> #include "amd_shared.h"
> #include "cgs_common.h"
> #include "dm_pp_interface.h"
> -
> -extern const struct amd_ip_funcs pp_ip_funcs;
> -extern const struct amd_pm_funcs pp_dpm_funcs;
> -
> -enum amd_pp_sensors {
> - AMDGPU_PP_SENSOR_GFX_SCLK = 0,
> - AMDGPU_PP_SENSOR_VDDNB,
> - AMDGPU_PP_SENSOR_VDDGFX,
> - AMDGPU_PP_SENSOR_UVD_VCLK,
> - AMDGPU_PP_SENSOR_UVD_DCLK,
> - AMDGPU_PP_SENSOR_VCE_ECCLK,
> - AMDGPU_PP_SENSOR_GPU_LOAD,
> - AMDGPU_PP_SENSOR_GFX_MCLK,
> - AMDGPU_PP_SENSOR_GPU_TEMP,
> - AMDGPU_PP_SENSOR_VCE_POWER,
> - AMDGPU_PP_SENSOR_UVD_POWER,
> - AMDGPU_PP_SENSOR_GPU_POWER,
> -};
> -
> -enum amd_pp_task {
> - AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
> - AMD_PP_TASK_ENABLE_USER_STATE,
> - AMD_PP_TASK_READJUST_POWER_STATE,
> - AMD_PP_TASK_COMPLETE_INIT,
> - AMD_PP_TASK_MAX
> -};
> -
> -struct amd_pp_init {
> - struct cgs_device *device;
> - uint32_t chip_family;
> - uint32_t chip_id;
> - bool pm_en;
> - uint32_t feature_mask;
> -};
> -
> -
> -
> -enum {
> - PP_GROUP_UNKNOWN = 0,
> - PP_GROUP_GFX = 1,
> - PP_GROUP_SYS,
> - PP_GROUP_MAX
> -};
> -
> -struct pp_states_info {
> - uint32_t nums;
> - uint32_t states[16];
> -};
> -
> -struct pp_gpu_power {
> - uint32_t vddc_power;
> - uint32_t vddci_power;
> - uint32_t max_gpu_power;
> - uint32_t average_gpu_power;
> -};
> -
> -#define PP_GROUP_MASK 0xF0000000
> -#define PP_GROUP_SHIFT 28
> -
> -#define PP_BLOCK_MASK 0x0FFFFF00
> -#define PP_BLOCK_SHIFT 8
> -
> -#define PP_BLOCK_GFX_CG 0x01
> -#define PP_BLOCK_GFX_MG 0x02
> -#define PP_BLOCK_GFX_3D 0x04
> -#define PP_BLOCK_GFX_RLC 0x08
> -#define PP_BLOCK_GFX_CP 0x10
> -#define PP_BLOCK_SYS_BIF 0x01
> -#define PP_BLOCK_SYS_MC 0x02
> -#define PP_BLOCK_SYS_ROM 0x04
> -#define PP_BLOCK_SYS_DRM 0x08
> -#define PP_BLOCK_SYS_HDP 0x10
> -#define PP_BLOCK_SYS_SDMA 0x20
> -
> -#define PP_STATE_MASK 0x0000000F
> -#define PP_STATE_SHIFT 0
> -#define PP_STATE_SUPPORT_MASK 0x000000F0
> -#define PP_STATE_SUPPORT_SHIFT 0
> -
> -#define PP_STATE_CG 0x01
> -#define PP_STATE_LS 0x02
> -#define PP_STATE_DS 0x04
> -#define PP_STATE_SD 0x08
> -#define PP_STATE_SUPPORT_CG 0x10
> -#define PP_STATE_SUPPORT_LS 0x20
> -#define PP_STATE_SUPPORT_DS 0x40
> -#define PP_STATE_SUPPORT_SD 0x80
> -
> -#define PP_CG_MSG_ID(group, block, support, state) (group <<
> PP_GROUP_SHIFT |\
> - block <<
> PP_BLOCK_SHIFT |\
> - support <<
> PP_STATE_SUPPORT_SHIFT |\
> - state <<
> PP_STATE_SHIFT)
> +#include "kgd_pp_interface.h"
Is there any point in keeping this header around at this point? Looks like you've removed everything.
Alex
>
>
> #endif /* _AMD_POWERPLAY_H_ */
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-09-29 13:11 UTC | newest]
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-- links below jump to the message on this page --
2017-09-29 10:02 [PATCH 1/2] drm/amdgpu: move struct amd_powerplay to amdgpu.h Rex Zhu
[not found] ` <1506679340-31261-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-09-29 10:02 ` [PATCH 2/2] drm/amdgpu: add header kgd_pp_interface.h Rex Zhu
[not found] ` <1506679340-31261-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-09-29 13:11 ` Deucher, Alexander
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