[U-Boot] [PATCH v2 00/14] Enable Stratix10 SoC support

[U-Boot] [PATCH v2 00/14] Enable Stratix10 SoC support

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

This patch series are enabling support for Stratix 10 SoC

Changes for v2
- Removed defines for base addresses that can be extracted from DTS
- Added CPU node plus MDIO node for Ethernet at DTS
- Added defines for constant value for readability
- Consolidated common code for Clock Manager and misc code

Chin Liang See (14):
  arm: socfpga: stratix10: Add base address map for Statix10 SoC
  arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC
  arm: socfpga: stratix10: Add misc support for Stratix10 SoC
  arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC
  arm: socfpga: stratix10: Add MMU support for Stratix10 SoC
  arm: dts: Add dts for Stratix10 SoC
  arm: socfpga: Restructure the SPL file
  arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC
  arm: socfpga: stratix10: Add timer support for Stratix10 SoC
  ddr: altera: stratix10: Add DDR support for Stratix10 SoC
  board: altera: stratix10: Add socdk board support for Stratix10 SoC
  arm: socfpga: stratix10: Enable Stratix10 SoC build

 arch/arm/Kconfig                                   |   8 +-
 arch/arm/dts/Makefile                              |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts           | 180 ++++++++++
 arch/arm/mach-socfpga/Kconfig                      |  13 +
 arch/arm/mach-socfpga/Makefile                     |  19 +-
 arch/arm/mach-socfpga/clock_manager.c              |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c          | 355 +++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  56 +++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 210 +++++++++++
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |  84 +++++
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h   | 108 ++++++
 arch/arm/mach-socfpga/include/mach/misc.h          |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h           |   8 +-
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +++++++
 arch/arm/mach-socfpga/include/mach/sdram_s10.h     | 333 ++++++++++++++++++
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +++++++++
 arch/arm/mach-socfpga/mailbox_s10.c                | 238 +++++++++++++
 arch/arm/mach-socfpga/misc.c                       |  76 ++++
 arch/arm/mach-socfpga/misc_gen5.c                  |  75 +---
 arch/arm/mach-socfpga/misc_s10.c                   | 115 +++++++
 arch/arm/mach-socfpga/mmu-arm64_s10.c              |  71 ++++
 arch/arm/mach-socfpga/reset_manager.c              |  41 +++
 arch/arm/mach-socfpga/reset_manager_arria10.c      |  67 +---
 arch/arm/mach-socfpga/reset_manager_gen5.c         |  33 --
 arch/arm/mach-socfpga/reset_manager_s10.c          | 118 +++++++
 arch/arm/mach-socfpga/spl_a10.c                    | 105 ++++++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c}        |  46 ---
 arch/arm/mach-socfpga/spl_s10.c                    | 138 ++++++++
 arch/arm/mach-socfpga/system_manager_s10.c         |  91 +++++
 arch/arm/mach-socfpga/timer.c                      |  17 +-
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c     |  55 +++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c        |  44 +++
 board/altera/stratix10-socdk/MAINTAINERS           |   7 +
 board/altera/stratix10-socdk/Makefile              |   7 +
 board/altera/stratix10-socdk/socfpga.c             |   7 +
 configs/socfpga_stratix10_defconfig                |  39 +++
 drivers/ddr/altera/Makefile                        |   1 +
 drivers/ddr/altera/sdram_s10.c                     | 382 +++++++++++++++++++++
 include/configs/socfpga_stratix10_socdk.h          | 216 ++++++++++++
 include/dt-bindings/reset/altr,rst-mgr-s10.h       |  97 ++++++
 44 files changed, 3577 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 drivers/ddr/altera/sdram_s10.c
 create mode 100644 include/configs/socfpga_stratix10_socdk.h
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

--
2.2.2

[U-Boot] [PATCH v2 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 0000000..2fdc917
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

[U-Boot] [PATCH v2 02/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
--
Changes in v2
- Declared defines for constant value used
- Fixed spacing and comments
---
 arch/arm/mach-socfpga/Makefile                     |   4 +
 arch/arm/mach-socfpga/clock_manager.c              |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c          | 355 +++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 210 ++++++++++++
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c        |  44 +++
 7 files changed, 646 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..e5f9dd7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -30,6 +30,10 @@ obj-y	+= pinmux_arria10.o
 obj-y	+= reset_manager_arria10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= clock_manager_s10.o
+obj-y	+= wrap_pll_config_s10.o
+endif
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae03..f9450a4 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
 	do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 		inter_val = readl(&clock_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
 		inter_val = readl(&clock_manager_base->stat) & mask;
 #endif
 		/* Wait for stable lock */
@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
 	gd->bd->bi_ddr_freq = 0;
 #endif
 
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
new file mode 100644
index 0000000..cfb6708
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/handoff_s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(uint32_t val)
+{
+	writel(val, &clock_manager_base->main_pll.bypass);
+	cm_wait_for_fsm();
+}
+
+static void cm_write_bypass_perpll(uint32_t val)
+{
+	writel(val, &clock_manager_base->per_pll.bypass);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(uint32_t val)
+{
+	writel(val, &clock_manager_base->ctrl);
+	cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+	uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+	if (cfg == 0)
+		return;
+
+	/* Put all plls in bypass */
+	cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+	cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+	/* setup main PLL dividers where calculate the vcocalib value */
+	mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+		CLKMGR_FDBCK_MDIV_MASK;
+	refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		     CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+	mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+	hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+		CLKMGR_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+		   CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+	writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+		~CLKMGR_PLLGLOB_RST_MASK),
+		&clock_manager_base->main_pll.pllglob);
+	writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
+	writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
+	writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
+	writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
+	writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+
+	/* setup peripheral PLL dividers */
+	/* calculate the vcocalib value */
+	mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+		CLKMGR_FDBCK_MDIV_MASK;
+	refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		     CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+	mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+	hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+		CLKMGR_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+		   CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+	writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+		~CLKMGR_PLLGLOB_RST_MASK),
+		&clock_manager_base->per_pll.pllglob);
+	writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
+	writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
+	writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
+	writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
+	writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
+	writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+
+	/* Take both PLL out of reset and power up */
+	setbits_le32(&clock_manager_base->main_pll.pllglob,
+		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	setbits_le32(&clock_manager_base->per_pll.pllglob,
+		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+#define LOCKED_MASK \
+	(CLKMGR_STAT_MAINPLL_LOCKED | \
+	CLKMGR_STAT_PERPLL_LOCKED)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/*
+	 * Dividers for C2 to C9 only init after PLLs are lock. As dividers
+	 * only take effect upon value change, we shall set a maximum value as
+	 * default value.
+	 */
+	writel(0xff, &clock_manager_base->main_pll.mpuclk);
+	writel(0xff, &clock_manager_base->main_pll.nocclk);
+	writel(0xff, &clock_manager_base->main_pll.cntr2clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr3clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr4clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr5clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr6clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr7clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr8clk);
+	writel(0xff, &clock_manager_base->main_pll.cntr9clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr2clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr3clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr4clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr5clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr6clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr7clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr8clk);
+	writel(0xff, &clock_manager_base->per_pll.cntr9clk);
+
+	writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
+	writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
+	writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
+	writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
+	writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
+	writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
+	writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
+	writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
+	writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
+	writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
+	writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
+	writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
+	writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
+	writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
+	writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
+	writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
+	writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
+	writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+
+	/* Take all PLLs out of bypass */
+	cm_write_bypass_mainpll(0);
+	cm_write_bypass_perpll(0);
+
+	/* clear safe mode / out of boot mode */
+	cm_write_ctrl(readl(&clock_manager_base->ctrl)
+			& ~(CLKMGR_CTRL_SAFEMODE));
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll.en);
+	writel(~0, &clock_manager_base->per_pll.en);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
+	       &clock_manager_base->intrclr);
+}
+
+static unsigned long cm_get_main_vco_clk_hz(void)
+{
+	 unsigned long fref, refdiv, mdiv, reg, vco;
+
+	reg = readl(&clock_manager_base->main_pll.pllglob);
+
+	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz(0);
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+	reg = readl(&clock_manager_base->main_pll.fdbck);
+	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+	vco = fref / refdiv;
+	vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+	return vco;
+}
+
+static unsigned long cm_get_per_vco_clk_hz(void)
+{
+	unsigned long fref, refdiv, mdiv, reg, vco;
+
+	reg = readl(&clock_manager_base->per_pll.pllglob);
+
+	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz(0);
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+	reg = readl(&clock_manager_base->per_pll.fdbck);
+	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+	vco = fref / refdiv;
+	vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+	return vco;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_main_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+			  CLKMGR_PLLC0_DIV_MASK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_per_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz(0);
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
+		CLKMGR_CLKCNT_MSK);
+	return clock;
+}
+
+unsigned int cm_get_l3_main_clk_hz(void)
+{
+	uint32_t clock = readl(&clock_manager_base->main_pll.nocclk);
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_main_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+			  CLKMGR_PLLC0_DIV_MASK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_per_vco_clk_hz();
+		clock /= (readl(&clock_manager_base->per_pll.pllc1) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz(0);
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
+		CLKMGR_CLKCNT_MSK);
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	uint32_t clock = readl(&clock_manager_base->per_pll.cntr6clk);
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_l3_main_clk_hz();
+		clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
+			CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_l3_main_clk_hz();
+		clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
+			CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz(0);
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+	return clock / 4;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	uint32_t clock = cm_get_l3_main_clk_hz();
+
+	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
+		  CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+	return clock;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
+	printf("L3 main     %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
+	printf("Main VCO    %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
+	printf("Per VCO     %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
+	printf("EOSC1       %d kHz\n", cm_get_osc_clk_hz(0) / 1000);
+	printf("HPS MMC     %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("UART        %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 4c6b1f8..ddf814f 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);
 #include <asm/arch/clock_manager_gen5.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/clock_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/clock_manager_s10.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
new file mode 100644
index 0000000..831cf2c
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_CLOCK_MANAGER_S10_
+#define	_CLOCK_MANAGER_S10_
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ		25000000
+#define CLKMGR_INTOSC_HZ	460000000
+#define CLKMGR_FPGA_CLK_HZ	50000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+struct cm_config {
+	/* main group */
+	uint32_t main_pll_mpuclk;
+	uint32_t main_pll_nocclk;
+	uint32_t main_pll_cntr2clk;
+	uint32_t main_pll_cntr3clk;
+	uint32_t main_pll_cntr4clk;
+	uint32_t main_pll_cntr5clk;
+	uint32_t main_pll_cntr6clk;
+	uint32_t main_pll_cntr7clk;
+	uint32_t main_pll_cntr8clk;
+	uint32_t main_pll_cntr9clk;
+	uint32_t main_pll_nocdiv;
+	uint32_t main_pll_pllglob;
+	uint32_t main_pll_fdbck;
+	uint32_t main_pll_pllc0;
+	uint32_t main_pll_pllc1;
+	uint32_t spare;
+
+	/* peripheral group */
+	uint32_t per_pll_cntr2clk;
+	uint32_t per_pll_cntr3clk;
+	uint32_t per_pll_cntr4clk;
+	uint32_t per_pll_cntr5clk;
+	uint32_t per_pll_cntr6clk;
+	uint32_t per_pll_cntr7clk;
+	uint32_t per_pll_cntr8clk;
+	uint32_t per_pll_cntr9clk;
+	uint32_t per_pll_emacctl;
+	uint32_t per_pll_gpiodiv;
+	uint32_t per_pll_pllglob;
+	uint32_t per_pll_fdbck;
+	uint32_t per_pll_pllc0;
+	uint32_t per_pll_pllc1;
+
+	/* incoming clock */
+	uint32_t hps_osc_clk_hz;
+	uint32_t fpga_clk_hz;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+struct socfpga_clock_manager_main_pll {
+	u32	en;
+	u32	ens;
+	u32	enr;
+	u32	bypass;
+	u32	bypasss;
+	u32	bypassr;
+	u32	mpuclk;
+	u32	nocclk;
+	u32	cntr2clk;
+	u32	cntr3clk;
+	u32	cntr4clk;
+	u32	cntr5clk;
+	u32	cntr6clk;
+	u32	cntr7clk;
+	u32	cntr8clk;
+	u32	cntr9clk;
+	u32	nocdiv;
+	u32	pllglob;
+	u32	fdbck;
+	u32	mem;
+	u32	memstat;
+	u32	pllc0;
+	u32	pllc1;
+	u32	vcocalib;
+	u32	_pad_0x90_0xA0[5];
+};
+
+struct socfpga_clock_manager_per_pll {
+	u32	en;
+	u32	ens;
+	u32	enr;
+	u32	bypass;
+	u32	bypasss;
+	u32	bypassr;
+	u32	cntr2clk;
+	u32	cntr3clk;
+	u32	cntr4clk;
+	u32	cntr5clk;
+	u32	cntr6clk;
+	u32	cntr7clk;
+	u32	cntr8clk;
+	u32	cntr9clk;
+	u32	emacctl;
+	u32	gpiodiv;
+	u32	pllglob;
+	u32	fdbck;
+	u32	mem;
+	u32	memstat;
+	u32	pllc0;
+	u32	pllc1;
+	u32	vcocalib;
+	u32	_pad_0x100_0x124[10];
+};
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	stat;
+	u32	testioctrl;
+	u32	intrgen;
+	u32	intrmsk;
+	u32	intrclr;
+	u32	intrsts;
+	u32	intrstk;
+	u32	intrraw;
+	u32	_pad_0x24_0x2c[3];
+	struct socfpga_clock_manager_main_pll main_pll;
+	struct socfpga_clock_manager_per_pll per_pll;
+};
+
+#define CLKMGR_CTRL_SAFEMODE				(1 << 0)
+#define CLKMGR_BYPASS_MAINPLL_ALL			0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL			0x0000007f
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000008
+#define CLKMGR_STAT_BUSY				(1 << 0)
+#define CLKMGR_STAT_MAINPLL_LOCKED			(1 << 8)
+#define CLKMGR_STAT_PERPLL_LOCKED			(1 << 9)
+
+#define CLKMGR_PLLGLOB_PD_MASK				0x00000001
+#define CLKMGR_PLLGLOB_RST_MASK				0x00000002
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
+#define CLKMGR_VCO_PSRC_EOSC1				0
+#define CLKMGR_VCO_PSRC_INTOSC				1
+#define CLKMGR_VCO_PSRC_F2S				2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
+
+#define CLKMGR_CLKSRC_MASK				0x7
+#define CLKMGR_CLKSRC_OFFSET				16
+#define CLKMGR_CLKSRC_MAIN				0
+#define CLKMGR_CLKSRC_PER				1
+#define CLKMGR_CLKSRC_OSC1				2
+#define CLKMGR_CLKSRC_INTOSC				3
+#define CLKMGR_CLKSRC_FPGA				4
+#define CLKMGR_CLKCNT_MSK				0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK				0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET			24
+
+#define CLKMGR_PLLC0_DIV_MASK				0xff
+#define CLKMGR_PLLC1_DIV_MASK				0xff
+#define CLKMGR_PLLC0_EN_OFFSET				27
+#define CLKMGR_PLLC1_EN_OFFSET				24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET			0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET			8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET			16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET			24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET			26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET			28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK			0X3
+#define CLKMGR_NOCDIV_DIV1				0
+#define CLKMGR_NOCDIV_DIV2				1
+#define CLKMGR_NOCDIV_DIV4				2
+#define CLKMGR_NOCDIV_DIV8				3
+#define CLKMGR_CSPDBGCLK_DIV1				0
+#define CLKMGR_CSPDBGCLK_DIV4				1
+
+#define CLKMGR_MSCNT_CONST				200
+#define CLKMGR_MDIV_CONST				6
+#define CLKMGR_HSCNT_CONST				9
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK			0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET			9
+#define CLKMGR_VCOCALIB_HSCNT_MASK			0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET			26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET			27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET			28
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
+
+#endif /* _CLOCK_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
new file mode 100644
index 0000000..d4b89ac
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _HANDOFF_S10_H_
+#define _HANDOFF_S10_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define CONFIG_HANDOFF_BASE		0xFFE3F000
+#define CONFIG_HANDOFF_MUX		(CONFIG_HANDOFF_BASE + 0x10)
+#define CONFIG_HANDOFF_IOCTL		(CONFIG_HANDOFF_BASE + 0x1A0)
+#define CONFIG_HANDOFF_FPGA		(CONFIG_HANDOFF_BASE + 0x330)
+#define CONFIG_HANODFF_DELAY		(CONFIG_HANDOFF_BASE + 0x3F0)
+#define CONFIG_HANDOFF_CLOCK		(CONFIG_HANDOFF_BASE + 0x580)
+#define CONFIG_HANDOFF_MISC		(CONFIG_HANDOFF_BASE + 0x610)
+#define CONFIG_HANDOFF_MAGIC_MUX	0x504D5558
+#define CONFIG_HANDOFF_MAGIC_IOCTL	0x494F4354
+#define CONFIG_HANDOFF_MAGIC_FPGA	0x46504741
+#define CONFIG_HANDOFF_MAGIC_DELAY	0x444C4159
+#define CONFIG_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#define CONFIG_HANDOFF_MAGIC_MISC	0x4D495343
+#define CONFIG_HANDOFF_OFFSET_LENGTH	0x4
+#define CONFIG_HANDOFF_OFFSET_DATA	0x10
+
+#endif /* _HANDOFF_S10_H_ */
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
new file mode 100644
index 0000000..3f19534
--- /dev/null
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+
+const struct cm_config * const cm_get_default_config(void)
+{
+	struct cm_config *cm_handoff_cfg = (struct cm_config *)
+		(CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA);
+	u32 *conversion = (u32 *)cm_handoff_cfg;
+	u32 i;
+
+	if (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) {
+		writel(swab32(readl(CONFIG_HANDOFF_CLOCK)),
+			CONFIG_HANDOFF_CLOCK);
+		for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
+			conversion[i] = swab32(conversion[i]);
+		return cm_handoff_cfg;
+	} else if (readl(CONFIG_HANDOFF_CLOCK) == CONFIG_HANDOFF_MAGIC_CLOCK) {
+		return cm_handoff_cfg;
+	} else
+		return 0;
+}
+
+const unsigned int cm_get_osc_clk_hz(const int osc)
+{
+	return CLKMGR_EOSC1_HZ;
+}
+
+const unsigned int cm_get_intosc_clk_hz(void)
+{
+	return CLKMGR_INTOSC_HZ;
+}
+
+const unsigned int cm_get_fpga_clk_hz(void)
+{
+	return CLKMGR_FPGA_CLK_HZ;
+}
-- 
2.2.2

[U-Boot] [PATCH v2 03/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h           |   8 +-
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 ++++++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              |  41 +++++++
 arch/arm/mach-socfpga/reset_manager_arria10.c      |  67 +++---------
 arch/arm/mach-socfpga/reset_manager_gen5.c         |  33 ------
 arch/arm/mach-socfpga/reset_manager_s10.c          | 118 +++++++++++++++++++++
 include/dt-bindings/reset/altr,rst-mgr-s10.h       |  97 +++++++++++++++++
 9 files changed, 395 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= reset_manager_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 #include <asm/arch/reset_manager_gen5.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/reset_manager_s10.h>
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index b6d7f4f..e521839 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -28,10 +28,10 @@ struct socfpga_reset_manager {
 	u32	hdskreq;
 	u32	hdskack;
 	u32	counts;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
 	u32	sysmodrst;
 	u32	coldmodrst;
 	u32	nrstmodrst;
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 0000000..07ada59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_RESET_MANAGER_S10_
+#define	_RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	mpu_rst_stat;
+	u32	misc_stat;
+	u32	padding1;
+	u32	hdsk_en;
+	u32	hdsk_req;
+	u32	hdsk_ack;
+	u32	hdsk_stall;
+	u32     mpu_mod_reset;
+	u32     per_mod_reset;  /* stated as per0_mod_reset in S10 datasheet */
+	u32     per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+	u32     brg_mod_reset;
+	u32	padding2;
+	u32     cold_mod_reset;
+	u32	padding3;
+	u32     dbg_mod_reset;
+	u32     tap_mod_reset;
+	u32	padding4;
+	u32	padding5;
+	u32     brg_warm_mask;
+	u32	padding6[3];
+	u32     tst_stat;
+	u32	padding7;
+	u32     hdsk_timeout;
+	u32     mpul2flushtimeout;
+	u32     dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0		0
+#define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET	8
+#define RSTMGR_BANK_MASK	0x7
+#define RSTMGR_RESET_OFFSET	0
+#define RSTMGR_RESET_MASK	0x1f
+#define RSTMGR_DEFINE(_bank, _offset)		\
+	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)			\
+	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)			\
+	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0		RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP	RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP	RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP	RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCP		RSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCP		RSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCP		RSTMGR_DEFINE(1, 13)
+#define RSTMGR_SDMMC_OCP	RSTMGR_DEFINE(1, 15)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4WD2		RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4WD3		RSTMGR_DEFINE(2, 3)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(2, 4)
+#define RSTMGR_I2C0		RSTMGR_DEFINE(2, 8)
+#define RSTMGR_I2C1		RSTMGR_DEFINE(2, 9)
+#define RSTMGR_I2C2		RSTMGR_DEFINE(2, 10)
+#define RSTMGR_I2C3		RSTMGR_DEFINE(2, 11)
+#define RSTMGR_I2C4		RSTMGR_DEFINE(2, 12)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_GPIO0		RSTMGR_DEFINE(2, 24)
+#define RSTMGR_GPIO1		RSTMGR_DEFINE(2, 25)
+#define RSTMGR_SDR		RSTMGR_DEFINE(3, 6)
+
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name)	RSTMGR_##_name
+
+#endif /* _RESET_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 29438ed..6a62e93 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -20,8 +20,13 @@ static const struct socfpga_reset_manager *reset_manager_base =
 void reset_cpu(ulong addr)
 {
 	/* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	writel((1 << RSTMGR_MPUMODRST_CORE0),
+	       &reset_manager_base->mpu_mod_reset);
+#else
 	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
 	       &reset_manager_base->ctrl);
+#endif
 	/*
 	 * infinite loop here as watchdog will trigger and reset
 	 * the processor
@@ -29,3 +34,39 @@ void reset_cpu(ulong addr)
 	while (1)
 		;
 }
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+	const u32 *reg = 0;
+	u32 rstmgr_bank = RSTMGR_BANK(reset);
+
+	switch (rstmgr_bank) {
+	case 0:
+		reg = &reset_manager_base->mpu_mod_reset;
+		break;
+	case 1:
+		reg = &reset_manager_base->per_mod_reset;
+		break;
+	case 2:
+		reg = &reset_manager_base->per2_mod_reset;
+		break;
+	case 3:
+		reg = &reset_manager_base->brg_mod_reset;
+		break;
+	case 4:
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+		reg = &reset_manager_base->misc_mod_reset;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+		reg = &reset_manager_base->sysmodrst;
+#endif
+		break;
+	default:
+		return;
+	}
+
+	if (set)
+		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 66f1ec2..bf0345c 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -129,14 +129,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
 void socfpga_watchdog_disable(void)
 {
 	/* assert reset for watchdog */
-	setbits_le32(&reset_manager_base->per1modrst,
+	setbits_le32(&reset_manager_base->per2_mod_reset,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
 /* Release NOC ddr scheduler from reset */
 void socfpga_reset_deassert_noc_ddr_scheduler(void)
 {
-	clrbits_le32(&reset_manager_base->brgmodrst,
+	clrbits_le32(&reset_manager_base->brg_mod_reset,
 		     ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
 }
 
@@ -145,7 +145,7 @@ int socfpga_is_wdt_in_reset(void)
 {
 	u32 val;
 
-	val = readl(&reset_manager_base->per1modrst);
+	val = readl(&reset_manager_base->per2_mod_reset);
 	val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
 
 	/* return 0x1 if watchdog in reset */
@@ -181,12 +181,12 @@ void socfpga_emac_manage_reset(ulong emacbase, u32 state)
 
 	if (state) {
 		/* Enable ECC OCP first */
-		setbits_le32(&reset_manager_base->per0modrst, eccmask);
-		setbits_le32(&reset_manager_base->per0modrst, emacmask);
+		setbits_le32(&reset_manager_base->per_mod_reset, eccmask);
+		setbits_le32(&reset_manager_base->per_mod_reset, emacmask);
 	} else {
 		/* Disable ECC OCP first */
-		clrbits_le32(&reset_manager_base->per0modrst, emacmask);
-		clrbits_le32(&reset_manager_base->per0modrst, eccmask);
+		clrbits_le32(&reset_manager_base->per_mod_reset, emacmask);
+		clrbits_le32(&reset_manager_base->per_mod_reset, eccmask);
 	}
 }
 
@@ -219,7 +219,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
 	setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
 
 	/* Release bridges from reset state per handoff value */
-	clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+	clrbits_le32(&reset_manager_base->brg_mod_reset, mask_rstmgr);
 
 	/* Poll until all idleack to 0, timeout at 1000ms */
 	return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
@@ -241,54 +241,19 @@ void socfpga_reset_assert_fpga_connected_peripherals(void)
 		fpga_pinux_addr += sizeof(u32);
 	}
 
-	setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
-	setbits_le32(&reset_manager_base->per1modrst, mask1);
-	setbits_le32(&reset_manager_base->per0modrst, mask0);
+	setbits_le32(&reset_manager_base->per_mod_reset, mask0 & ECC_MASK);
+	setbits_le32(&reset_manager_base->per2_mod_reset, mask1);
+	setbits_le32(&reset_manager_base->per_mod_reset, mask0);
 }
 
 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
 void socfpga_reset_deassert_osc1wd0(void)
 {
-	clrbits_le32(&reset_manager_base->per1modrst,
+	clrbits_le32(&reset_manager_base->per2_mod_reset,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
 /*
- * Assert or de-assert SoCFPGA reset manager reset.
- */
-void socfpga_per_reset(u32 reset, int set)
-{
-	const u32 *reg;
-	u32 rstmgr_bank = RSTMGR_BANK(reset);
-
-	switch (rstmgr_bank) {
-	case 0:
-		reg = &reset_manager_base->mpumodrst;
-		break;
-	case 1:
-		reg = &reset_manager_base->per0modrst;
-		break;
-	case 2:
-		reg = &reset_manager_base->per1modrst;
-		break;
-	case 3:
-		reg = &reset_manager_base->brgmodrst;
-		break;
-	case 4:
-		reg = &reset_manager_base->sysmodrst;
-		break;
-
-	default:
-		return;
-	}
-
-	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
-	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
-}
-
-/*
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
@@ -310,11 +275,11 @@ void socfpga_per_reset_all(void)
 		ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
 
 	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
-	writel(~l4wd0, &reset_manager_base->per1modrst);
-	setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+	writel(~l4wd0, &reset_manager_base->per2_mod_reset);
+	setbits_le32(&reset_manager_base->per_mod_reset, ~mask_ecc_ocp);
 
 	/* Finally disable the ECC_OCP */
-	setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+	setbits_le32(&reset_manager_base->per_mod_reset, mask_ecc_ocp);
 }
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
@@ -367,7 +332,7 @@ int socfpga_bridges_reset(void)
 		return ret;
 
 	/* Put all bridges (except NOR DDR scheduler) into reset state */
-	setbits_le32(&reset_manager_base->brgmodrst,
+	setbits_le32(&reset_manager_base->brg_mod_reset,
 		     (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
 		     ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
 		     ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index aa88adb..0abb519 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -18,39 +18,6 @@ static const struct socfpga_reset_manager *reset_manager_base =
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
-void socfpga_per_reset(u32 reset, int set)
-{
-	const u32 *reg;
-	u32 rstmgr_bank = RSTMGR_BANK(reset);
-
-	switch (rstmgr_bank) {
-	case 0:
-		reg = &reset_manager_base->mpu_mod_reset;
-		break;
-	case 1:
-		reg = &reset_manager_base->per_mod_reset;
-		break;
-	case 2:
-		reg = &reset_manager_base->per2_mod_reset;
-		break;
-	case 3:
-		reg = &reset_manager_base->brg_mod_reset;
-		break;
-	case 4:
-		reg = &reset_manager_base->misc_mod_reset;
-		break;
-
-	default:
-		return;
-	}
-
-	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
-	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
-}
-
 /*
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
new file mode 100644
index 0000000..2dc050c
--- /dev/null
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+static const struct socfpga_system_manager *system_manager_base =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	/* disable all except OCP and l4wd0. OCP disable later */
+	writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+	       &reset_manager_base->per_mod_reset);
+	writel(~l4wd0, &reset_manager_base->per_mod_reset);
+	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
+void socfpga_bridges_reset(int enable)
+{
+	if (enable) {
+		/* clear idle request to all bridges */
+		setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+
+		/* Release bridges from reset state per handoff value */
+		clrbits_le32(&reset_manager_base->brg_mod_reset, ~0);
+
+		/* Poll until all idleack to 0 */
+		while (readl(&system_manager_base->noc_idleack))
+			;
+	} else {
+		/* set idle request to all bridges */
+		writel(~0, &system_manager_base->noc_idlereq_set);
+
+		/* Enable the NOC timeout */
+		writel(1, &system_manager_base->noc_timeout);
+
+		/* Poll until all idleack to 1 */
+		while ((readl(&system_manager_base->noc_idleack) ^
+			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+			;
+
+		/* Poll until all idlestatus to 1 */
+		while ((readl(&system_manager_base->noc_idlestatus) ^
+			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+			;
+
+		/* Put all bridges (except NOR DDR scheduler) into reset */
+		setbits_le32(&reset_manager_base->brg_mod_reset,
+			     ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+
+		/* Disable NOC timeout */
+		writel(0, &system_manager_base->noc_timeout);
+	}
+}
+
+/* of_reset_id: emac reset id
+ * state: 0 - disable reset, !0 - enable reset
+ */
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
+{
+	u32 reset_emac;
+	u32 reset_emacocp;
+
+	/* hardcode this now */
+	switch (of_reset_id) {
+	case EMAC0_RESET:
+		reset_emac = SOCFPGA_RESET(EMAC0);
+		reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
+		break;
+	case EMAC1_RESET:
+		reset_emac = SOCFPGA_RESET(EMAC1);
+		reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
+		break;
+	case EMAC2_RESET:
+		reset_emac = SOCFPGA_RESET(EMAC2);
+		reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
+		break;
+	default:
+		printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+		hang();
+		break;
+	}
+
+	/* Reset ECC OCP first */
+	socfpga_per_reset(reset_emacocp, state);
+
+	/* Release the EMAC controller from reset */
+	socfpga_per_reset(reset_emac, state);
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per2_mod_reset);
+	/* Enable OCP first */
+	writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per_mod_reset);
+	writel(0, &reset_manager_base->per_mod_reset);
+}
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
new file mode 100644
index 0000000..29eb829
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+
+/* MPUMODRST */
+#define CPU0_RESET		0
+#define CPU1_RESET		1
+#define CPU2_RESET		2
+#define CPU3_RESET		3
+
+/* PER0MODRST */
+#define EMAC0_RESET		32
+#define EMAC1_RESET		33
+#define EMAC2_RESET		34
+#define USB0_RESET		35
+#define USB1_RESET		36
+#define NAND_RESET		37
+/* 38 is empty*/
+#define SDMMC_RESET		39
+#define EMAC0OCP_RESET		40
+#define EMAC1OCP_RESET		41
+#define EMAC2OCP_RESET		42
+#define USB0OCP_RESET		43
+#define USB1OCP_RESET		44
+#define NANDOCP_RESET		45
+/* 46 is empty*/
+#define SDMMCOCP_RESET		47
+#define DMA_RESET		48
+#define SPIM0_RESET		49
+#define SPIM1_RESET		50
+#define SPIS0_RESET		51
+#define SPIS1_RESET		52
+#define DMAOCP_RESET		53
+#define EMACPTP_RESET		54
+/* 55 is empty*/
+#define DMAIF0_RESET		56
+#define DMAIF1_RESET		57
+#define DMAIF2_RESET		58
+#define DMAIF3_RESET		59
+#define DMAIF4_RESET		60
+#define DMAIF5_RESET		61
+#define DMAIF6_RESET		62
+#define DMAIF7_RESET		63
+
+/* PER1MODRST */
+#define L4WD0_RESET		64
+#define L4WD1_RESET		65
+#define L4WD2_RESET		66
+#define L4WD3_RESET		67
+#define L4SYSTIMER0_RESET	68
+#define L4SYSTIMER1_RESET	69
+#define SPTIMER0_RESET		70
+#define SPTIMER1_RESET		71
+#define I2C0_RESET		72
+#define I2C1_RESET		73
+#define I2C2_RESET		74
+#define I2C3_RESET		75
+#define I2C4_RESET		76
+/* 77-79 is reserved */
+#define UART0_RESET		80
+#define UART1_RESET		81
+/* 82-87 is reserved */
+#define GPIO0_RESET		88
+#define GPIO1_RESET		89
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET		96
+#define LWHPS2FPGA_RESET	97
+#define FPGA2HPS_RESET		98
+#define F2SSDRAM0_RESET		99
+#define F2SSDRAM1_RESET		100
+#define F2SSDRAM2_RESET		101
+#define DDRSCH_RESET		102
+
+/* 128-159 is reserved */
+
+/* COLDMODRST */
+#define CPUPOR0_RESET		160
+#define CPUPOR1_RESET		161
+#define CPUPOR2_RESET		162
+#define CPUPOR3_RESET		163
+/* 164-167 is reserved */
+#define L2_RESET		168
+
+/* 192-223 is reserved */
+
+/* DBGMODRST */
+#define DBG_RESET		224
+#define CSDAP_RESET		225
+
+#endif
-- 
2.2.2

[U-Boot] [PATCH v2 04/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |   2 +
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +++++++++++++++++++++
 arch/arm/mach-socfpga/system_manager_s10.c         |  91 +++++++++++
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c     |  55 +++++++
 5 files changed, 321 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f10b05c..910eb6f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -33,6 +33,8 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= reset_manager_s10.o
+obj-y	+= system_manager_s10.o
+obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e6d4280..80c7d0b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,6 +7,9 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/system_manager_s10.h>
+#else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
 #define SYSMGR_ECC_OCRAM_EN	BIT(0)
@@ -89,5 +92,5 @@
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel)		\
 		(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
-
+#endif
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
new file mode 100644
index 0000000..d992072
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_SYSTEM_MANAGER_S10_
+#define	_SYSTEM_MANAGER_S10_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+	/* System Manager Module */
+	u32	siliconid1;			/* 0x00 */
+	u32	siliconid2;
+	u32	wddbg;
+	u32	_pad_0xc;
+	u32	mpu_status;			/* 0x10 */
+	u32	mpu_ace;
+	u32	_pad_0x18_0x1c[2];
+	u32	dma;				/* 0x20 */
+	u32	dma_periph;
+	/* SDMMC Controller Group */
+	u32	sdmmcgrp_ctrl;
+	u32	sdmmcgrp_l3master;
+	/* NAND Flash Controller Register Group */
+	u32	nandgrp_bootstrap;		/* 0x30 */
+	u32	nandgrp_l3master;
+	/* USB Controller Group */
+	u32	usb0_l3master;
+	u32	usb1_l3master;
+	/* EMAC Group */
+	u32	emac_gbl;			/* 0x40 */
+	u32	emac0;
+	u32	emac1;
+	u32	emac2;
+	u32	emac0_ace;			/* 0x50 */
+	u32	emac1_ace;
+	u32	emac2_ace;
+	u32	nand_axuser;
+	u32	_pad_0x60_0x64[2];		/* 0x60 */
+	/* FPGA interface Group */
+	u32	fpgaintf_en_1;
+	u32	fpgaintf_en_2;
+	u32	fpgaintf_en_3;			/* 0x70 */
+	u32	dma_l3master;
+	u32	etr_l3master;
+	u32	_pad_0x7c;
+	u32	sec_ctrl_slt;			/* 0x80 */
+	u32	osc_trim;
+	u32	_pad_0x88_0x8c[2];
+	/* ECC Group */
+	u32	ecc_intmask_value;		/* 0x90 */
+	u32	ecc_intmask_set;
+	u32	ecc_intmask_clr;
+	u32	ecc_intstatus_serr;
+	u32	ecc_intstatus_derr;		/* 0xa0 */
+	u32	_pad_0xa4_0xac[3];
+	u32	noc_addr_remap;			/* 0xb0 */
+	u32	hmc_clk;
+	u32	io_pa_ctrl;
+	u32	_pad_0xbc;
+	/* NOC Group */
+	u32	noc_timeout;			/* 0xc0 */
+	u32	noc_idlereq_set;
+	u32	noc_idlereq_clr;
+	u32	noc_idlereq_value;
+	u32	noc_idleack;			/* 0xd0 */
+	u32	noc_idlestatus;
+	u32	fpga2soc_ctrl;
+	u32	fpga_config;
+	u32	iocsrclk_gate;			/* 0xe0 */
+	u32	gpo;
+	u32	gpi;
+	u32	_pad_0xec;
+	u32	mpu;				/* 0xf0 */
+	u32	sdm_hps_spare;
+	u32	hps_sdm_spare;
+	u32	_pad_0xfc_0x1fc[65];
+	/* Boot scratch register group */
+	u32	boot_scratch_cold0;		/* 0x200 */
+	u32	boot_scratch_cold1;
+	u32	boot_scratch_cold2;
+	u32	boot_scratch_cold3;
+	u32	boot_scratch_cold4;		/* 0x210 */
+	u32	boot_scratch_cold5;
+	u32	boot_scratch_cold6;
+	u32	boot_scratch_cold7;
+	u32	boot_scratch_cold8;		/* 0x220 */
+	u32	boot_scratch_cold9;
+	u32	_pad_0x228_0xffc[886];
+	/* Pin select and pin control group */
+	u32	pinsel0[40];			/* 0x1000 */
+	u32	_pad_0x10a0_0x10fc[24];
+	u32	pinsel40[8];
+	u32	_pad_0x1120_0x112c[4];
+	u32	ioctrl0[28];
+	u32	_pad_0x11a0_0x11fc[24];
+	u32	ioctrl28[20];
+	u32	_pad_0x1250_0x12fc[44];
+	/* Use FPGA mux */
+	u32	rgmii0usefpga;			/* 0x1300 */
+	u32	rgmii1usefpga;
+	u32	rgmii2usefpga;
+	u32	i2c0usefpga;
+	u32	i2c1usefpga;
+	u32	i2c_emac0_usefpga;
+	u32	i2c_emac1_usefpga;
+	u32	i2c_emac2_usefpga;
+	u32	nandusefpga;
+	u32	_pad_0x1324;
+	u32	spim0usefpga;
+	u32	spim1usefpga;
+	u32	spis0usefpga;
+	u32	spis1usefpga;
+	u32	uart0usefpga;
+	u32	uart1usefpga;
+	u32	mdio0usefpga;
+	u32	mdio1usefpga;
+	u32	mdio2usefpga;
+	u32	_pad_0x134c;
+	u32	jtagusefpga;
+	u32	sdmmcusefpga;
+	u32	hps_osc_clk;
+	u32	_pad_0x135c_0x13fc[41];
+	u32	iodelay0[40];
+	u32	_pad_0x14a0_0x14fc[24];
+	u32	iodelay40[8];
+
+};
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	(1 << 0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	(1 << 1)
+#define SYSMGR_ECC_OCRAM_EN	(1 << 0)
+#define SYSMGR_ECC_OCRAM_SERR	(1 << 3)
+#define SYSMGR_ECC_OCRAM_DERR	(1 << 4)
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+
+#define SYSMGR_FPGAINTF_NAND	(1 << 4)
+#define SYSMGR_FPGAINTF_SDMMC	(1 << 8)
+#define SYSMGR_FPGAINTF_SPIM0	(1 << 16)
+#define SYSMGR_FPGAINTF_SPIM1	(1 << 24)
+#define SYSMGR_FPGAINTF_EMAC0	(0x11 << 0)
+#define SYSMGR_FPGAINTF_EMAC1	(0x11 << 8)
+#define SYSMGR_FPGAINTF_EMAC2	(0x11 << 16)
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
+#define SYSMGR_NOC_H2F_MSK		0x00000001
+#define SYSMGR_NOC_LWH2F_MSK		0x00000010
+#define SYSMGR_HMC_CLK_STATUS_MSK	0x00000001
+
+#endif /* _SYSTEM_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
new file mode 100644
index 0000000..8c7a715
--- /dev/null
+++ b/arch/arm/mach-socfpga/system_manager_s10.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+	populate_sysmgr_pinmux();
+	populate_sysmgr_fpgaintf_module();
+}
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+void populate_sysmgr_fpgaintf_module(void)
+{
+	uint32_t handoff_val = 0;
+
+	/* Enable the signal for those HPS peripherals that use FPGA. */
+	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_NAND;
+	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+	writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
+
+	handoff_val = 0;
+	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+	if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC2;
+	writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
+}
+
+/*
+ * Configure all the pin muxes
+ */
+void populate_sysmgr_pinmux(void)
+{
+	const u32 *sys_mgr_table_u32;
+	unsigned int len, i;
+
+	/* setup the pin sel */
+	sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i+2) {
+		writel(sys_mgr_table_u32[i+1],
+		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
+	}
+
+	/* setup the pin ctrl */
+	sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i+2) {
+		writel(sys_mgr_table_u32[i+1],
+		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
+	}
+
+	/* setup the fpga use */
+	sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i+2) {
+		writel(sys_mgr_table_u32[i+1],
+		       sys_mgr_table_u32[i] +
+		       (u8 *)&sysmgr_regs->rgmii0usefpga);
+	}
+
+	/* setup the IO delay */
+	sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
+	for (i = 0; i < len; i = i+2) {
+		writel(sys_mgr_table_u32[i+1],
+		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
+	}
+}
diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
new file mode 100644
index 0000000..b6a9f68
--- /dev/null
+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+
+static void sysmgr_pinmux_handoff_read(void *handoff_address,
+				const u32 **table, unsigned int *table_len)
+{
+	unsigned int handoff_entry = (swab32(readl(handoff_address +
+					CONFIG_HANDOFF_OFFSET_LENGTH)) -
+					CONFIG_HANDOFF_OFFSET_DATA) /
+					sizeof(unsigned int);
+	unsigned int handoff_chunk[handoff_entry], temp, i;
+
+	if (swab32(readl(CONFIG_HANDOFF_MUX)) == CONFIG_HANDOFF_MAGIC_MUX) {
+		/* using handoff from Quartus tools if exists */
+		for (i = 0; i < handoff_entry; i++) {
+			temp = readl(handoff_address +
+				     CONFIG_HANDOFF_OFFSET_DATA + (i * 4));
+			handoff_chunk[i] = swab32(temp);
+		}
+		*table = handoff_chunk;
+		*table_len = ARRAY_SIZE(handoff_chunk);
+	}
+}
+
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_MUX, table,
+				   table_len);
+}
+
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_IOCTL, table,
+				   table_len);
+}
+
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_FPGA, table,
+				   table_len);
+}
+
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)
+{
+	sysmgr_pinmux_handoff_read((void *)CONFIG_HANODFF_DELAY, table,
+				   table_len);
+}
-- 
2.2.2

[U-Boot] [PATCH v2 05/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile            |   1 +
 arch/arm/mach-socfpga/include/mach/misc.h |   1 +
 arch/arm/mach-socfpga/misc.c              |  76 ++++++++++++++++++++
 arch/arm/mach-socfpga/misc_gen5.c         |  75 ++-----------------
 arch/arm/mach-socfpga/misc_s10.c          | 115 ++++++++++++++++++++++++++++++
 5 files changed, 197 insertions(+), 71 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 0b65783..8466023 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -8,6 +8,7 @@
 #define _MISC_H_
 
 void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+int socfpga_eth_reset(void);
 
 struct bsel {
 	const char	*mode;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 00eff90..cee3296 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -20,11 +20,14 @@
 #include <asm/arch/nic301.h>
 #include <asm/arch/scu.h>
 #include <asm/pl310.h>
+#include <asm/arch/sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
 
 struct bsel bsel_str[] = {
 	{ "rsvd", "Reserved", },
@@ -53,6 +56,7 @@ void enable_caches(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
 	/* Disable the L2 cache */
@@ -73,6 +77,7 @@ void v7_outer_cache_disable(void)
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
+#endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
@@ -136,3 +141,74 @@ int arch_cpu_init(void)
 
 	return 0;
 }
+
+#if !defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+	if (!phymode)
+		return -EINVAL;
+
+	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rgmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+#endif
+
+#ifdef CONFIG_ETH_DESIGNWARE
+int socfpga_eth_reset(void)
+{
+	const void *fdt = gd->fdt_blob;
+	struct fdtdec_phandle_args args;
+	const char *phy_mode;
+	u32 phy_modereg;
+	int nodes[3];	/* Max. 3 GMACs */
+	int ret, count;
+	int i, node;
+
+	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+					   COMPAT_ALTERA_SOCFPGA_DWMAC,
+					   nodes, ARRAY_SIZE(nodes));
+	for (i = 0; i < count; i++) {
+		node = nodes[i];
+		if (node <= 0)
+			continue;
+
+		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+						     "#reset-cells", 1, 0,
+						     &args);
+		if (ret || (args.args_count != 1)) {
+			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+			continue;
+		}
+
+		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+		if (ret) {
+			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+			continue;
+		}
+
+		dwmac_deassert_reset(args.args[0], phy_modereg);
+	}
+
+	return 0;
+}
+#else
+int socfpga_eth_reset(void)
+{
+	return 0;
+};
+#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 91ddb79..6149c8a 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -67,77 +67,6 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
 	/* Release the EMAC controller from reset */
 	socfpga_per_reset(reset, 0);
 }
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-	if (!phymode)
-		return -EINVAL;
-
-	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
-		return 0;
-	}
-
-	if (!strcmp(phymode, "rgmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
-		return 0;
-	}
-
-	if (!strcmp(phymode, "rmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
-		return 0;
-	}
-
-	return -EINVAL;
-}
-
-static int socfpga_eth_reset(void)
-{
-	const void *fdt = gd->fdt_blob;
-	struct fdtdec_phandle_args args;
-	const char *phy_mode;
-	u32 phy_modereg;
-	int nodes[2];	/* Max. two GMACs */
-	int ret, count;
-	int i, node;
-
-	/* Put both GMACs into RESET state. */
-	socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-	socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
-	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
-					   COMPAT_ALTERA_SOCFPGA_DWMAC,
-					   nodes, ARRAY_SIZE(nodes));
-	for (i = 0; i < count; i++) {
-		node = nodes[i];
-		if (node <= 0)
-			continue;
-
-		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-						     "#reset-cells", 1, 0,
-						     &args);
-		if (ret || (args.args_count != 1)) {
-			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
-			continue;
-		}
-
-		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
-		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
-		if (ret) {
-			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
-			continue;
-		}
-
-		dwmac_deassert_reset(args.args[0], phy_modereg);
-	}
-
-	return 0;
-}
-#else
-static int socfpga_eth_reset(void)
-{
-	return 0;
-};
 #endif
 
 static const struct {
@@ -222,6 +151,10 @@ int arch_misc_init(void)
 	env_set("bootmode", bsel_str[bsel].mode);
 	if (fpga_id >= 0)
 		env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
+
+	/* Put both GMACs into RESET state. */
+	socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
 	return socfpga_eth_reset();
 }
 #endif
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
new file mode 100644
index 0000000..cc45dcc
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <altera.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+				 const u32 phymode)
+{
+	/* Put the emac we're using into reset.
+	 * This is required before configuring the PHY interface
+	 */
+	socfpga_emac_manage_reset(of_reset_id, 1);
+
+	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
+			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+			phymode);
+
+	socfpga_emac_manage_reset(of_reset_id, 0);
+}
+#endif
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	puts("CPU:   Intel FPGA SoCFPGA Platform\n");
+	puts("FPGA:  Intel FPGA Stratix 10\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	return socfpga_eth_reset();
+}
+#endif
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+		socfpga_sdram_apply_static_cfg();
+		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+		writel(iswgrp_handoff[1], &nic301_regs->remap);
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+		socfpga_bridges_reset(1);
+#endif
+		break;
+	case 'd':	/* Disable */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+		writel(0, &sysmgr_regs->fpgaintfgrp_module);
+		writel(0, &sdr_ctrl->fpgaport_rst);
+		socfpga_sdram_apply_static_cfg();
+		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(1, &nic301_regs->remap);
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+		socfpga_bridges_reset(0);
+#endif
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bridge, 2, 1, do_bridge,
+	"SoCFPGA HPS FPGA bridge control",
+	"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	""
+);
-- 
2.2.2

[U-Boot] [PATCH v2 06/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add mailbox support for Stratix SoC

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile                   |   1 +
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++++++++++
 arch/arm/mach-socfpga/mailbox_s10.c              | 238 +++++++++++++++++++++++
 3 files changed, 347 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b253914..43e18d2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
new file mode 100644
index 0000000..b9bddf6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#define MBOX_CLIENT_ID_UBOOT	0xB
+#define MBOX_ID_UBOOT		0x1
+
+#define MBOX_MAX_CMD_INDEX	2047
+#define MBOX_CMD_BUFFER_SIZE	32
+#define MBOX_RESP_BUFFER_SIZE	16
+
+#define MBOX_HDR_CMD_LSB	0
+#define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
+#define MBOX_HDR_I_LSB		11
+#define MBOX_HDR_I_MSK		BIT(11)
+#define MBOX_HDR_LEN_LSB	12
+#define MBOX_HDR_LEN_MSK	0x007FF000
+#define MBOX_HDR_ID_LSB		24
+#define MBOX_HDR_ID_MSK		0x0F000000
+#define MBOX_HDR_CLIENT_LSB	28
+#define MBOX_HDR_CLIENT_MSK	0xF0000000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
+				 MBOX_FLAGS_INT_RIE | \
+				 MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK	BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, cmd)		   \
+	(((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
+	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)	 | \
+	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)
+
+#define MBOX_RESP_ERR_GET(resp)				\
+	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)			\
+	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp)				\
+	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp)			\
+	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+typedef enum {
+	/* CMD completed succesfully, but check resp ARGS for any errors */
+	MBOX_RESP_STATOK = 0,
+	/* CMD is incorrectly formatted in some way */
+	MBOX_RESP_INVALID_COMMAND = 1,
+	/* BootROM Command code not undesrtood */
+	MBOX_RESP_UNKNOWN_BR = 2,
+	/* CMD code not recognized by firmware */
+	MBOX_RESP_UNKNOWN = 3,
+	/* Indicates that the device is not configured */
+	MBOX_RESP_NOT_CONFIGURED = 256,
+	/* Indicates that the device is busy */
+	MBOX_RESP_DEVICE_BUSY = 0x1FF,
+	/* Indicates that there is no valid response available */
+	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+	/* General Error */
+	MBOX_RESP_ERROR = 0x3FF,
+} ALT_SDM_MBOX_RESP_CODE;
+
+/* Mailbox command list */
+#define MBOX_RESTART		2
+#define MBOX_QSPI_OPEN		50
+#define MBOX_QSPI_CLOSE		51
+#define MBOX_QSPI_DIRECT	59
+
+struct socfpga_mailbox {
+	u32 cin;		/* command valid offset */
+	u32 rout;		/* response output offset */
+	u32 urg;		/* urgent command */
+	u32 flags;		/* interrupt enables */
+	u32 pad_0x10_0x1f[4];	/* 0x10 - 0x1F reserved */
+	u32 cout;		/* command free offset */
+	u32 rin;		/* respond valid offset */
+	u32 pad_0x28;		/* 0x28 reserved */
+	u32 status;		/* mailbox status */
+	u32 pad_0x30_0x3f[4];	/* 0x30 - 0x3F reserved */
+	u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];	/* 0x40 - 0xBC circular command
+						   buffer to SDM */
+	u32 resp_buf[MBOX_RESP_BUFFER_SIZE];	/* 0xC0 - 0xFF circular
+						   response buffer */
+};
+
+/* Use define other than put into struct socfpga_mailbox to save spaces */
+#define MBOX_DOORBELL_TO_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x400)
+#define MBOX_DOORBELL_FROM_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x480)
+
+int mbox_init(void);
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void);
+int mbox_qspi_open(void);
+#endif
+
+#endif	/* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
new file mode 100644
index 0000000..de836b1
--- /dev/null
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <asm/arch/mailbox_s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_mailbox *mbox_base =
+		(void *)SOCFPGA_MAILBOX_ADDRESS;
+
+#define MBOX_POLL_RESP_TIMEOUT		50 /* ms */
+
+static int mbox_polling_resp(u32 rout)
+{
+	u32 rin;
+	unsigned long start = get_timer(0);
+
+	while (1) {
+		rin = readl(&mbox_base->rin);
+		if (rout != rin)
+			return 0;
+
+		if (get_timer(start) > MBOX_POLL_RESP_TIMEOUT)
+			break;
+
+		udelay(1);
+	}
+
+	debug("mailbox: polling response timeout\n");
+	return -ETIMEDOUT;
+}
+
+/* Check for available slot and write to circular buffer.
+ * It also update command valid offset (cin) register.
+ */
+static int mbox_fill_cmd_circular_buff(u32 header, u32 len, u32 *arg)
+{
+	u32 cmd_free_offset;
+	u32 i;
+
+	/* checking available command free slot */
+	cmd_free_offset = readl(&mbox_base->cout);
+	if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {
+		error("ERROR: Not enough space, cout %d\n", cmd_free_offset);
+		return -ENOMEM;
+	}
+
+	/* write header to circular buffer */
+	writel(header, &mbox_base->cmd_buf[cmd_free_offset++]);
+	/* wrapping around when it reach the buffer size */
+	cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
+
+	/* write arguments */
+	for (i = 0; i < len; i++) {
+		writel(arg[i], &mbox_base->cmd_buf[cmd_free_offset++]);
+		/* wrapping around when it reach the buffer size */
+		cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
+	}
+
+	/* write command valid offset */
+	writel(cmd_free_offset, &mbox_base->cin);
+	return 0;
+}
+
+/* Support one command and up to 31 words argument length only */
+int mbox_send_cmd(u8 id, u32 cmd, u32 len, u32 *arg, u8 urgent,
+			u32 *resp_buf_len, u32 *resp_buf)
+{
+	u32 header;
+	u32 rin;
+	u32 resp;
+	u32 rout;
+	u32 status;
+	u32 resp_len;
+	u32 buf_len;
+	int ret;
+
+	/* Total lenght is command + argument length */
+	if ((len + 1) > MBOX_CMD_BUFFER_SIZE) {
+		error("ERROR: command %d arguments too long, max %d\n", cmd,
+		      MBOX_CMD_BUFFER_SIZE - 1);
+		return -EINVAL;
+	}
+
+	if (cmd > MBOX_MAX_CMD_INDEX) {
+		error("ERROR: Unsupported command index %d\n", cmd);
+		return -EINVAL;
+	}
+
+	header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id , len, cmd);
+
+	ret = mbox_fill_cmd_circular_buff(header, len, arg);
+	if (ret)
+		return ret;
+
+	if (urgent) {
+		/* Send command as urgent command */
+		writel(1, &mbox_base->urg);
+	}
+
+	/* write doorbell */
+	writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+	while (1) {
+		/* Wait for doorbell from SDM */
+		ret = wait_for_bit(__func__,
+				   (const u32 *)MBOX_DOORBELL_FROM_SDM_REG,
+				   1, true, 500000, false);
+		if (ret) {
+			error("mailbox: timeout from SDM\n");
+			return ret;
+		}
+
+		/* clear interrupt */
+		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+		if (urgent) {
+			/* urgent command doesn't has response */
+			writel(0, &mbox_base->urg);
+			status = readl(&mbox_base->status);
+			if (status & MBOX_STATUS_UA_MSK)
+				return 0;
+
+			error("mailbox: cmd %d no urgent ACK\n", cmd);
+			return -1;
+		}
+
+		/* read current response offset */
+		rout = readl(&mbox_base->rout);
+
+		/* read response valid offset */
+		rin = readl(&mbox_base->rin);
+
+		if (rout != rin) {
+			/* Response received */
+			resp = readl(&mbox_base->resp_buf[rout]);
+			rout++;
+			/* wrapping around when it reach the buffer size */
+			rout %= MBOX_RESP_BUFFER_SIZE;
+			/* update next ROUT */
+			writel(rout, &mbox_base->rout);
+
+			/* check client ID and ID */
+			if ((MBOX_RESP_CLIENT_GET(resp) ==
+			    MBOX_CLIENT_ID_UBOOT) &&
+			    (MBOX_RESP_ID_GET(resp) == id)) {
+				ret = MBOX_RESP_ERR_GET(resp);
+				if (ret) {
+					error("mailbox send command %d error %d\n",
+					      cmd, ret);
+					return ret;
+				}
+
+				if (resp_buf_len) {
+					buf_len = *resp_buf_len;
+					*resp_buf_len = 0;
+				} else {
+					buf_len = 0;
+				}
+
+				resp_len = MBOX_RESP_LEN_GET(resp);
+				while (resp_len) {
+					ret = mbox_polling_resp(rout);
+					if (ret)
+						return ret;
+					/* we need to process response buffer
+					   even caller doesn't need it */
+					resp = readl(&mbox_base->resp_buf[rout]);
+					rout++;
+					resp_len--;
+					rout %= MBOX_RESP_BUFFER_SIZE;
+					writel(rout, &mbox_base->rout);
+					if (buf_len) {
+						/* copy response to buffer */
+						resp_buf[*resp_buf_len] = resp;
+						(*resp_buf_len)++;
+						buf_len--;
+					}
+				}
+				return ret;
+			}
+		}
+	};
+
+	return -EIO;
+}
+
+int mbox_init(void)
+{
+	int ret;
+
+	/* enable mailbox interrupts */
+	writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, 0, NULL, 1, 0, NULL);
+	if (ret)
+		return ret;
+
+	/* Renable mailbox interrupts after MBOX_RESTART */
+	writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+	return 0;
+}
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, 0, NULL, 0, 0,
+			     NULL);
+}
+
+int mbox_qspi_open(void)
+{
+	int ret;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, 0, NULL, 0, 0, NULL);
+	if (ret)
+		return ret;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, 0, NULL, 0, 0,
+			    NULL);
+	if (ret)
+		goto error;
+
+	return ret;
+
+error:
+	mbox_qspi_close();
+
+	return ret;
+}
+#endif /* CONFIG_CADENCE_QSPI */
-- 
2.2.2

[U-Boot] [PATCH v2 07/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile        |  1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 43e18d2..098e5e9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 0000000..91c7f2e
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+	{
+		/* MEM 2GB*/
+		.virt	= 0x0UL,
+		.phys	= 0x0UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* FPGA 1.5GB */
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x60000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* DEVICE 142MB */
+		.virt	= 0xF7000000UL,
+		.phys	= 0xF7000000UL,
+		.size	= 0x08E00000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* OCRAM 1MB but available 256KB */
+		.virt	= 0xFFE00000UL,
+		.phys	= 0xFFE00000UL,
+		.size	= 0x00100000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 32KB */
+		.virt	= 0xFFFC0000UL,
+		.phys	= 0xFFFC0000UL,
+		.size	= 0x00008000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* MEM 124GB */
+		.virt	= 0x0100000000UL,
+		.phys	= 0x0100000000UL,
+		.size	= 0x1F00000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 4GB */
+		.virt	= 0x2000000000UL,
+		.phys	= 0x2000000000UL,
+		.size	= 0x0100000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* List terminator */
+	},
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
2.2.2

[U-Boot] [PATCH v2 08/14] arm: dts: Add dts for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Device tree for Stratix10 SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/dts/Makefile                    |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 180 +++++++++++++++++++++++++++++++
 2 files changed, 182 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c062f0..f66b9c9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
-	socfpga_cyclone5_vining_fpga.dtb
+	socfpga_cyclone5_vining_fpga.dtb		\
+	socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
 	dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 0000000..26b407f
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+/ {
+	model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+	compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		ethernet0 = &gmac0;
+		spi0 = &qspi;
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x2>;
+		};
+
+		cpu at 3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x3>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		device_type = "soc";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		rst: rstmgr at ffd11000 {
+			#reset-cells = <1>;
+			compatible = "altr,rst-mgr";
+			reg = <0xffd11000 0x100>;
+			altr,modrst-offset = <0x20>;
+		};
+
+		mdio {
+			phy0: ethernet-phy at 0 {
+				txd0-skew-ps = <0>; /* -420ps */
+				txd1-skew-ps = <0>; /* -420ps */
+				txd2-skew-ps = <0>; /* -420ps */
+				txd3-skew-ps = <0>; /* -420ps */
+				rxd0-skew-ps = <420>; /* 0ps */
+				rxd1-skew-ps = <420>; /* 0ps */
+				rxd2-skew-ps = <420>; /* 0ps */
+				rxd3-skew-ps = <420>; /* 0ps */
+				txen-skew-ps = <0>; /* -420ps */
+				txc-skew-ps = <1860>; /* 960ps */
+				rxdv-skew-ps = <420>; /* 0ps */
+				rxc-skew-ps = <1680>; /* 780ps */
+			};
+		};
+
+		gmac0: ethernet at ff800000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+			reg = <0xff800000 0x2000>;
+			interrupts = <0 90 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];
+			resets = <&rst EMAC0_RESET>;
+			reset-names = "stmmaceth";
+			phy-mode = "rgmii";
+			phy-addr = <0xffffffff>; /* probe for phy addr */
+			phy = <&phy0>;
+			max-speed = <1000>;
+			status = "okay";
+		};
+
+		mmc0: dwmmc0 at 0xff808000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0xff808000 0x1000>;
+			interrupts = <0 96 4>;
+			num-slots = <1>;
+			broken-cd;
+			bus-width = <4>;
+			fifo-depth = <0x400>;
+			cap-mmc-highspeed;
+			cap-sd-highspeed;
+			drvsel = <3>;
+			smplsel = <0>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+			vmmc-supply = <&regulator_3_3v>;
+			vqmmc-supply = <&regulator_3_3v>;
+		};
+
+		uart0: serial0 at ffc02000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xffc02000 0x1000>;
+			interrupts = <0 108 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "okay";
+		};
+
+		qspi: spi at ff8d2000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cadence,qspi";
+			reg = <0xff8d2000 0x100>,
+				<0xff900000 0x100000>;
+			interrupts = <0 98 4>;
+			sram-size = <1024>;
+			bus-num = <0>;
+			spi-max-frequency = <50000000>;
+			spi-tx-bus-width = <1>;
+			spi-rx-bus-width = <4>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+
+			flash0: n25q1024a at 0 {
+				u-boot,dm-pre-reloc;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "stmicro,n25q1024a";
+				reg = <0>;      /* chip select */
+				spi-max-frequency = <50000000>;
+				page-size = <256>;
+				block-size = <16>; /* 2^16, 64KB */
+				tshsl-ns = <50>;
+				tsd2d-ns = <50>;
+				tchsh-ns = <4>;
+				tslch-ns = <4>;
+			};
+		};
+	};
+};
-- 
2.2.2

[U-Boot] [PATCH v2 09/14] arm: socfpga: Restructure the SPL file

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile              |   5 +-
 arch/arm/mach-socfpga/spl_a10.c             | 105 ++++++++++++++++++++++++++++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c} |  46 ------------
 3 files changed, 109 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 098e5e9..b669d43 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,13 +41,16 @@ obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y	+= spl_gen5.o
 obj-y	+= freeze_controller.o
 obj-y	+= wrap_iocsr_config.o
 obj-y	+= wrap_pinmux_config.o
 obj-y	+= wrap_sdram_config.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y	+= spl_a10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
new file mode 100644
index 0000000..e6fc766
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pl310.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#include <asm/arch/pinmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+	const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+		socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	config_dedicated_pins(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	/* Release UART from reset */
+	socfpga_reset_uart(0);
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+	/*
+	 * Configure Clock Manager to use intosc clock instead external osc to
+	 * ensure success watchdog operation. We do it as early as possible.
+	 */
+	cm_use_intosc();
+
+	socfpga_watchdog_disable();
+
+	arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	socfpga_reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c
similarity index 83%
rename from arch/arm/mach-socfpga/spl.c
rename to arch/arm/mach-socfpga/spl_gen5.c
index 71bae82..9864082 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -22,21 +22,15 @@
 #include <asm/sections.h>
 #include <fdtdec.h>
 #include <watchdog.h>
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#include <asm/arch/pinmux.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#endif
-
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -77,7 +71,6 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
 	writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -193,42 +186,3 @@ void board_init_f(ulong dummy)
 	/* Configure simple malloc base pointer into RAM. */
 	gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-void spl_board_init(void)
-{
-	/* configuring the clock based on handoff */
-	cm_basic_init(gd->fdt_blob);
-	WATCHDOG_RESET();
-
-	config_dedicated_pins(gd->fdt_blob);
-	WATCHDOG_RESET();
-
-	/* Release UART from reset */
-	socfpga_reset_uart(0);
-
-	/* enable console uart printing */
-	preloader_console_init();
-}
-
-void board_init_f(ulong dummy)
-{
-	/*
-	 * Configure Clock Manager to use intosc clock instead external osc to
-	 * ensure success watchdog operation. We do it as early as possible.
-	 */
-	cm_use_intosc();
-
-	socfpga_watchdog_disable();
-
-	arch_early_init_r();
-
-#ifdef CONFIG_HW_WATCHDOG
-	/* release osc1 watchdog timer 0 from reset */
-	socfpga_reset_deassert_osc1wd0();
-
-	/* reconfigure and enable the watchdog */
-	hw_watchdog_init();
-	WATCHDOG_RESET();
-#endif /* CONFIG_HW_WATCHDOG */
-}
-#endif
-- 
2.2.2

[U-Boot] [PATCH v2 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile                    |   4 +
 arch/arm/mach-socfpga/include/mach/firewall_s10.h |  84 +++++++++++++
 arch/arm/mach-socfpga/spl_s10.c                   | 138 ++++++++++++++++++++++
 3 files changed, 226 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b669d43..35b124a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,7 @@ obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= spl_gen5.o
@@ -51,6 +52,9 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y	+= spl_a10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
new file mode 100644
index 0000000..6894bb9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_FIREWALL_S10_
+#define	_FIREWALL_S10_
+
+struct socfpga_firwall_l4_per {
+	u32	nand;		/* 0x00 */
+	u32	nand_data;
+	u32	_pad_0x8;
+	u32	usb0;
+	u32	usb1;		/* 0x10 */
+	u32	_pad_0x14;
+	u32	_pad_0x18;
+	u32	spim0;
+	u32	spim1;		/* 0x20 */
+	u32	spis0;
+	u32	spis1;
+	u32	emac0;
+	u32	emac1;		/* 0x30 */
+	u32	emac2;
+	u32	_pad_0x38;
+	u32	_pad_0x3c;
+	u32	sdmmc;		/* 0x40 */
+	u32	gpio0;
+	u32	gpio1;
+	u32	_pad_0x4c;
+	u32	i2c0;		/* 0x50 */
+	u32	i2c1;
+	u32	i2c2;
+	u32	i2c3;
+	u32	i2c4;		/* 0x60 */
+	u32	timer0;
+	u32	timer1;
+	u32	uart0;
+	u32	uart1;		/* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+	u32	_pad_0x00;		/* 0x00 */
+	u32	_pad_0x04;
+	u32	dma_ecc;
+	u32	emac0rx_ecc;
+	u32	emac0tx_ecc;		/* 0x10 */
+	u32	emac1rx_ecc;
+	u32	emac1tx_ecc;
+	u32	emac2rx_ecc;
+	u32	emac2tx_ecc;		/* 0x20 */
+	u32	_pad_0x24;
+	u32	_pad_0x28;
+	u32	nand_ecc;
+	u32	nand_read_ecc;		/* 0x30 */
+	u32	nand_write_ecc;
+	u32	ocram_ecc;
+	u32	_pad_0x3c;
+	u32	sdmmc_ecc;		/* 0x40 */
+	u32	usb0_ecc;
+	u32	usb1_ecc;
+	u32	clock_manager;
+	u32	_pad_0x50;		/* 0x50 */
+	u32	io_manager;
+	u32	reset_manager;
+	u32	system_manager;
+	u32	osc0_timer;		/* 0x60 */
+	u32	osc1_timer;
+	u32	watchdog0;
+	u32	watchdog1;
+	u32	watchdog2;		/* 0x70 */
+	u32	watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7004688
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7018628
+
+#define CCU_ADMASK_P_MASK			(BIT(0))
+#define CCU_ADMASK_NS_MASK			(BIT(1))
+
+#endif /* _FIREWALL_S10_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 0000000..12cafe6
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -0,0 +1,138 @@
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/sdram_s10.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/firewall_s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
+	(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
+static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
+	(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
+
+u32 spl_boot_device(void)
+{
+	/* TODO: Get from SDM or handoff */
+/* #ifdef CONFIG_CADENCE_QSPI*/
+#if 0
+	return BOOT_DEVICE_SPI;
+#else
+	return BOOT_DEVICE_MMC1;
+#endif
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
+	timer_init();
+
+	populate_sysmgr_pinmux();
+
+	/* configuring the HPS clocks */
+	cm_basic_init(cm_default_cfg);
+
+	/* enable console uart printing */
+#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)
+	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+	/* enables nonsecure access to UART0 */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);
+#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)
+	socfpga_per_reset(SOCFPGA_RESET(UART1), 0);
+	/* enables nonsecure access to UART1 */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);
+#endif
+
+	preloader_console_init();
+	cm_print_clock_quick_summary();
+
+	/* enable all EMACs */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);
+	/* enables nonsecure access to all the emacs */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);
+
+	/* enables SDMMC */
+	socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);
+	socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+	/* Enables nonsecure access to SDMMC */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);
+
+	/* enable i2c0 and i2c1 */
+	socfpga_per_reset(SOCFPGA_RESET(I2C0), 0);
+	socfpga_per_reset(SOCFPGA_RESET(I2C1), 0);
+	/* enables nonsecure access to i2c0 and i2c1 */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);
+
+	/* disable lwsocf2fpga and soc2fpga bridge security */
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
+
+	/* enables nonsecure access to clock mgr */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager);
+
+	/* enables nonsecure access to OCRAM */
+	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc);
+
+	/* disable ocram security at CCU for non secure access */
+	clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR,
+		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR,
+		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+
+	puts("DDR: Initializing Hard Memory Controller\n");
+	if (sdram_mmr_init_full(0)) {
+		puts("DDR: Initialization failed.\n");
+		hang();
+	}
+
+	gd->ram_size = sdram_calculate_size();
+	printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
+
+	/* Sanity check ensure correct SDRAM size specified */
+	puts("DDR: Running SDRAM size sanity check\n");
+	if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+	puts("DDR: SDRAM size check passed!\n");
+
+#ifdef CONFIG_CADENCE_QSPI
+	mbox_init();
+	mbox_qspi_open();
+#endif
+}
-- 
2.2.2

[U-Boot] [PATCH v2 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/timer.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..23450b0 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -1,5 +1,6 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -10,15 +11,29 @@
 
 #define TIMER_LOAD_VAL		0xFFFFFFFF
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+#endif
 
 /*
  * Timer initialization
  */
 int timer_init(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	int enable = 0x3;	/* timer enable + output signal masked */
+	int loadval = ~0;
+
+	/* enable system counter */
+	writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+	/* enable processor pysical counter */
+	asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+	asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+
+#else
 	writel(TIMER_LOAD_VAL, &timer_base->load_val);
 	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
 	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+#endif
 	return 0;
 }
-- 
2.2.2

[U-Boot] [PATCH v2 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +++++++++++++++++++++
 drivers/ddr/altera/Makefile                    |   1 +
 drivers/ddr/altera/sdram_s10.c                 | 382 +++++++++++++++++++++++++
 3 files changed, 716 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
new file mode 100644
index 0000000..d0fd958
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef	_SDRAM_S10_H_
+#define	_SDRAM_S10_H_
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+#define DDR_TWR				15
+#define DDR_READ_LATENCY_DELAY		40
+#define DDR_ACTIVATE_FAWBANK		0x1
+
+
+struct socfpga_ecc_hmc {
+	uint32_t ip_rev_id;
+	uint32_t _pad_0x4_0x7;
+	uint32_t ddrioctrl;
+	uint32_t ddrcalstat;
+	uint32_t mpr_0beat1;
+	uint32_t mpr_1beat1;
+	uint32_t mpr_2beat1;
+	uint32_t mpr_3beat1;
+	uint32_t mpr_4beat1;
+	uint32_t mpr_5beat1;
+	uint32_t mpr_6beat1;
+	uint32_t mpr_7beat1;
+	uint32_t mpr_8beat1;
+	uint32_t mpr_0beat2;
+	uint32_t mpr_1beat2;
+	uint32_t mpr_2beat2;
+	uint32_t mpr_3beat2;
+	uint32_t mpr_4beat2;
+	uint32_t mpr_5beat2;
+	uint32_t mpr_6beat2;
+	uint32_t mpr_7beat2;
+	uint32_t mpr_8beat2;
+	uint32_t _pad_0x58_0x5f[2];
+	uint32_t auto_precharge;
+	uint32_t _pad_0x64_0xdf[31];
+	uint32_t dramaddrwidth;
+	uint32_t _pad_0xe4_0xff[7];
+	uint32_t eccctrl;
+	uint32_t eccctrl2;
+	uint32_t _pad_0x108_0x10f[2];
+	uint32_t errinten;
+	uint32_t errintens;
+	uint32_t errintenr;
+	uint32_t intmode;
+	uint32_t intstat;
+	uint32_t diaginttest;
+	uint32_t modstat;
+	uint32_t derraddra;
+	uint32_t serraddra;
+	uint32_t _pad_0x134_0x137;
+	uint32_t autowb_corraddr;
+	uint32_t serrcntreg;
+	uint32_t autowb_drop_cntreg;
+	uint32_t ecc_reg2wreccdatabus;
+	uint32_t ecc_rdeccdata2regbus;
+	uint32_t ecc_reg2rdeccdatabus;
+	uint32_t ecc_diagon;
+	uint32_t ecc_decstat;
+	uint32_t _pad_0x158_0x15f[2];
+	uint32_t ecc_errgenaddr_0;
+	uint32_t ecc_errgenaddr_1;
+	uint32_t ecc_errgenaddr_2;
+	uint32_t ecc_errgenaddr_3;
+	uint32_t ecc_ref2rddatabus_beat0;
+	uint32_t ecc_ref2rddatabus_beat1;
+	uint32_t ecc_ref2rddatabus_beat2;
+	uint32_t ecc_ref2rddatabus_beat3;
+	uint32_t ecc_errgenhaddr_0;
+	uint32_t ecc_errgenhaddr_1;
+	uint32_t ecc_errgenhaddr_2;
+	uint32_t ecc_errgenhaddr_3;
+	uint32_t ecc_rdeccdata2regbus_beat0;
+	uint32_t ecc_rdeccdata2regbus_beat1;
+	uint32_t ecc_rdeccdata2regbus_beat2;
+	uint32_t ecc_rdeccdata2regbus_beat3;
+	uint32_t _pad_0x1a0_0x1af[4];
+	uint32_t derrhaddr;
+	uint32_t serrhaddr;
+	uint32_t _pad_0x1b8_0x1bb;
+	uint32_t autowb_corrhaddr;
+	uint32_t _pad_0x1c0_0x20f[20];
+	uint32_t hpsintfcsel;
+	uint32_t rsthandshakectrl;
+	uint32_t rsthandshakestat;
+};
+
+struct socfpga_noc_ddr_scheduler {
+	uint32_t main_scheduler_id_coreid;
+	uint32_t main_scheduler_id_revisionid;
+	uint32_t main_scheduler_ddrconf;
+	uint32_t main_scheduler_ddrtiming;
+	uint32_t main_scheduler_ddrmode;
+	uint32_t main_scheduler_readlatency;
+	uint32_t _pad_0x18_0x37[8];
+	uint32_t main_scheduler_activate;
+	uint32_t main_scheduler_devtodev;
+	uint32_t main_scheduler_ddr4timing;
+};
+
+struct socfpga_io48_mmr {
+	uint32_t dbgcfg0;
+	uint32_t dbgcfg1;
+	uint32_t dbgcfg2;
+	uint32_t dbgcfg3;
+	uint32_t dbgcfg4;
+	uint32_t dbgcfg5;
+	uint32_t dbgcfg6;
+	uint32_t reserve0;
+	uint32_t reserve1;
+	uint32_t reserve2;
+	uint32_t ctrlcfg0;
+	uint32_t ctrlcfg1;
+	uint32_t ctrlcfg2;
+	uint32_t ctrlcfg3;
+	uint32_t ctrlcfg4;
+	uint32_t ctrlcfg5;
+	uint32_t ctrlcfg6;
+	uint32_t ctrlcfg7;
+	uint32_t ctrlcfg8;
+	uint32_t ctrlcfg9;
+	uint32_t dramtiming0;
+	uint32_t dramodt0;
+	uint32_t dramodt1;
+	uint32_t sbcfg0;
+	uint32_t sbcfg1;
+	uint32_t sbcfg2;
+	uint32_t sbcfg3;
+	uint32_t sbcfg4;
+	uint32_t sbcfg5;
+	uint32_t sbcfg6;
+	uint32_t sbcfg7;
+	uint32_t caltiming0;
+	uint32_t caltiming1;
+	uint32_t caltiming2;
+	uint32_t caltiming3;
+	uint32_t caltiming4;
+	uint32_t caltiming5;
+	uint32_t caltiming6;
+	uint32_t caltiming7;
+	uint32_t caltiming8;
+	uint32_t caltiming9;
+	uint32_t caltiming10;
+	uint32_t dramaddrw;
+	uint32_t sideband0;
+	uint32_t sideband1;
+	uint32_t sideband2;
+	uint32_t sideband3;
+	uint32_t sideband4;
+	uint32_t sideband5;
+	uint32_t sideband6;
+	uint32_t sideband7;
+	uint32_t sideband8;
+	uint32_t sideband9;
+	uint32_t sideband10;
+	uint32_t sideband11;
+	uint32_t sideband12;
+	uint32_t sideband13;
+	uint32_t sideband14;
+	uint32_t sideband15;
+	uint32_t dramsts;
+	uint32_t dbgdone;
+	uint32_t dbgsignals;
+	uint32_t dbgreset;
+	uint32_t dbgmatch;
+	uint32_t counter0mask;
+	uint32_t counter1mask;
+	uint32_t counter0match;
+	uint32_t counter1match;
+	uint32_t niosreserve0;
+	uint32_t niosreserve1;
+	uint32_t niosreserve2;
+};
+
+union dramaddrw_reg {
+	struct {
+		u32 cfg_col_addr_width:5;
+		u32 cfg_row_addr_width:5;
+		u32 cfg_bank_addr_width:4;
+		u32 cfg_bank_group_addr_width:2;
+		u32 cfg_cs_addr_width:3;
+		u32 reserved:13;
+	};
+	u32 word;
+};
+
+union ctrlcfg0_reg {
+	struct {
+		u32 cfg_mem_type:4;
+		u32 cfg_dimm_type:3;
+		u32 cfg_ac_pos:2;
+		u32 cfg_ctrl_burst_len:5;
+		u32 reserved:18;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union ctrlcfg1_reg {
+	struct {
+		u32 cfg_dbc3_burst_len:5;
+		u32 cfg_addr_order:2;
+		u32 cfg_ctrl_enable_ecc:1;
+		u32 reserved:24;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union dramtiming0_reg {
+	struct {
+		u32 cfg_tcl:6;
+		u32 reserved:8;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming0_reg {
+	struct {
+		u32 cfg_act_to_rdwr:6;
+		u32 cfg_act_to_pch:6;
+		u32 cfg_act_to_act:6;
+		u32 cfg_act_to_act_db:6;
+		u32 reserved:8;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming1_reg {
+	struct {
+		u32 cfg_rd_to_rd:6;
+		u32 cfg_rd_to_rd_dc:6;
+		u32 cfg_rd_to_rd_db:6;
+		u32 cfg_rd_to_wr:6;
+		u32 cfg_rd_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming2_reg {
+	struct {
+		u32 cfg_rd_to_wr_db:6;
+		u32 cfg_rd_to_pch:6;
+		u32 cfg_rd_ap_to_valid:6;
+		u32 cfg_wr_to_wr:6;
+		u32 cfg_wr_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming3_reg {
+	struct {
+		u32 cfg_wr_to_wr_db:6;
+		u32 cfg_wr_to_rd:6;
+		u32 cfg_wr_to_rd_dc:6;
+		u32 cfg_wr_to_rd_db:6;
+		u32 cfg_wr_to_pch:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming4_reg {
+	struct {
+		u32 cfg_wr_ap_to_valid:6;
+		u32 cfg_pch_to_valid:6;
+		u32 cfg_pch_all_to_valid:6;
+		u32 cfg_arf_to_valid:8;
+		u32 cfg_pdn_to_valid:6;
+	};
+	u32 word;
+};
+
+union caltiming9_reg {
+	struct {
+		u32 cfg_4_act_to_act:8;
+		u32 reserved:24;
+	};
+	u32 word;
+};
+
+#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET	0
+#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET	6
+#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET	12
+#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET	18
+#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET	21
+#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET	26
+#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET	31
+#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET	1
+#define DDR_SCHED_ACTIVATE_RRD_OFFSET		0
+#define DDR_SCHED_ACTIVATE_FAW_OFFSET		4
+#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET	10
+#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET	0
+#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET	2
+#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET	4
+#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
+#define DDR_HMC_DDRCALSTAT_CAL_MSK		0x00000001
+#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	0x00010000
+#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		0x00000100
+#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		0x00000001
+#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		0x00000100
+#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		0x00000001
+#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
+#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
+#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		0x8
+#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
+
+#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR	0xf7004400
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR	0xf70045c0
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR	0xf70045e0
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR	0xf7004600
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR	0xf7004620
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR	0xf7004640
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR	0xf7004660
+
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR	0xf7018560
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR	0xf7018580
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR	0xf70185a0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR	0xf70185c0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR	0xf70185e0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR	0xf7018600
+
+#define CCU_ADBASE_DI_MASK			0x00000010
+
+#endif /* _SDRAM_S10_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index bdd2872..943b6cd 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
 endif
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
new file mode 100644
index 0000000..c488caf
--- /dev/null
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -0,0 +1,382 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include <asm/arch/sdram_s10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+		(void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+static const struct socfpga_system_manager *sysmgr_regs =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+#define DDR_CONFIG(A, B, C, R)	((A<<24)|(B<<16)|(C<<8)|R)
+
+/* The followring are the supported configurations */
+u32 ddr_config[] = {
+	/* DDR_CONFIG(Address order,Bank,Column,Row) */
+	/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
+	DDR_CONFIG(0, 3, 10, 12),
+	DDR_CONFIG(0, 3,  9, 13),
+	DDR_CONFIG(0, 3, 10, 13),
+	DDR_CONFIG(0, 3,  9, 14),
+	DDR_CONFIG(0, 3, 10, 14),
+	DDR_CONFIG(0, 3, 10, 15),
+	DDR_CONFIG(0, 3, 11, 14),
+	DDR_CONFIG(0, 3, 11, 15),
+	DDR_CONFIG(0, 3, 10, 16),
+	DDR_CONFIG(0, 3, 11, 16),
+	DDR_CONFIG(0, 3, 12, 15),	/* 0xa */
+	/* List for DDR4 only (pinout order > chip, bank, row, column) */
+	DDR_CONFIG(1, 3, 10, 14),
+	DDR_CONFIG(1, 4, 10, 14),
+	DDR_CONFIG(1, 3, 10, 15),
+	DDR_CONFIG(1, 4, 10, 15),
+	DDR_CONFIG(1, 3, 10, 16),
+	DDR_CONFIG(1, 4, 10, 16),
+	DDR_CONFIG(1, 3, 10, 17),
+	DDR_CONFIG(1, 4, 10, 17),
+};
+
+#define DDR_CONFIG_ELEMENTS	(sizeof(ddr_config)/sizeof(u32))
+
+int match_ddr_conf(u32 ddr_conf)
+{
+	int i;
+	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+		if (ddr_conf == ddr_config[i])
+			return i;
+	}
+	return 0;
+}
+
+static int emif_clear(void)
+{
+	u32 s2c, i;
+
+	writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl);
+	s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+	      DDR_HMC_RSTHANDSHAKE_MASK;
+
+	for (i = 1000; (i > 0) && s2c; i--) {
+		WATCHDOG_RESET();
+		mdelay(1);
+		s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+		      DDR_HMC_RSTHANDSHAKE_MASK;
+	}
+	return !s2c;
+}
+
+static int emif_reset(void)
+{
+	u32 c2s, s2c, i;
+
+	c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) &
+	      DDR_HMC_RSTHANDSHAKE_MASK;
+	s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+	      DDR_HMC_RSTHANDSHAKE_MASK;
+
+	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+	      c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0),
+	      readl(&socfpga_io48_mmr_base->niosreserve1),
+	      readl(&socfpga_io48_mmr_base->niosreserve2),
+	      readl(&socfpga_io48_mmr_base->dramsts));
+
+	if (s2c && emif_clear()) {
+		printf("DDR: emif_clear() failed\n");
+		return -1;
+	}
+
+	puts("DDR: Triggerring emif_reset\n");
+	writel(DDR_HMC_CORE2SEQ_INT_REQ,
+	       &socfpga_ecc_hmc_base->rsthandshakectrl);
+
+	for (i = 1000; i > 0; i--) {
+		/* if seq2core[3] = 0, we are good */
+		if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
+		    DDR_HMC_SEQ2CORE_INT_RESP_MASK))
+			break;
+		WATCHDOG_RESET();
+		mdelay(1);
+	}
+
+	if (!i) {
+		printf("DDR: failed to get ack from EMIF\n");
+		return -2;
+	}
+
+	if (emif_clear()) {
+		printf("DDR: emif_clear() failed\n");
+		return -3;
+	}
+
+	printf("DDR: emif_reset triggered successly\n");
+	return 0;
+}
+
+static int poll_hmc_clock_status(void)
+{
+	u32 status, i;
+
+	for (i = 1000; i > 0; i--) {
+		status = readl(&sysmgr_regs->hmc_clk) &
+			 SYSMGR_HMC_CLK_STATUS_MSK;
+		udelay(1);
+		if (status)
+			break;
+		WATCHDOG_RESET();
+	}
+	return status;
+}
+
+/**
+ * sdram_mmr_init_full() - Function to initialize SDRAM MMR
+ *
+ * Initialize the SDRAM MMR.
+ */
+int sdram_mmr_init_full(unsigned int unused)
+{
+	u32 update_value, io48_value, ddrioctl;
+	u32 i, j, cal_success;
+
+	/* Enable access to DDR from CPU master */
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);
+
+	/* Enable access to DDR from IO master */
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);
+
+	/* this enables nonsecure access to DDR */
+	/* mpuregion0addr_limit */
+	writel(0xFFFF0000, 0xF8020118);
+	writel(0x1F, 0xF802011c);
+
+	/* nonmpuregion0addr_limit */
+	writel(0xFFFF0000, 0xF8020198);
+	writel(0x1F, 0xF802019C);
+
+	/* Enable mpuregion0enable and nonmpuregion0enable */
+	writel(BIT(0) | BIT(8), 0xF8020100);
+
+	/* Ensure HMC clock is running */
+	if (!poll_hmc_clock_status()) {
+		puts("DDR: Error as HMC clock not running\n");
+		return -1;
+	}
+
+	/* release DDR scheduler from reset */
+	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
+
+	/* Try 3 times to do a calibration */
+	for (i = 0; i < 3; i++) {
+		cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) &
+			      DDR_HMC_DDRCALSTAT_CAL_MSK;
+		/* A delay to wait for calibration bit to set */
+		for (j = 0; (j < 1000) && !cal_success; j++) {
+			WATCHDOG_RESET();
+			mdelay(1);
+			cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat)
+				      & DDR_HMC_DDRCALSTAT_CAL_MSK;
+		}
+
+		if (cal_success)
+			break;
+		else
+			emif_reset();
+	}
+
+	if (!cal_success) {
+		puts("DDR: Error as SDRAM calibration failed\n");
+		return -1;
+	}
+	puts("DDR: Calibration success\n");
+
+	union ctrlcfg0_reg ctrlcfg0 = (union ctrlcfg0_reg)
+				readl(&socfpga_io48_mmr_base->ctrlcfg0);
+	union ctrlcfg1_reg ctrlcfg1 = (union ctrlcfg1_reg)
+				readl(&socfpga_io48_mmr_base->ctrlcfg1);
+	union dramaddrw_reg dramaddrw = (union dramaddrw_reg)
+				readl(&socfpga_io48_mmr_base->dramaddrw);
+	union dramtiming0_reg dramtim0 = (union dramtiming0_reg)
+				readl(&socfpga_io48_mmr_base->dramtiming0);
+	union caltiming0_reg caltim0 = (union caltiming0_reg)
+				readl(&socfpga_io48_mmr_base->caltiming0);
+	union caltiming1_reg caltim1 = (union caltiming1_reg)
+				readl(&socfpga_io48_mmr_base->caltiming1);
+	union caltiming2_reg caltim2 = (union caltiming2_reg)
+				readl(&socfpga_io48_mmr_base->caltiming2);
+	union caltiming3_reg caltim3 = (union caltiming3_reg)
+				readl(&socfpga_io48_mmr_base->caltiming3);
+	union caltiming4_reg caltim4 = (union caltiming4_reg)
+				readl(&socfpga_io48_mmr_base->caltiming4);
+	union caltiming9_reg caltim9 = (union caltiming9_reg)
+				readl(&socfpga_io48_mmr_base->caltiming9);
+
+	/*
+	 * Configure the DDR IO size [0xFFCFB008]
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+	writel(((update_value & 0xFF) >> 5), &socfpga_ecc_hmc_base->ddrioctrl);
+	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+	/* enable HPS interface to HMC */
+	writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK,
+	       &socfpga_ecc_hmc_base->hpsintfcsel);
+
+	/* Set the DDR Configuration */
+	io48_value = DDR_CONFIG(ctrlcfg1.cfg_addr_order,
+				(dramaddrw.cfg_bank_addr_width +
+				 dramaddrw.cfg_bank_group_addr_width),
+				dramaddrw.cfg_col_addr_width,
+				dramaddrw.cfg_row_addr_width);
+
+	update_value = match_ddr_conf(io48_value);
+	if (update_value)
+		writel(update_value,
+		       &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrconf);
+
+	/* Configure HMC dramaddrw */
+	writel(readl(&socfpga_io48_mmr_base->dramaddrw),
+	       &socfpga_ecc_hmc_base->dramaddrwidth);
+
+	/*
+	 * Configure DDR timing
+	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
+	 *  WRTOMISS = WL + tWR + tRP + tRCD and
+	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
+	 *  First part of equation is in memory clock units so divide by 2
+	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+	 */
+	update_value = caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid +
+		       caltim0.cfg_act_to_rdwr -
+		       (ctrlcfg0.cfg_ctrl_burst_len >> 2);
+	io48_value = (((dramtim0.cfg_tcl + 2 + DDR_TWR +
+		      (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -
+		      /* Up to here was in memory cycles so divide by 2 */
+		      caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +
+		      caltim4.cfg_pch_to_valid);
+
+	writel(((caltim0.cfg_act_to_act << DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET) |
+		(update_value << DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET) |
+		(io48_value << DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET) |
+		((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<
+			DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET) |
+		(caltim1.cfg_rd_to_wr << DDR_SCHED_DDRTIMING_RDTOWR_OFFSET) |
+		(caltim3.cfg_wr_to_rd << DDR_SCHED_DDRTIMING_WRTORD_OFFSET) |
+		(((ddrioctl == 1) ? 1 : 0) <<
+			DDR_SCHED_DDRTIMING_BWRATIO_OFFSET)),
+		&socfpga_noc_ddr_scheduler_base->main_scheduler_ddrtiming);
+
+	/* Configure DDR mode [precharge = 0] */
+	writel(((ddrioctl ? 0 : 1) << DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET),
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrmode);
+
+	/* Configure the read latency */
+	writel((dramtim0.cfg_tcl >> 1) + DDR_READ_LATENCY_DELAY,
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_readlatency);
+
+	/*
+	 * Configuring timing values concerning activate commands
+	 * [FAWBANK alway 1 because always 4 bank DDR]
+	 */
+	writel(((caltim0.cfg_act_to_act_db << DDR_SCHED_ACTIVATE_RRD_OFFSET) |
+	       (caltim9.cfg_4_act_to_act << DDR_SCHED_ACTIVATE_FAW_OFFSET) |
+	       (DDR_ACTIVATE_FAWBANK << DDR_SCHED_ACTIVATE_FAWBANK_OFFSET)),
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_activate);
+
+	/*
+	 * Configuring timing values concerning device to device data bus
+	 * ownership change
+	 */
+	writel(((caltim1.cfg_rd_to_rd_dc <<
+			DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET) |
+	       (caltim1.cfg_rd_to_wr_dc <<
+			DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET) |
+	       (caltim3.cfg_wr_to_rd_dc <<
+			DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET)),
+	       &socfpga_noc_ddr_scheduler_base->main_scheduler_devtodev);
+
+	/* Enable or disable the SDRAM ECC */
+	if (ctrlcfg1.cfg_ctrl_enable_ecc) {
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+	} else {
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+	}
+
+	puts("DDR: HMC init success\n");
+	return 0;
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+unsigned long sdram_calculate_size(void)
+{
+	union dramaddrw_reg dramaddrw =
+		(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);
+
+	u32 size = (1 << (dramaddrw.cfg_cs_addr_width +
+		    dramaddrw.cfg_bank_group_addr_width +
+		    dramaddrw.cfg_bank_addr_width +
+		    dramaddrw.cfg_row_addr_width +
+		    dramaddrw.cfg_col_addr_width));
+
+	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+		       DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+
+	return size;
+}
-- 
2.2.2

[U-Boot] [PATCH v2 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add socdk board support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 board/altera/stratix10-socdk/MAINTAINERS | 7 +++++++
 board/altera/stratix10-socdk/Makefile    | 7 +++++++
 board/altera/stratix10-socdk/socfpga.c   | 7 +++++++
 3 files changed, 21 insertions(+)
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 0000000..6192bc9
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:	Chin-Liang See <chin.liang.see@intel.com>
+M:	Dinh Nguyen <dinh.nguyen@intel.com>
+S:	Maintained
+F:	board/altera/stratix10-socdk/
+F:	include/configs/socfpga_stratix10_socdk.h
+F:	configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 0000000..02a9cad
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 0000000..3deb989
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
-- 
2.2.2

[U-Boot] [PATCH v2 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

[chin.liang.see at intel.com]

From: Chin Liang See <chin.liang.see@intel.com>

Add build support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/Kconfig                          |   8 +-
 arch/arm/mach-socfpga/Kconfig             |  13 ++
 configs/socfpga_stratix10_defconfig       |  39 ++++++
 include/configs/socfpga_stratix10_socdk.h | 216 ++++++++++++++++++++++++++++++
 4 files changed, 273 insertions(+), 3 deletions(-)
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d6d9558..4a6b9da 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -656,21 +656,23 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
-	select CPU_V7
+	select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select ARM64 if TARGET_SOCFPGA_STRATIX10
 	select SUPPORT_SPL
 	select OF_CONTROL
 	select SPL_OF_CONTROL
 	select DM
 	select DM_SPI_FLASH
 	select DM_SPI
-	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT
 	select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
-	select SYS_THUMB_BUILD
+	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
 	imply FAT_WRITE
+	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..03ab956 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5
 	bool
 	select ALTERA_SDRAM
 
+config TARGET_SOCFPGA_STRATIX10
+	bool
+	select ARMV8_MULTIENTRY
+	select ARMV8_SPIN_TABLE
+	select ARMV8_SET_SMPEN
+
 choice
 	prompt "Altera SOCFPGA board select"
 	optional
@@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+	bool "Intel SOCFPGA SoCDK (Stratix 10)"
+	select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -116,12 +126,14 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -145,6 +157,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
new file mode 100644
index 0000000..e5a7a69
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MMC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CADENCE_QSPI=y
+CONFIG_DM_ETH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 0000000..0d955f8
--- /dev/null
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
+#define __CONFIG_SOCFGPA_STRATIX10_H__
+
+#include <asm/arch/base_addr_s10.h>
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_TEXT_BASE		0x1000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR			0x80000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+#define CPU_RELEASE_ADDR		0x80
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE		/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING		/* Command history etc */
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+/*
+ * U-Boot run time memory configurations
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x40000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR \
+					+ CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_SP_ADDR)
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/*
+ * U-Boot display configurations
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
+#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
+
+/*
+ * QSPI support
+ */
+ #ifdef CONFIG_CADENCE_QSPI
+/* Enable it if you want to use dual-stacked mode */
+#undef CONFIG_SF_DUAL_FLASH
+/*#define CONFIG_QSPI_RBF_ADDR		0x720000*/
+
+/* Flash device info */
+#define CONFIG_SF_DEFAULT_SPEED		(50000000)
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_3 | SPI_RX_QUAD)
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+
+/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		0x710000
+#define CONFIG_ENV_SIZE			(4 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(4 * 1024)
+#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
+
+/*#define CONFIG_BOOT_FLASH_TYPE		"qspi"*/
+#define CONFIG_CQSPI_DECODER		0
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
+#endif /* CONFIG_SPL_BUILD */
+
+/* 533MHz, TODO: Get from SDM */
+#define CONFIG_CQSPI_REF_CLK		400000000
+
+#endif /* CONFIG_CADENCE_QSPI */
+
+/*
+ * Boot arguments passed to the boot command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "earlycon"
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bootfile=Image\0" \
+	"fdt_addr=8000000\0" \
+	"fdtimage=socfpga_stratix10_socdk.dtb\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"booti ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0"
+
+/*
+ * Generic Interrupt Controller Definitions
+ */
+#define CONFIG_GICV2
+
+/*
+ * External memory configurations
+ */
+#define PHYS_SDRAM_1			0x0
+#define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE - 0x200000
+
+/*
+ * SDRAM controller
+ */
+#define CONFIG_ALTERA_SDRAM
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550_CLK		100000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+/* always write in 32 bit manner */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+
+/*
+ * Timer & watchdog configurations
+ */
+#define COUNTER_FREQUENCY		400000000
+
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
+#endif
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
+#define CONFIG_PHY_GIGE
+#endif /* CONFIG_CMD_NET */
+
+
+/*
+ * SPL memory layout
+ *
+ * On chip RAM
+ * 0xFFE0_0000 ...... Start of OCRAM
+ * SPL code, rwdata
+ * 0xFFEx_xxxx ...... Top of stack (grows down)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
+ * 0xFFE3_FFFF ...... End of OCRAM
+ *
+ * SDRAM
+ * 0x0000_0000 ...... Start of SDRAM_1
+ * unused / empty space for image loading
+ * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
+ * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
+ * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
+ *
+ */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SPL_BSS_START_ADDR	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
+					- CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR \
+					- CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS      0x400000
+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
+
+#endif	/* __CONFIG_H */
-- 
2.2.2

[U-Boot] [PATCH v2 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add the base address map for Statix10 SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 ++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> new file mode 100644
> index 0000000..2fdc917
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS          0xf8000400
> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS           0xf8010000
> +#define SOCFPGA_SDR_ADDRESS                    0xf8011000
> +#define SOCFPGA_SMMU_ADDRESS                   0xfa000000
> +#define SOCFPGA_MAILBOX_ADDRESS                        0xffA30000
> +#define SOCFPGA_USB0_ADDRESS                   0xffb00000
> +#define SOCFPGA_USB1_ADDRESS                   0xffb40000

USB address is obtainable from DT.

> +#define SOCFPGA_NANDREGS_ADDRESS               0xffb80000
> +#define SOCFPGA_NANDDATA_ADDRESS               0xffb90000
> +#define SOCFPGA_UART0_ADDRESS                  0xffc02000
> +#define SOCFPGA_UART1_ADDRESS                  0xffc02100
> +#define SOCFPGA_I2C0_ADDRESS                   0xffc02800
> +#define SOCFPGA_I2C1_ADDRESS                   0xffc02900
> +#define SOCFPGA_I2C2_ADDRESS                   0xffc02a00
> +#define SOCFPGA_I2C3_ADDRESS                   0xffc02b00
> +#define SOCFPGA_I2C4_ADDRESS                   0xffc02c00

I2C is also obtainabled

Please check the other peripherals.

Dinh

[U-Boot] [PATCH v2 02/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add Clock Manager driver support for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> --
> Changes in v2
> - Declared defines for constant value used
> - Fixed spacing and comments
> ---
>  arch/arm/mach-socfpga/Makefile                     |   4 +
>  arch/arm/mach-socfpga/clock_manager.c              |   4 +-
>  arch/arm/mach-socfpga/clock_manager_s10.c          | 355 +++++++++++++++++++++
>  arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
>  .../mach-socfpga/include/mach/clock_manager_s10.h  | 210 ++++++++++++
>  arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
>  arch/arm/mach-socfpga/wrap_pll_config_s10.c        |  44 +++
>  7 files changed, 646 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
>  create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>  create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
>  create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 286bfef..e5f9dd7 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -30,6 +30,10 @@ obj-y        += pinmux_arria10.o
>  obj-y  += reset_manager_arria10.o
>  endif
>
> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> +obj-y  += clock_manager_s10.o
> +obj-y  += wrap_pll_config_s10.o
> +endif
>  ifdef CONFIG_SPL_BUILD
>  obj-y  += spl.o
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
> index cb6ae03..f9450a4 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
>         do {
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>                 inter_val = readl(&clock_manager_base->inter) & mask;
> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#else
>                 inter_val = readl(&clock_manager_base->stat) & mask;
>  #endif
>                 /* Wait for stable lock */
> @@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
>
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>         gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#else
>         gd->bd->bi_ddr_freq = 0;
>  #endif
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> new file mode 100644
> index 0000000..cfb6708
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -0,0 +1,355 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/arch/handoff_s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_clock_manager *clock_manager_base =
> +       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void cm_write_bypass_mainpll(uint32_t val)
> +{
> +       writel(val, &clock_manager_base->main_pll.bypass);
> +       cm_wait_for_fsm();
> +}
> +
> +static void cm_write_bypass_perpll(uint32_t val)
> +{
> +       writel(val, &clock_manager_base->per_pll.bypass);
> +       cm_wait_for_fsm();
> +}
> +
> +/* function to write the ctrl register which requires a poll of the busy bit */
> +static void cm_write_ctrl(uint32_t val)
> +{
> +       writel(val, &clock_manager_base->ctrl);
> +       cm_wait_for_fsm();
> +}
> +
> +/*
> + * Setup clocks while making no assumptions about previous state of the clocks.
> + */
> +void cm_basic_init(const struct cm_config * const cfg)
> +{
> +       uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;
> +
> +       if (cfg == 0)
> +               return;
> +
> +       /* Put all plls in bypass */
> +       cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
> +       cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
> +
> +       /* setup main PLL dividers where calculate the vcocalib value */
> +       mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> +               CLKMGR_FDBCK_MDIV_MASK;
> +       refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> +                    CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> +       mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
> +       hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
> +               CLKMGR_HSCNT_CONST;
> +       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> +                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> +                  CLKMGR_VCOCALIB_MSCNT_OFFSET);
> +
> +       writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> +               ~CLKMGR_PLLGLOB_RST_MASK),
> +               &clock_manager_base->main_pll.pllglob);
> +       writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
> +       writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
> +       writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
> +       writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
> +       writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
> +
> +       /* setup peripheral PLL dividers */
> +       /* calculate the vcocalib value */
> +       mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> +               CLKMGR_FDBCK_MDIV_MASK;
> +       refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> +                    CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> +       mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
> +       hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
> +               CLKMGR_HSCNT_CONST;
> +       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> +                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> +                  CLKMGR_VCOCALIB_MSCNT_OFFSET);
> +
> +       writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> +               ~CLKMGR_PLLGLOB_RST_MASK),
> +               &clock_manager_base->per_pll.pllglob);
> +       writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
> +       writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
> +       writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
> +       writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
> +       writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
> +       writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
> +
> +       /* Take both PLL out of reset and power up */
> +       setbits_le32(&clock_manager_base->main_pll.pllglob,
> +                    CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> +       setbits_le32(&clock_manager_base->per_pll.pllglob,
> +                    CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> +
> +#define LOCKED_MASK \
> +       (CLKMGR_STAT_MAINPLL_LOCKED | \
> +       CLKMGR_STAT_PERPLL_LOCKED)
> +
> +       cm_wait_for_lock(LOCKED_MASK);
> +
> +       /*
> +        * Dividers for C2 to C9 only init after PLLs are lock. As dividers
> +        * only take effect upon value change, we shall set a maximum value as
> +        * default value.
> +        */
> +       writel(0xff, &clock_manager_base->main_pll.mpuclk);
> +       writel(0xff, &clock_manager_base->main_pll.nocclk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr2clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr3clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr4clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr5clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr6clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr7clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr8clk);
> +       writel(0xff, &clock_manager_base->main_pll.cntr9clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr2clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr3clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr4clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr5clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr6clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr7clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr8clk);
> +       writel(0xff, &clock_manager_base->per_pll.cntr9clk);
> +
> +       writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
> +       writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
> +       writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
> +       writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
> +       writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
> +       writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
> +       writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
> +       writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
> +       writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
> +       writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
> +       writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
> +       writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
> +       writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
> +       writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
> +       writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
> +       writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
> +       writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
> +       writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
> +
> +       /* Take all PLLs out of bypass */
> +       cm_write_bypass_mainpll(0);
> +       cm_write_bypass_perpll(0);
> +
> +       /* clear safe mode / out of boot mode */
> +       cm_write_ctrl(readl(&clock_manager_base->ctrl)
> +                       & ~(CLKMGR_CTRL_SAFEMODE));
> +
> +       /* Now ungate non-hw-managed clocks */
> +       writel(~0, &clock_manager_base->main_pll.en);
> +       writel(~0, &clock_manager_base->per_pll.en);
> +
> +       /* Clear the loss of lock bits (write 1 to clear) */
> +       writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
> +              &clock_manager_base->intrclr);
> +}
> +
> +static unsigned long cm_get_main_vco_clk_hz(void)
> +{
> +        unsigned long fref, refdiv, mdiv, reg, vco;
> +
> +       reg = readl(&clock_manager_base->main_pll.pllglob);
> +
> +       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> +               CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> +       switch (fref) {
> +       case CLKMGR_VCO_PSRC_EOSC1:
> +               fref = cm_get_osc_clk_hz(0);
> +               break;
> +       case CLKMGR_VCO_PSRC_INTOSC:
> +               fref = cm_get_intosc_clk_hz();
> +               break;
> +       case CLKMGR_VCO_PSRC_F2S:
> +               fref = cm_get_fpga_clk_hz();
> +               break;
> +       }
> +
> +       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> +                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> +
> +       reg = readl(&clock_manager_base->main_pll.fdbck);
> +       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> +
> +       vco = fref / refdiv;
> +       vco = vco * (CLKMGR_MDIV_CONST + mdiv);
> +       return vco;
> +}
> +
> +static unsigned long cm_get_per_vco_clk_hz(void)
> +{
> +       unsigned long fref, refdiv, mdiv, reg, vco;
> +
> +       reg = readl(&clock_manager_base->per_pll.pllglob);
> +
> +       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> +               CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> +       switch (fref) {
> +       case CLKMGR_VCO_PSRC_EOSC1:
> +               fref = cm_get_osc_clk_hz(0);
> +               break;
> +       case CLKMGR_VCO_PSRC_INTOSC:
> +               fref = cm_get_intosc_clk_hz();
> +               break;
> +       case CLKMGR_VCO_PSRC_F2S:
> +               fref = cm_get_fpga_clk_hz();
> +               break;
> +       }
> +
> +       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> +                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> +
> +       reg = readl(&clock_manager_base->per_pll.fdbck);
> +       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> +
> +       vco = fref / refdiv;
> +       vco = vco * (CLKMGR_MDIV_CONST + mdiv);
> +       return vco;
> +}
> +
> +unsigned long cm_get_mpu_clk_hz(void)
> +{
> +       unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
> +       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> +
> +       switch (clock) {
> +       case CLKMGR_CLKSRC_MAIN:
> +               clock = cm_get_main_vco_clk_hz();
> +               clock /= (readl(&clock_manager_base->main_pll.pllc0) &
> +                         CLKMGR_PLLC0_DIV_MASK);
> +               break;
> +
> +       case CLKMGR_CLKSRC_PER:
> +               clock = cm_get_per_vco_clk_hz();
> +               clock /= (readl(&clock_manager_base->per_pll.pllc0) &
> +                         CLKMGR_CLKCNT_MSK);
> +               break;
> +
> +       case CLKMGR_CLKSRC_OSC1:
> +               clock = cm_get_osc_clk_hz(0);
> +               break;
> +
> +       case CLKMGR_CLKSRC_INTOSC:
> +               clock = cm_get_intosc_clk_hz();
> +               break;
> +
> +       case CLKMGR_CLKSRC_FPGA:
> +               clock = cm_get_fpga_clk_hz();
> +               break;
> +       }
> +
> +       clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
> +               CLKMGR_CLKCNT_MSK);
> +       return clock;
> +}
> +
> +unsigned int cm_get_l3_main_clk_hz(void)
> +{
> +       uint32_t clock = readl(&clock_manager_base->main_pll.nocclk);
> +       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> +
> +       switch (clock) {
> +       case CLKMGR_CLKSRC_MAIN:
> +               clock = cm_get_main_vco_clk_hz();
> +               clock /= (readl(&clock_manager_base->main_pll.pllc1) &
> +                         CLKMGR_PLLC0_DIV_MASK);
> +               break;
> +
> +       case CLKMGR_CLKSRC_PER:
> +               clock = cm_get_per_vco_clk_hz();
> +               clock /= (readl(&clock_manager_base->per_pll.pllc1) &
> +                         CLKMGR_CLKCNT_MSK);
> +               break;
> +
> +       case CLKMGR_CLKSRC_OSC1:
> +               clock = cm_get_osc_clk_hz(0);
> +               break;
> +
> +       case CLKMGR_CLKSRC_INTOSC:
> +               clock = cm_get_intosc_clk_hz();
> +               break;
> +
> +       case CLKMGR_CLKSRC_FPGA:
> +               clock = cm_get_fpga_clk_hz();
> +               break;
> +       }
> +
> +       clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
> +               CLKMGR_CLKCNT_MSK);
> +       return clock;
> +}
> +
> +unsigned int cm_get_mmc_controller_clk_hz(void)
> +{
> +       uint32_t clock = readl(&clock_manager_base->per_pll.cntr6clk);
> +       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> +
> +       switch (clock) {
> +       case CLKMGR_CLKSRC_MAIN:
> +               clock = cm_get_l3_main_clk_hz();
> +               clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
> +                       CLKMGR_CLKCNT_MSK);
> +               break;
> +
> +       case CLKMGR_CLKSRC_PER:
> +               clock = cm_get_l3_main_clk_hz();
> +               clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
> +                       CLKMGR_CLKCNT_MSK);
> +               break;
> +
> +       case CLKMGR_CLKSRC_OSC1:
> +               clock = cm_get_osc_clk_hz(0);
> +               break;
> +
> +       case CLKMGR_CLKSRC_INTOSC:
> +               clock = cm_get_intosc_clk_hz();
> +               break;
> +
> +       case CLKMGR_CLKSRC_FPGA:
> +               clock = cm_get_fpga_clk_hz();
> +               break;
> +       }
> +       return clock / 4;
> +}
> +
> +unsigned int cm_get_l4_sp_clk_hz(void)
> +{
> +       uint32_t clock = cm_get_l3_main_clk_hz();
> +
> +       clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
> +                 CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
> +       return clock;
> +}
> +
> +void cm_print_clock_quick_summary(void)
> +{
> +       printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
> +       printf("L3 main     %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
> +       printf("Main VCO    %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
> +       printf("Per VCO     %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
> +       printf("EOSC1       %d kHz\n", cm_get_osc_clk_hz(0) / 1000);
> +       printf("HPS MMC     %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
> +       printf("UART        %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
> +}
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 4c6b1f8..ddf814f 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);
>  #include <asm/arch/clock_manager_gen5.h>
>  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>  #include <asm/arch/clock_manager_arria10.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> +#include <asm/arch/clock_manager_s10.h>
>  #endif
>
>  #endif /* _CLOCK_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> new file mode 100644
> index 0000000..831cf2c
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -0,0 +1,210 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#ifndef        _CLOCK_MANAGER_S10_
> +#define        _CLOCK_MANAGER_S10_
> +
> +/* Clock speed accessors */
> +unsigned long cm_get_mpu_clk_hz(void);
> +unsigned long cm_get_sdram_clk_hz(void);
> +unsigned int cm_get_l4_sp_clk_hz(void);
> +unsigned int cm_get_mmc_controller_clk_hz(void);
> +unsigned int cm_get_qspi_controller_clk_hz(void);
> +unsigned int cm_get_spi_controller_clk_hz(void);
> +const unsigned int cm_get_osc_clk_hz(const int osc);
> +const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> +const unsigned int cm_get_intosc_clk_hz(void);
> +const unsigned int cm_get_fpga_clk_hz(void);
> +
> +#define CLKMGR_EOSC1_HZ                25000000
> +#define CLKMGR_INTOSC_HZ       460000000
> +#define CLKMGR_FPGA_CLK_HZ     50000000
> +
> +/* Clock configuration accessors */
> +const struct cm_config * const cm_get_default_config(void);
> +
> +struct cm_config {
> +       /* main group */
> +       uint32_t main_pll_mpuclk;
> +       uint32_t main_pll_nocclk;
> +       uint32_t main_pll_cntr2clk;
> +       uint32_t main_pll_cntr3clk;
> +       uint32_t main_pll_cntr4clk;
> +       uint32_t main_pll_cntr5clk;
> +       uint32_t main_pll_cntr6clk;
> +       uint32_t main_pll_cntr7clk;
> +       uint32_t main_pll_cntr8clk;
> +       uint32_t main_pll_cntr9clk;
> +       uint32_t main_pll_nocdiv;
> +       uint32_t main_pll_pllglob;
> +       uint32_t main_pll_fdbck;
> +       uint32_t main_pll_pllc0;
> +       uint32_t main_pll_pllc1;
> +       uint32_t spare;
> +
> +       /* peripheral group */
> +       uint32_t per_pll_cntr2clk;
> +       uint32_t per_pll_cntr3clk;
> +       uint32_t per_pll_cntr4clk;
> +       uint32_t per_pll_cntr5clk;
> +       uint32_t per_pll_cntr6clk;
> +       uint32_t per_pll_cntr7clk;
> +       uint32_t per_pll_cntr8clk;
> +       uint32_t per_pll_cntr9clk;
> +       uint32_t per_pll_emacctl;
> +       uint32_t per_pll_gpiodiv;
> +       uint32_t per_pll_pllglob;
> +       uint32_t per_pll_fdbck;
> +       uint32_t per_pll_pllc0;
> +       uint32_t per_pll_pllc1;
> +
> +       /* incoming clock */
> +       uint32_t hps_osc_clk_hz;
> +       uint32_t fpga_clk_hz;
> +};
> +
> +void cm_basic_init(const struct cm_config * const cfg);
> +
> +struct socfpga_clock_manager_main_pll {
> +       u32     en;
> +       u32     ens;
> +       u32     enr;
> +       u32     bypass;
> +       u32     bypasss;
> +       u32     bypassr;
> +       u32     mpuclk;
> +       u32     nocclk;
> +       u32     cntr2clk;
> +       u32     cntr3clk;
> +       u32     cntr4clk;
> +       u32     cntr5clk;
> +       u32     cntr6clk;
> +       u32     cntr7clk;
> +       u32     cntr8clk;
> +       u32     cntr9clk;
> +       u32     nocdiv;
> +       u32     pllglob;
> +       u32     fdbck;
> +       u32     mem;
> +       u32     memstat;
> +       u32     pllc0;
> +       u32     pllc1;
> +       u32     vcocalib;
> +       u32     _pad_0x90_0xA0[5];
> +};
> +
> +struct socfpga_clock_manager_per_pll {
> +       u32     en;
> +       u32     ens;
> +       u32     enr;
> +       u32     bypass;
> +       u32     bypasss;
> +       u32     bypassr;
> +       u32     cntr2clk;
> +       u32     cntr3clk;
> +       u32     cntr4clk;
> +       u32     cntr5clk;
> +       u32     cntr6clk;
> +       u32     cntr7clk;
> +       u32     cntr8clk;
> +       u32     cntr9clk;
> +       u32     emacctl;
> +       u32     gpiodiv;
> +       u32     pllglob;
> +       u32     fdbck;
> +       u32     mem;
> +       u32     memstat;
> +       u32     pllc0;
> +       u32     pllc1;
> +       u32     vcocalib;
> +       u32     _pad_0x100_0x124[10];
> +};
> +
> +struct socfpga_clock_manager {
> +       u32     ctrl;
> +       u32     stat;
> +       u32     testioctrl;
> +       u32     intrgen;
> +       u32     intrmsk;
> +       u32     intrclr;
> +       u32     intrsts;
> +       u32     intrstk;
> +       u32     intrraw;
> +       u32     _pad_0x24_0x2c[3];
> +       struct socfpga_clock_manager_main_pll main_pll;
> +       struct socfpga_clock_manager_per_pll per_pll;
> +};
> +
> +#define CLKMGR_CTRL_SAFEMODE                           (1 << 0)
> +#define CLKMGR_BYPASS_MAINPLL_ALL                      0x00000007
> +#define CLKMGR_BYPASS_PERPLL_ALL                       0x0000007f
> +
> +#define CLKMGR_INTER_MAINPLLLOCKED_MASK                        0x00000001
> +#define CLKMGR_INTER_PERPLLLOCKED_MASK                 0x00000002
> +#define CLKMGR_INTER_MAINPLLLOST_MASK                  0x00000004
> +#define CLKMGR_INTER_PERPLLLOST_MASK                   0x00000008
> +#define CLKMGR_STAT_BUSY                               (1 << 0)
> +#define CLKMGR_STAT_MAINPLL_LOCKED                     (1 << 8)
> +#define CLKMGR_STAT_PERPLL_LOCKED                      (1 << 9)
> +
> +#define CLKMGR_PLLGLOB_PD_MASK                         0x00000001
> +#define CLKMGR_PLLGLOB_RST_MASK                                0x00000002
> +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK                   0X3
> +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET                 16
> +#define CLKMGR_VCO_PSRC_EOSC1                          0
> +#define CLKMGR_VCO_PSRC_INTOSC                         1
> +#define CLKMGR_VCO_PSRC_F2S                            2
> +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK                  0X3f
> +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET                        8
> +
> +#define CLKMGR_CLKSRC_MASK                             0x7
> +#define CLKMGR_CLKSRC_OFFSET                           16
> +#define CLKMGR_CLKSRC_MAIN                             0
> +#define CLKMGR_CLKSRC_PER                              1
> +#define CLKMGR_CLKSRC_OSC1                             2
> +#define CLKMGR_CLKSRC_INTOSC                           3
> +#define CLKMGR_CLKSRC_FPGA                             4
> +#define CLKMGR_CLKCNT_MSK                              0x7ff
> +
> +#define CLKMGR_FDBCK_MDIV_MASK                         0xff
> +#define CLKMGR_FDBCK_MDIV_OFFSET                       24
> +
> +#define CLKMGR_PLLC0_DIV_MASK                          0xff
> +#define CLKMGR_PLLC1_DIV_MASK                          0xff
> +#define CLKMGR_PLLC0_EN_OFFSET                         27
> +#define CLKMGR_PLLC1_EN_OFFSET                         24
> +
> +#define CLKMGR_NOCDIV_L4MAIN_OFFSET                    0
> +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET                   8
> +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET                   16
> +#define CLKMGR_NOCDIV_CSATCLK_OFFSET                   24
> +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET                        26
> +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET                 28
> +
> +#define CLKMGR_NOCDIV_L4SPCLK_MASK                     0X3
> +#define CLKMGR_NOCDIV_DIV1                             0
> +#define CLKMGR_NOCDIV_DIV2                             1
> +#define CLKMGR_NOCDIV_DIV4                             2
> +#define CLKMGR_NOCDIV_DIV8                             3
> +#define CLKMGR_CSPDBGCLK_DIV1                          0
> +#define CLKMGR_CSPDBGCLK_DIV4                          1
> +
> +#define CLKMGR_MSCNT_CONST                             200
> +#define CLKMGR_MDIV_CONST                              6
> +#define CLKMGR_HSCNT_CONST                             9
> +
> +#define CLKMGR_VCOCALIB_MSCNT_MASK                     0xff
> +#define CLKMGR_VCOCALIB_MSCNT_OFFSET                   9
> +#define CLKMGR_VCOCALIB_HSCNT_MASK                     0xff
> +
> +#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET                 26
> +#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET                 27
> +#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET                 28
> +
> +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK              0x00000020
> +
> +#endif /* _CLOCK_MANAGER_S10_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
> new file mode 100644
> index 0000000..d4b89ac
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
> @@ -0,0 +1,29 @@
> +/*
> + *  Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#ifndef _HANDOFF_S10_H_
> +#define _HANDOFF_S10_H_
> +
> +/*
> + * Offset for HW handoff from Quartus tools
> + */
> +#define CONFIG_HANDOFF_BASE            0xFFE3F000
> +#define CONFIG_HANDOFF_MUX             (CONFIG_HANDOFF_BASE + 0x10)
> +#define CONFIG_HANDOFF_IOCTL           (CONFIG_HANDOFF_BASE + 0x1A0)
> +#define CONFIG_HANDOFF_FPGA            (CONFIG_HANDOFF_BASE + 0x330)
> +#define CONFIG_HANODFF_DELAY           (CONFIG_HANDOFF_BASE + 0x3F0)
> +#define CONFIG_HANDOFF_CLOCK           (CONFIG_HANDOFF_BASE + 0x580)
> +#define CONFIG_HANDOFF_MISC            (CONFIG_HANDOFF_BASE + 0x610)
> +#define CONFIG_HANDOFF_MAGIC_MUX       0x504D5558
> +#define CONFIG_HANDOFF_MAGIC_IOCTL     0x494F4354
> +#define CONFIG_HANDOFF_MAGIC_FPGA      0x46504741
> +#define CONFIG_HANDOFF_MAGIC_DELAY     0x444C4159
> +#define CONFIG_HANDOFF_MAGIC_CLOCK     0x434C4B53
> +#define CONFIG_HANDOFF_MAGIC_MISC      0x4D495343
> +#define CONFIG_HANDOFF_OFFSET_LENGTH   0x4
> +#define CONFIG_HANDOFF_OFFSET_DATA     0x10
> +
> +#endif /* _HANDOFF_S10_H_ */
> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> new file mode 100644
> index 0000000..3f19534
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/io.h>
> +#include <asm/arch/handoff_s10.h>
> +
> +const struct cm_config * const cm_get_default_config(void)
> +{
> +       struct cm_config *cm_handoff_cfg = (struct cm_config *)
> +               (CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA);
> +       u32 *conversion = (u32 *)cm_handoff_cfg;
> +       u32 i;
> +
> +       if (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) {
> +               writel(swab32(readl(CONFIG_HANDOFF_CLOCK)),
> +                       CONFIG_HANDOFF_CLOCK);
> +               for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
> +                       conversion[i] = swab32(conversion[i]);
> +               return cm_handoff_cfg;
> +       } else if (readl(CONFIG_HANDOFF_CLOCK) == CONFIG_HANDOFF_MAGIC_CLOCK) {
> +               return cm_handoff_cfg;
> +       } else

the above code doesn't really read well. Can you do something like this?

handoff_clk = readl(CONFIG_HANDOFF_CLOCK);
if (swab32(handoff_clk) == CONFIG_HANDOFF_MAGIC_CLOCK) {
       writel(swab32(handoff_clk);
       for...
} else if (handoff_clk == CONFIG_HANDOFF_MAGIC_CLOCK)
      return cm_handoff_cfg;

return 0;


> +               return 0;
> +}
> +
> +const unsigned int cm_get_osc_clk_hz(const int osc)

What's "osc" used for?

Dinh

[U-Boot] [PATCH v2 03/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add Reset Manager driver support for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                     |   1 +
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
>  .../include/mach/reset_manager_arria10.h           |   8 +-
>  .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 ++++++++++++++++++++
>  arch/arm/mach-socfpga/reset_manager.c              |  41 +++++++
>  arch/arm/mach-socfpga/reset_manager_arria10.c      |  67 +++---------
>  arch/arm/mach-socfpga/reset_manager_gen5.c         |  33 ------
>  arch/arm/mach-socfpga/reset_manager_s10.c          | 118 +++++++++++++++++++++
>  include/dt-bindings/reset/altr,rst-mgr-s10.h       |  97 +++++++++++++++++
>  9 files changed, 395 insertions(+), 88 deletions(-)

Yikes! Can you find a way to split this patch up? Looks like you're
adding support
for Stratix10, but you're also messing with gen5 and arria10 stuff,
it's a bit hard to
review.

Thanks,
Dinh

[U-Boot] [PATCH v2 04/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add pinmux driver support for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                     |   2 +
>  .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
>  .../mach-socfpga/include/mach/system_manager_s10.h | 169 +++++++++++++++++++++
>  arch/arm/mach-socfpga/system_manager_s10.c         |  91 +++++++++++
>  arch/arm/mach-socfpga/wrap_pinmux_config_s10.c     |  55 +++++++
>  5 files changed, 321 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>  create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
>  create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
>

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>

[U-Boot] [PATCH v2 05/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add misc support such as EMAC and cpu info printout for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile            |   1 +
>  arch/arm/mach-socfpga/include/mach/misc.h |   1 +
>  arch/arm/mach-socfpga/misc.c              |  76 ++++++++++++++++++++
>  arch/arm/mach-socfpga/misc_gen5.c         |  75 ++-----------------
>  arch/arm/mach-socfpga/misc_s10.c          | 115 ++++++++++++++++++++++++++++++
>  5 files changed, 197 insertions(+), 71 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>

I can see a few ways this patch can get split up to more
manageable pieces. The bridge enablement  can be separated.
The wrap of CONFIG_SYS_L2_PL310 can be separate. The
split of the emac reset can be separate. This would allow for
easier review.

Dinh

[U-Boot] [PATCH v2 06/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add mailbox support for Stratix SoC
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                   |   1 +
>  arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++++++++++
>  arch/arm/mach-socfpga/mailbox_s10.c              | 238 +++++++++++++++++++++++
>  3 files changed, 347 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>  create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b253914..43e18d2 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y  += clock_manager_s10.o
> +obj-y  += mailbox_s10.o
>  obj-y  += misc_s10.o
>  obj-y  += reset_manager_s10.o
>  obj-y  += system_manager_s10.o
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> new file mode 100644
> index 0000000..b9bddf6
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +#ifndef _MAILBOX_S10_H_
> +#define _MAILBOX_S10_H_
> +
> +/* user define Uboot ID */
> +#define MBOX_CLIENT_ID_UBOOT   0xB
> +#define MBOX_ID_UBOOT          0x1
> +
> +#define MBOX_MAX_CMD_INDEX     2047
> +#define MBOX_CMD_BUFFER_SIZE   32
> +#define MBOX_RESP_BUFFER_SIZE  16
> +
> +#define MBOX_HDR_CMD_LSB       0
> +#define MBOX_HDR_CMD_MSK       (BIT(11) - 1)
> +#define MBOX_HDR_I_LSB         11
> +#define MBOX_HDR_I_MSK         BIT(11)
> +#define MBOX_HDR_LEN_LSB       12
> +#define MBOX_HDR_LEN_MSK       0x007FF000
> +#define MBOX_HDR_ID_LSB                24
> +#define MBOX_HDR_ID_MSK                0x0F000000
> +#define MBOX_HDR_CLIENT_LSB    28
> +#define MBOX_HDR_CLIENT_MSK    0xF0000000
> +
> +/* Interrupt flags */
> +#define MBOX_FLAGS_INT_COE     BIT(0)  /* COUT update interrupt enable */
> +#define MBOX_FLAGS_INT_RIE     BIT(1)  /* RIN update interrupt enable */
> +#define MBOX_FLAGS_INT_UAE     BIT(8)  /* Urgent ACK interrupt enable */
> +#define MBOX_ALL_INTRS         (MBOX_FLAGS_INT_COE | \
> +                                MBOX_FLAGS_INT_RIE | \
> +                                MBOX_FLAGS_INT_UAE)
> +
> +/* Status */
> +#define MBOX_STATUS_UA_MSK     BIT(8)
> +
> +#define MBOX_CMD_HEADER(client, id, len, cmd)             \
> +       (((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
> +       (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
> +       (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)    | \
> +       (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)
> +
> +#define MBOX_RESP_ERR_GET(resp)                                \
> +       (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
> +#define MBOX_RESP_LEN_GET(resp)                        \
> +       (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
> +#define MBOX_RESP_ID_GET(resp)                         \
> +       (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
> +#define MBOX_RESP_CLIENT_GET(resp)                     \
> +       (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
> +
> +/* Response error list */
> +typedef enum {
> +       /* CMD completed succesfully, but check resp ARGS for any errors */
> +       MBOX_RESP_STATOK = 0,
> +       /* CMD is incorrectly formatted in some way */
> +       MBOX_RESP_INVALID_COMMAND = 1,
> +       /* BootROM Command code not undesrtood */
> +       MBOX_RESP_UNKNOWN_BR = 2,
> +       /* CMD code not recognized by firmware */
> +       MBOX_RESP_UNKNOWN = 3,
> +       /* Indicates that the device is not configured */
> +       MBOX_RESP_NOT_CONFIGURED = 256,
> +       /* Indicates that the device is busy */
> +       MBOX_RESP_DEVICE_BUSY = 0x1FF,
> +       /* Indicates that there is no valid response available */
> +       MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
> +       /* General Error */
> +       MBOX_RESP_ERROR = 0x3FF,
> +} ALT_SDM_MBOX_RESP_CODE;
> +
> +/* Mailbox command list */
> +#define MBOX_RESTART           2
> +#define MBOX_QSPI_OPEN         50
> +#define MBOX_QSPI_CLOSE                51
> +#define MBOX_QSPI_DIRECT       59

Only 3 commands?

> +
> +struct socfpga_mailbox {
> +       u32 cin;                /* command valid offset */
> +       u32 rout;               /* response output offset */
> +       u32 urg;                /* urgent command */
> +       u32 flags;              /* interrupt enables */
> +       u32 pad_0x10_0x1f[4];   /* 0x10 - 0x1F reserved */
> +       u32 cout;               /* command free offset */
> +       u32 rin;                /* respond valid offset */
> +       u32 pad_0x28;           /* 0x28 reserved */
> +       u32 status;             /* mailbox status */
> +       u32 pad_0x30_0x3f[4];   /* 0x30 - 0x3F reserved */
> +       u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];      /* 0x40 - 0xBC circular command
> +                                                  buffer to SDM */
> +       u32 resp_buf[MBOX_RESP_BUFFER_SIZE];    /* 0xC0 - 0xFF circular
> +                                                  response buffer */
> +};
> +
> +/* Use define other than put into struct socfpga_mailbox to save spaces */
> +#define MBOX_DOORBELL_TO_SDM_REG       (SOCFPGA_MAILBOX_ADDRESS + 0x400)
> +#define MBOX_DOORBELL_FROM_SDM_REG     (SOCFPGA_MAILBOX_ADDRESS + 0x480)
> +
> +int mbox_init(void);
> +
> +#ifdef CONFIG_CADENCE_QSPI
> +int mbox_qspi_close(void);
> +int mbox_qspi_open(void);
> +#endif

I think these should be in a separate patch.

> +
> +#endif /* _MAILBOX_S10_H_ */
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
> new file mode 100644
> index 0000000..de836b1
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <wait_bit.h>
> +#include <asm/io.h>
> +#include <asm/arch/mailbox_s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_mailbox *mbox_base =
> +               (void *)SOCFPGA_MAILBOX_ADDRESS;
> +
> +#define MBOX_POLL_RESP_TIMEOUT         50 /* ms */
> +
> +static int mbox_polling_resp(u32 rout)
> +{
> +       u32 rin;
> +       unsigned long start = get_timer(0);
> +
> +       while (1) {
> +               rin = readl(&mbox_base->rin);
> +               if (rout != rin)
> +                       return 0;
> +
> +               if (get_timer(start) > MBOX_POLL_RESP_TIMEOUT)
> +                       break;
> +
> +               udelay(1);
> +       }
> +
> +       debug("mailbox: polling response timeout\n");
> +       return -ETIMEDOUT;
> +}
> +
> +/* Check for available slot and write to circular buffer.
> + * It also update command valid offset (cin) register.
> + */
> +static int mbox_fill_cmd_circular_buff(u32 header, u32 len, u32 *arg)
> +{
> +       u32 cmd_free_offset;
> +       u32 i;
> +
> +       /* checking available command free slot */
> +       cmd_free_offset = readl(&mbox_base->cout);
> +       if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {
> +               error("ERROR: Not enough space, cout %d\n", cmd_free_offset);
> +               return -ENOMEM;
> +       }
> +
> +       /* write header to circular buffer */
> +       writel(header, &mbox_base->cmd_buf[cmd_free_offset++]);
> +       /* wrapping around when it reach the buffer size */
> +       cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
> +
> +       /* write arguments */
> +       for (i = 0; i < len; i++) {
> +               writel(arg[i], &mbox_base->cmd_buf[cmd_free_offset++]);
> +               /* wrapping around when it reach the buffer size */
> +               cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
> +       }
> +
> +       /* write command valid offset */
> +       writel(cmd_free_offset, &mbox_base->cin);
> +       return 0;
> +}
> +
> +/* Support one command and up to 31 words argument length only */
> +int mbox_send_cmd(u8 id, u32 cmd, u32 len, u32 *arg, u8 urgent,
> +                       u32 *resp_buf_len, u32 *resp_buf)
> +{
> +       u32 header;
> +       u32 rin;
> +       u32 resp;
> +       u32 rout;
> +       u32 status;
> +       u32 resp_len;
> +       u32 buf_len;
> +       int ret;
> +
> +       /* Total lenght is command + argument length */
> +       if ((len + 1) > MBOX_CMD_BUFFER_SIZE) {
> +               error("ERROR: command %d arguments too long, max %d\n", cmd,
> +                     MBOX_CMD_BUFFER_SIZE - 1);
> +               return -EINVAL;
> +       }
> +
> +       if (cmd > MBOX_MAX_CMD_INDEX) {
> +               error("ERROR: Unsupported command index %d\n", cmd);
> +               return -EINVAL;
> +       }
> +
> +       header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id , len, cmd);
> +
> +       ret = mbox_fill_cmd_circular_buff(header, len, arg);
> +       if (ret)
> +               return ret;
> +
> +       if (urgent) {
> +               /* Send command as urgent command */
> +               writel(1, &mbox_base->urg);
> +       }
> +
> +       /* write doorbell */
> +       writel(1, MBOX_DOORBELL_TO_SDM_REG);
> +
> +       while (1) {
> +               /* Wait for doorbell from SDM */
> +               ret = wait_for_bit(__func__,
> +                                  (const u32 *)MBOX_DOORBELL_FROM_SDM_REG,
> +                                  1, true, 500000, false);

Add a define for 500000.

> +               if (ret) {
> +                       error("mailbox: timeout from SDM\n");
> +                       return ret;
> +               }
> +
> +               /* clear interrupt */
> +               writel(0, MBOX_DOORBELL_FROM_SDM_REG);
> +
> +               if (urgent) {
> +                       /* urgent command doesn't has response */
> +                       writel(0, &mbox_base->urg);
> +                       status = readl(&mbox_base->status);
> +                       if (status & MBOX_STATUS_UA_MSK)
> +                               return 0;
> +
> +                       error("mailbox: cmd %d no urgent ACK\n", cmd);
> +                       return -1;

Use '-EPERM' for -1.

> +               }
> +
> +               /* read current response offset */
> +               rout = readl(&mbox_base->rout);
> +
> +               /* read response valid offset */
> +               rin = readl(&mbox_base->rin);
> +
> +               if (rout != rin) {
> +                       /* Response received */
> +                       resp = readl(&mbox_base->resp_buf[rout]);
> +                       rout++;
> +                       /* wrapping around when it reach the buffer size */
> +                       rout %= MBOX_RESP_BUFFER_SIZE;
> +                       /* update next ROUT */
> +                       writel(rout, &mbox_base->rout);
> +
> +                       /* check client ID and ID */
> +                       if ((MBOX_RESP_CLIENT_GET(resp) ==
> +                           MBOX_CLIENT_ID_UBOOT) &&
> +                           (MBOX_RESP_ID_GET(resp) == id)) {
> +                               ret = MBOX_RESP_ERR_GET(resp);
> +                               if (ret) {
> +                                       error("mailbox send command %d error %d\n",
> +                                             cmd, ret);
> +                                       return ret;
> +                               }
> +
> +                               if (resp_buf_len) {
> +                                       buf_len = *resp_buf_len;
> +                                       *resp_buf_len = 0;
> +                               } else {
> +                                       buf_len = 0;
> +                               }
> +
> +                               resp_len = MBOX_RESP_LEN_GET(resp);
> +                               while (resp_len) {
> +                                       ret = mbox_polling_resp(rout);
> +                                       if (ret)
> +                                               return ret;
> +                                       /* we need to process response buffer
> +                                          even caller doesn't need it */

Fix comment style.

> +                                       resp = readl(&mbox_base->resp_buf[rout]);
> +                                       rout++;
> +                                       resp_len--;
> +                                       rout %= MBOX_RESP_BUFFER_SIZE;
> +                                       writel(rout, &mbox_base->rout);
> +                                       if (buf_len) {
> +                                               /* copy response to buffer */
> +                                               resp_buf[*resp_buf_len] = resp;
> +                                               (*resp_buf_len)++;
> +                                               buf_len--;
> +                                       }
> +                               }
> +                               return ret;
> +                       }
> +               }
> +       };
> +
> +       return -EIO;
> +}
> +
> +int mbox_init(void)
> +{
> +       int ret;
> +
> +       /* enable mailbox interrupts */
> +       writel(MBOX_ALL_INTRS, &mbox_base->flags);
> +
> +       ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, 0, NULL, 1, 0, NULL);
> +       if (ret)
> +               return ret;
> +
> +       /* Renable mailbox interrupts after MBOX_RESTART */
> +       writel(MBOX_ALL_INTRS, &mbox_base->flags);
> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_CADENCE_QSPI

I think this should be in a separate patch.

Dinh

[U-Boot] [PATCH v2 08/14] arm: dts: Add dts for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Device tree for Stratix10 SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/dts/Makefile                    |   3 +-
>  arch/arm/dts/socfpga_stratix10_socdk.dts | 180 +++++++++++++++++++++++++++++++
>  2 files changed, 182 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

Shouldn't you have a dtsi base file for the SOC, and then subsequent
boards would be the dts?

>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 7c062f0..f66b9c9 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               \
>         socfpga_cyclone5_sockit.dtb                     \
>         socfpga_cyclone5_socrates.dtb                   \
>         socfpga_cyclone5_sr1500.dtb                     \
> -       socfpga_cyclone5_vining_fpga.dtb
> +       socfpga_cyclone5_vining_fpga.dtb                \
> +       socfpga_stratix10_socdk.dtb
>
>  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
>         dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
> new file mode 100644
> index 0000000..26b407f
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -0,0 +1,180 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +/dts-v1/;
> +#include "skeleton.dtsi"
> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +
> +/ {
> +       model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
> +       compatible = "altr,socfpga-stratix10", "altr,socfpga";
> +
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +
> +       chosen {
> +               bootargs = "console=ttyS0,115200";
> +       };
> +
> +       aliases {
> +               ethernet0 = &gmac0;
> +               spi0 = &qspi;
> +       };
> +
> +       memory {
> +               name = "memory";
> +               device_type = "memory";
> +               reg = <0x0 0x80000000>; /* 2GB */
> +       };
> +
> +       regulator_3_3v: 3-3-v-regulator {
> +               compatible = "regulator-fixed";
> +               regulator-name = "3.3V";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu at 0 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x0>;
> +               };
> +
> +               cpu at 1 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x1>;
> +               };
> +
> +               cpu at 2 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x2>;
> +               };
> +
> +               cpu at 3 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x3>;
> +               };
> +       };
> +
> +       soc {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "simple-bus";
> +               device_type = "soc";
> +               ranges;
> +               u-boot,dm-pre-reloc;
> +
> +               rst: rstmgr at ffd11000 {
> +                       #reset-cells = <1>;
> +                       compatible = "altr,rst-mgr";
> +                       reg = <0xffd11000 0x100>;
> +                       altr,modrst-offset = <0x20>;
> +               };
> +
> +               mdio {
> +                       phy0: ethernet-phy at 0 {
> +                               txd0-skew-ps = <0>; /* -420ps */
> +                               txd1-skew-ps = <0>; /* -420ps */
> +                               txd2-skew-ps = <0>; /* -420ps */
> +                               txd3-skew-ps = <0>; /* -420ps */
> +                               rxd0-skew-ps = <420>; /* 0ps */
> +                               rxd1-skew-ps = <420>; /* 0ps */
> +                               rxd2-skew-ps = <420>; /* 0ps */
> +                               rxd3-skew-ps = <420>; /* 0ps */
> +                               txen-skew-ps = <0>; /* -420ps */
> +                               txc-skew-ps = <1860>; /* 960ps */
> +                               rxdv-skew-ps = <420>; /* 0ps */
> +                               rxc-skew-ps = <1680>; /* 780ps */
> +                       };
> +               };
> +
> +               gmac0: ethernet at ff800000 {
> +                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +                       reg = <0xff800000 0x2000>;
> +                       interrupts = <0 90 4>;
> +                       interrupt-names = "macirq";
> +                       mac-address = [00 00 00 00 00 00];
> +                       resets = <&rst EMAC0_RESET>;
> +                       reset-names = "stmmaceth";
> +                       phy-mode = "rgmii";
> +                       phy-addr = <0xffffffff>; /* probe for phy addr */

I don't a usage for 'phy-addr' in the code anymore.

Dinh

[U-Boot] [PATCH v2 09/14] arm: socfpga: Restructure the SPL file

[Dinh Nguyen]

On 10/05/2017 08:07 AM, chin.liang.see at intel.com wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
> 
> Restructure the SPL so each devices such as CV, A10 and S10
> will have their own dedicated SPL file. SPL file determine
> the HW initialization flow which is device specific
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile              |   5 +-
>  arch/arm/mach-socfpga/spl_a10.c             | 105 ++++++++++++++++++++++++++++
>  arch/arm/mach-socfpga/{spl.c => spl_gen5.c} |  46 ------------
>  3 files changed, 109 insertions(+), 47 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/spl_a10.c
>  rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)
> 

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>

Dinh

[U-Boot] [PATCH v2 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[Dinh Nguyen]

On 10/05/2017 08:07 AM, chin.liang.see at intel.com wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
> 
> Add SPL driver support for Stratix SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                    |   4 +
>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |  84 +++++++++++++
>  arch/arm/mach-socfpga/spl_s10.c                   | 138 ++++++++++++++++++++++
>  3 files changed, 226 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b669d43..35b124a 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -40,6 +40,7 @@ obj-y	+= system_manager_s10.o
>  obj-y	+= wrap_pinmux_config_s10.o
>  obj-y	+= wrap_pll_config_s10.o
>  endif
> +
>  ifdef CONFIG_SPL_BUILD
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>  obj-y	+= spl_gen5.o
> @@ -51,6 +52,9 @@ endif
>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>  obj-y	+= spl_a10.o
>  endif
> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> +obj-y	+= spl_s10.o
> +endif
>  endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
> new file mode 100644
> index 0000000..6894bb9
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef	_FIREWALL_S10_
> +#define	_FIREWALL_S10_
> +
> +struct socfpga_firwall_l4_per {
> +	u32	nand;		/* 0x00 */
> +	u32	nand_data;
> +	u32	_pad_0x8;
> +	u32	usb0;
> +	u32	usb1;		/* 0x10 */
> +	u32	_pad_0x14;
> +	u32	_pad_0x18;
> +	u32	spim0;
> +	u32	spim1;		/* 0x20 */
> +	u32	spis0;
> +	u32	spis1;
> +	u32	emac0;
> +	u32	emac1;		/* 0x30 */
> +	u32	emac2;
> +	u32	_pad_0x38;
> +	u32	_pad_0x3c;
> +	u32	sdmmc;		/* 0x40 */
> +	u32	gpio0;
> +	u32	gpio1;
> +	u32	_pad_0x4c;
> +	u32	i2c0;		/* 0x50 */
> +	u32	i2c1;
> +	u32	i2c2;
> +	u32	i2c3;
> +	u32	i2c4;		/* 0x60 */
> +	u32	timer0;
> +	u32	timer1;
> +	u32	uart0;
> +	u32	uart1;		/* 0x70 */
> +};
> +
> +struct socfpga_firwall_l4_sys {
> +	u32	_pad_0x00;		/* 0x00 */
> +	u32	_pad_0x04;
> +	u32	dma_ecc;
> +	u32	emac0rx_ecc;
> +	u32	emac0tx_ecc;		/* 0x10 */
> +	u32	emac1rx_ecc;
> +	u32	emac1tx_ecc;
> +	u32	emac2rx_ecc;
> +	u32	emac2tx_ecc;		/* 0x20 */
> +	u32	_pad_0x24;
> +	u32	_pad_0x28;
> +	u32	nand_ecc;
> +	u32	nand_read_ecc;		/* 0x30 */
> +	u32	nand_write_ecc;
> +	u32	ocram_ecc;
> +	u32	_pad_0x3c;
> +	u32	sdmmc_ecc;		/* 0x40 */
> +	u32	usb0_ecc;
> +	u32	usb1_ecc;
> +	u32	clock_manager;
> +	u32	_pad_0x50;		/* 0x50 */
> +	u32	io_manager;
> +	u32	reset_manager;
> +	u32	system_manager;
> +	u32	osc0_timer;		/* 0x60 */
> +	u32	osc1_timer;
> +	u32	watchdog0;
> +	u32	watchdog1;
> +	u32	watchdog2;		/* 0x70 */
> +	u32	watchdog3;
> +};
> +
> +#define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
> +#define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
> +
> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7004688
> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR	0xf7018628
> +
> +#define CCU_ADMASK_P_MASK			(BIT(0))
> +#define CCU_ADMASK_NS_MASK			(BIT(1))
> +
> +#endif /* _FIREWALL_S10_ */
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> new file mode 100644
> index 0000000..12cafe6
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -0,0 +1,138 @@
> +/*
> + *  Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/u-boot.h>
> +#include <asm/utils.h>
> +#include <image.h>
> +#include <asm/arch/reset_manager.h>
> +#include <spl.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/arch/sdram_s10.h>
> +#include <asm/arch/mailbox_s10.h>
> +#include <asm/arch/firewall_s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
> +	(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
> +	(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
> +
> +u32 spl_boot_device(void)
> +{
> +	/* TODO: Get from SDM or handoff */
> +/* #ifdef CONFIG_CADENCE_QSPI*/
> +#if 0

Remove the '#if 0'.

> +	return BOOT_DEVICE_SPI;
> +#else
> +	return BOOT_DEVICE_MMC1;
> +#endif
> +}
> +
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
> +	return MMCSD_MODE_FS;
> +#else
> +	return MMCSD_MODE_RAW;
> +#endif
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	const struct cm_config *cm_default_cfg = cm_get_default_config();
> +
> +	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
> +	timer_init();
> +
> +	populate_sysmgr_pinmux();
> +
> +	/* configuring the HPS clocks */
> +	cm_basic_init(cm_default_cfg);
> +
> +	/* enable console uart printing */
> +#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS)
> +	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> +	/* enables nonsecure access to UART0 */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0);
> +#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS)
> +	socfpga_per_reset(SOCFPGA_RESET(UART1), 0);
> +	/* enables nonsecure access to UART1 */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1);
> +#endif
> +
> +	preloader_console_init();
> +	cm_print_clock_quick_summary();
> +
> +	/* enable all EMACs */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2);
> +	/* enables nonsecure access to all the emacs */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc);
> +
> +	/* enables SDMMC */
> +	socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
> +	/* Enables nonsecure access to SDMMC */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc);
> +
> +	/* enable i2c0 and i2c1 */
> +	socfpga_per_reset(SOCFPGA_RESET(I2C0), 0);
> +	socfpga_per_reset(SOCFPGA_RESET(I2C1), 0);
> +	/* enables nonsecure access to i2c0 and i2c1 */
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0);
> +	writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1);

I'd enable non-secure access to all of the HPS peripherals, USB, SPIM,
GPIO, and timers.

Dinh

[U-Boot] [PATCH v2 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[Dinh Nguyen]

On 10/05/2017 08:07 AM, chin.liang.see at intel.com wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
> 
> Add timer support for Stratix SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/timer.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>

Dinh

[U-Boot] [PATCH v2 06/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Dinh Nguyen]

On 10/05/2017 08:07 AM, chin.liang.see at intel.com wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
> 
> Add mailbox support for Stratix SoC
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                   |   1 +
>  arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++++++++++
>  arch/arm/mach-socfpga/mailbox_s10.c              | 238 +++++++++++++++++++++++
>  3 files changed, 347 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>  create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b253914..43e18d2 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y	+= clock_manager_s10.o
> +obj-y	+= mailbox_s10.o
>  obj-y	+= misc_s10.o
>  obj-y	+= reset_manager_s10.o
>  obj-y	+= system_manager_s10.o
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> new file mode 100644
> index 0000000..b9bddf6
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +#ifndef _MAILBOX_S10_H_
> +#define _MAILBOX_S10_H_
> +
> +/* user define Uboot ID */
> +#define MBOX_CLIENT_ID_UBOOT	0xB
> +#define MBOX_ID_UBOOT		0x1
> +
> +#define MBOX_MAX_CMD_INDEX	2047
> +#define MBOX_CMD_BUFFER_SIZE	32
> +#define MBOX_RESP_BUFFER_SIZE	16
> +
> +#define MBOX_HDR_CMD_LSB	0
> +#define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
> +#define MBOX_HDR_I_LSB		11
> +#define MBOX_HDR_I_MSK		BIT(11)
> +#define MBOX_HDR_LEN_LSB	12
> +#define MBOX_HDR_LEN_MSK	0x007FF000
> +#define MBOX_HDR_ID_LSB		24
> +#define MBOX_HDR_ID_MSK		0x0F000000
> +#define MBOX_HDR_CLIENT_LSB	28
> +#define MBOX_HDR_CLIENT_MSK	0xF0000000
> +
> +/* Interrupt flags */
> +#define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
> +#define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
> +#define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
> +#define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
> +				 MBOX_FLAGS_INT_RIE | \
> +				 MBOX_FLAGS_INT_UAE)
> +
> +/* Status */
> +#define MBOX_STATUS_UA_MSK	BIT(8)
> +
> +#define MBOX_CMD_HEADER(client, id, len, cmd)		   \
> +	(((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
> +	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
> +	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)	 | \
> +	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)
> +
> +#define MBOX_RESP_ERR_GET(resp)				\
> +	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
> +#define MBOX_RESP_LEN_GET(resp)			\
> +	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
> +#define MBOX_RESP_ID_GET(resp)				\
> +	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
> +#define MBOX_RESP_CLIENT_GET(resp)			\
> +	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
> +
> +/* Response error list */
> +typedef enum {
> +	/* CMD completed succesfully, but check resp ARGS for any errors */
> +	MBOX_RESP_STATOK = 0,
> +	/* CMD is incorrectly formatted in some way */
> +	MBOX_RESP_INVALID_COMMAND = 1,
> +	/* BootROM Command code not undesrtood */
> +	MBOX_RESP_UNKNOWN_BR = 2,
> +	/* CMD code not recognized by firmware */
> +	MBOX_RESP_UNKNOWN = 3,
> +	/* Indicates that the device is not configured */
> +	MBOX_RESP_NOT_CONFIGURED = 256,
> +	/* Indicates that the device is busy */
> +	MBOX_RESP_DEVICE_BUSY = 0x1FF,
> +	/* Indicates that there is no valid response available */
> +	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
> +	/* General Error */
> +	MBOX_RESP_ERROR = 0x3FF,
> +} ALT_SDM_MBOX_RESP_CODE;
> +
> +/* Mailbox command list */
> +#define MBOX_RESTART		2
> +#define MBOX_QSPI_OPEN		50
> +#define MBOX_QSPI_CLOSE		51
> +#define MBOX_QSPI_DIRECT	59
> +
> +struct socfpga_mailbox {
> +	u32 cin;		/* command valid offset */
> +	u32 rout;		/* response output offset */
> +	u32 urg;		/* urgent command */
> +	u32 flags;		/* interrupt enables */
> +	u32 pad_0x10_0x1f[4];	/* 0x10 - 0x1F reserved */
> +	u32 cout;		/* command free offset */
> +	u32 rin;		/* respond valid offset */
> +	u32 pad_0x28;		/* 0x28 reserved */
> +	u32 status;		/* mailbox status */
> +	u32 pad_0x30_0x3f[4];	/* 0x30 - 0x3F reserved */
> +	u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];	/* 0x40 - 0xBC circular command
> +						   buffer to SDM */
> +	u32 resp_buf[MBOX_RESP_BUFFER_SIZE];	/* 0xC0 - 0xFF circular
> +						   response buffer */
> +};
> +
> +/* Use define other than put into struct socfpga_mailbox to save spaces */
> +#define MBOX_DOORBELL_TO_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x400)
> +#define MBOX_DOORBELL_FROM_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x480)
> +
> +int mbox_init(void);
> +
> +#ifdef CONFIG_CADENCE_QSPI
> +int mbox_qspi_close(void);
> +int mbox_qspi_open(void);
> +#endif
> +
> +#endif	/* _MAILBOX_S10_H_ */
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
> new file mode 100644
> index 0000000..de836b1
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <wait_bit.h>
> +#include <asm/io.h>
> +#include <asm/arch/mailbox_s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_mailbox *mbox_base =
> +		(void *)SOCFPGA_MAILBOX_ADDRESS;
> +
> +#define MBOX_POLL_RESP_TIMEOUT		50 /* ms */
> +
> +static int mbox_polling_resp(u32 rout)
> +{
> +	u32 rin;
> +	unsigned long start = get_timer(0);
> +
> +	while (1) {
> +		rin = readl(&mbox_base->rin);
> +		if (rout != rin)
> +			return 0;
> +
> +		if (get_timer(start) > MBOX_POLL_RESP_TIMEOUT)
> +			break;
> +
> +		udelay(1);
> +	}
> +
> +	debug("mailbox: polling response timeout\n");
> +	return -ETIMEDOUT;
> +}
> +
> +/* Check for available slot and write to circular buffer.
> + * It also update command valid offset (cin) register.
> + */
> +static int mbox_fill_cmd_circular_buff(u32 header, u32 len, u32 *arg)
> +{
> +	u32 cmd_free_offset;
> +	u32 i;
> +
> +	/* checking available command free slot */
> +	cmd_free_offset = readl(&mbox_base->cout);
> +	if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {
> +		error("ERROR: Not enough space, cout %d\n", cmd_free_offset);

I'm getting these build error:

arch/arm/mach-socfpga/mailbox_s10.c: In function
‘mbox_fill_cmd_circular_buff’:
arch/arm/mach-socfpga/mailbox_s10.c:50:3: warning: implicit declaration
of function ‘error’ [-Wimplicit-function-declaration]
   error("ERROR: Not enough space, cout %d\n", cmd_free_offset)

arch/arm/mach-socfpga/built-in.o: In function `mbox_send_cmd':
/home/dinguyen/linux_dev/u-boot/arch/arm/mach-socfpga/mailbox_s10.c:86:
undefined reference to `error'

Please at least do a compile test on your patches in the future.

Dinh

[U-Boot] [PATCH v2 06/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Dinh Nguyen]

On Wed, Oct 11, 2017 at 4:33 AM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
>
> On 10/05/2017 08:07 AM, chin.liang.see at intel.com wrote:
>> From: Chin Liang See <chin.liang.see@intel.com>
>>
>> Add mailbox support for Stratix SoC
>>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> ---
>>  arch/arm/mach-socfpga/Makefile                   |   1 +
>>  arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++++++++++
>>  arch/arm/mach-socfpga/mailbox_s10.c              | 238 +++++++++++++++++++++++
>>  3 files changed, 347 insertions(+)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>>  create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index b253914..43e18d2 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -32,6 +32,7 @@ endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>  obj-y        += clock_manager_s10.o
>> +obj-y        += mailbox_s10.o
>>  obj-y        += misc_s10.o
>>  obj-y        += reset_manager_s10.o
>>  obj-y        += system_manager_s10.o
>> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>> new file mode 100644
>> index 0000000..b9bddf6
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
>> @@ -0,0 +1,108 @@
>> +/*
>> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0
>> + */
>> +#ifndef _MAILBOX_S10_H_
>> +#define _MAILBOX_S10_H_
>> +
>> +/* user define Uboot ID */
>> +#define MBOX_CLIENT_ID_UBOOT 0xB
>> +#define MBOX_ID_UBOOT                0x1
>> +
>> +#define MBOX_MAX_CMD_INDEX   2047
>> +#define MBOX_CMD_BUFFER_SIZE 32
>> +#define MBOX_RESP_BUFFER_SIZE        16
>> +
>> +#define MBOX_HDR_CMD_LSB     0
>> +#define MBOX_HDR_CMD_MSK     (BIT(11) - 1)
>> +#define MBOX_HDR_I_LSB               11
>> +#define MBOX_HDR_I_MSK               BIT(11)
>> +#define MBOX_HDR_LEN_LSB     12
>> +#define MBOX_HDR_LEN_MSK     0x007FF000
>> +#define MBOX_HDR_ID_LSB              24
>> +#define MBOX_HDR_ID_MSK              0x0F000000
>> +#define MBOX_HDR_CLIENT_LSB  28
>> +#define MBOX_HDR_CLIENT_MSK  0xF0000000
>> +
>> +/* Interrupt flags */
>> +#define MBOX_FLAGS_INT_COE   BIT(0)  /* COUT update interrupt enable */
>> +#define MBOX_FLAGS_INT_RIE   BIT(1)  /* RIN update interrupt enable */
>> +#define MBOX_FLAGS_INT_UAE   BIT(8)  /* Urgent ACK interrupt enable */
>> +#define MBOX_ALL_INTRS               (MBOX_FLAGS_INT_COE | \
>> +                              MBOX_FLAGS_INT_RIE | \
>> +                              MBOX_FLAGS_INT_UAE)
>> +
>> +/* Status */
>> +#define MBOX_STATUS_UA_MSK   BIT(8)
>> +
>> +#define MBOX_CMD_HEADER(client, id, len, cmd)                   \
>> +     (((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
>> +     (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
>> +     (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)    | \
>> +     (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)
>> +
>> +#define MBOX_RESP_ERR_GET(resp)                              \
>> +     (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
>> +#define MBOX_RESP_LEN_GET(resp)                      \
>> +     (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
>> +#define MBOX_RESP_ID_GET(resp)                               \
>> +     (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
>> +#define MBOX_RESP_CLIENT_GET(resp)                   \
>> +     (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
>> +
>> +/* Response error list */
>> +typedef enum {
>> +     /* CMD completed succesfully, but check resp ARGS for any errors */
>> +     MBOX_RESP_STATOK = 0,
>> +     /* CMD is incorrectly formatted in some way */
>> +     MBOX_RESP_INVALID_COMMAND = 1,
>> +     /* BootROM Command code not undesrtood */
>> +     MBOX_RESP_UNKNOWN_BR = 2,
>> +     /* CMD code not recognized by firmware */
>> +     MBOX_RESP_UNKNOWN = 3,
>> +     /* Indicates that the device is not configured */
>> +     MBOX_RESP_NOT_CONFIGURED = 256,
>> +     /* Indicates that the device is busy */
>> +     MBOX_RESP_DEVICE_BUSY = 0x1FF,
>> +     /* Indicates that there is no valid response available */
>> +     MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
>> +     /* General Error */
>> +     MBOX_RESP_ERROR = 0x3FF,
>> +} ALT_SDM_MBOX_RESP_CODE;
>> +
>> +/* Mailbox command list */
>> +#define MBOX_RESTART         2
>> +#define MBOX_QSPI_OPEN               50
>> +#define MBOX_QSPI_CLOSE              51
>> +#define MBOX_QSPI_DIRECT     59
>> +
>> +struct socfpga_mailbox {
>> +     u32 cin;                /* command valid offset */
>> +     u32 rout;               /* response output offset */
>> +     u32 urg;                /* urgent command */
>> +     u32 flags;              /* interrupt enables */
>> +     u32 pad_0x10_0x1f[4];   /* 0x10 - 0x1F reserved */
>> +     u32 cout;               /* command free offset */
>> +     u32 rin;                /* respond valid offset */
>> +     u32 pad_0x28;           /* 0x28 reserved */
>> +     u32 status;             /* mailbox status */
>> +     u32 pad_0x30_0x3f[4];   /* 0x30 - 0x3F reserved */
>> +     u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];      /* 0x40 - 0xBC circular command
>> +                                                buffer to SDM */
>> +     u32 resp_buf[MBOX_RESP_BUFFER_SIZE];    /* 0xC0 - 0xFF circular
>> +                                                response buffer */
>> +};
>> +
>> +/* Use define other than put into struct socfpga_mailbox to save spaces */
>> +#define MBOX_DOORBELL_TO_SDM_REG     (SOCFPGA_MAILBOX_ADDRESS + 0x400)
>> +#define MBOX_DOORBELL_FROM_SDM_REG   (SOCFPGA_MAILBOX_ADDRESS + 0x480)
>> +
>> +int mbox_init(void);
>> +
>> +#ifdef CONFIG_CADENCE_QSPI
>> +int mbox_qspi_close(void);
>> +int mbox_qspi_open(void);
>> +#endif
>> +
>> +#endif       /* _MAILBOX_S10_H_ */
>> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
>> new file mode 100644
>> index 0000000..de836b1
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
>> @@ -0,0 +1,238 @@
>> +/*
>> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0
>> + */
>> +
>> +#include <common.h>
>> +#include <wait_bit.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/mailbox_s10.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static const struct socfpga_mailbox *mbox_base =
>> +             (void *)SOCFPGA_MAILBOX_ADDRESS;
>> +
>> +#define MBOX_POLL_RESP_TIMEOUT               50 /* ms */
>> +
>> +static int mbox_polling_resp(u32 rout)
>> +{
>> +     u32 rin;
>> +     unsigned long start = get_timer(0);
>> +
>> +     while (1) {
>> +             rin = readl(&mbox_base->rin);
>> +             if (rout != rin)
>> +                     return 0;
>> +
>> +             if (get_timer(start) > MBOX_POLL_RESP_TIMEOUT)
>> +                     break;
>> +
>> +             udelay(1);
>> +     }
>> +
>> +     debug("mailbox: polling response timeout\n");
>> +     return -ETIMEDOUT;
>> +}
>> +
>> +/* Check for available slot and write to circular buffer.
>> + * It also update command valid offset (cin) register.
>> + */
>> +static int mbox_fill_cmd_circular_buff(u32 header, u32 len, u32 *arg)
>> +{
>> +     u32 cmd_free_offset;
>> +     u32 i;
>> +
>> +     /* checking available command free slot */
>> +     cmd_free_offset = readl(&mbox_base->cout);
>> +     if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {
>> +             error("ERROR: Not enough space, cout %d\n", cmd_free_offset);
>
> I'm getting these build error:
>
> arch/arm/mach-socfpga/mailbox_s10.c: In function
> ‘mbox_fill_cmd_circular_buff’:
> arch/arm/mach-socfpga/mailbox_s10.c:50:3: warning: implicit declaration
> of function ‘error’ [-Wimplicit-function-declaration]
>    error("ERROR: Not enough space, cout %d\n", cmd_free_offset)
>
> arch/arm/mach-socfpga/built-in.o: In function `mbox_send_cmd':
> /home/dinguyen/linux_dev/u-boot/arch/arm/mach-socfpga/mailbox_s10.c:86:
> undefined reference to `error'
>
> Please at least do a compile test on your patches in the future.
>


FYI: the reason for the above error is because of this commit:

commit 9b643e312d528f291966c1f30b0d90bf3b1d43dc
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Date:   Sat Sep 16 14:10:41 2017 +0900

    treewide: replace with error() with pr_err()

Please use pr_error().

Dinh

[U-Boot] [PATCH v2 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add DDR support for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +++++++++++++++++++++
>  drivers/ddr/altera/Makefile                    |   1 +
>  drivers/ddr/altera/sdram_s10.c                 | 382 +++++++++++++++++++++++++
>  3 files changed, 716 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
>  create mode 100644 drivers/ddr/altera/sdram_s10.c
>
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
> new file mode 100644
> index 0000000..d0fd958

[...]

> diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
> index bdd2872..943b6cd 100644
> --- a/drivers/ddr/altera/Makefile
> +++ b/drivers/ddr/altera/Makefile
> @@ -10,4 +10,5 @@
>
>  ifdef CONFIG_ALTERA_SDRAM
>  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
> +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
>  endif
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> new file mode 100644
> index 0000000..c488caf
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -0,0 +1,382 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <div64.h>
> +#include <asm/io.h>
> +#include <watchdog.h>
> +#include <asm/arch/sdram_s10.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/reset_manager.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
> +               (void *)SOCFPGA_SDR_ADDRESS;
> +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
> +               (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
> +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
> +               (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
> +static const struct socfpga_system_manager *sysmgr_regs =
> +               (void *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +#define DDR_CONFIG(A, B, C, R) ((A<<24)|(B<<16)|(C<<8)|R)
> +
> +/* The followring are the supported configurations */
> +u32 ddr_config[] = {
> +       /* DDR_CONFIG(Address order,Bank,Column,Row) */
> +       /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
> +       DDR_CONFIG(0, 3, 10, 12),
> +       DDR_CONFIG(0, 3,  9, 13),
> +       DDR_CONFIG(0, 3, 10, 13),
> +       DDR_CONFIG(0, 3,  9, 14),
> +       DDR_CONFIG(0, 3, 10, 14),
> +       DDR_CONFIG(0, 3, 10, 15),
> +       DDR_CONFIG(0, 3, 11, 14),
> +       DDR_CONFIG(0, 3, 11, 15),
> +       DDR_CONFIG(0, 3, 10, 16),
> +       DDR_CONFIG(0, 3, 11, 16),
> +       DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
> +       /* List for DDR4 only (pinout order > chip, bank, row, column) */
> +       DDR_CONFIG(1, 3, 10, 14),
> +       DDR_CONFIG(1, 4, 10, 14),
> +       DDR_CONFIG(1, 3, 10, 15),
> +       DDR_CONFIG(1, 4, 10, 15),
> +       DDR_CONFIG(1, 3, 10, 16),
> +       DDR_CONFIG(1, 4, 10, 16),
> +       DDR_CONFIG(1, 3, 10, 17),
> +       DDR_CONFIG(1, 4, 10, 17),
> +};
> +
> +#define DDR_CONFIG_ELEMENTS    (sizeof(ddr_config)/sizeof(u32))
> +
> +int match_ddr_conf(u32 ddr_conf)

Should be static.

> +{
> +       int i;
> +       for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
> +               if (ddr_conf == ddr_config[i])
> +                       return i;
> +       }
> +       return 0;
> +}
> +
> +static int emif_clear(void)
> +{
> +       u32 s2c, i;
> +
> +       writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl);
> +       s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +             DDR_HMC_RSTHANDSHAKE_MASK;
> +
> +       for (i = 1000; (i > 0) && s2c; i--) {
> +               WATCHDOG_RESET();
> +               mdelay(1);
> +               s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +                     DDR_HMC_RSTHANDSHAKE_MASK;
> +       }
> +       return !s2c;
> +}
> +
> +static int emif_reset(void)

What's the return used for? I don't see the callers of emif_reset checking
the return values at all.

> +{
> +       u32 c2s, s2c, i;
> +
> +       c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) &
> +             DDR_HMC_RSTHANDSHAKE_MASK;
> +       s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +             DDR_HMC_RSTHANDSHAKE_MASK;
> +
> +       debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
> +             c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0),
> +             readl(&socfpga_io48_mmr_base->niosreserve1),
> +             readl(&socfpga_io48_mmr_base->niosreserve2),
> +             readl(&socfpga_io48_mmr_base->dramsts));
> +
> +       if (s2c && emif_clear()) {
> +               printf("DDR: emif_clear() failed\n");
> +               return -1;
> +       }
> +
> +       puts("DDR: Triggerring emif_reset\n");
> +       writel(DDR_HMC_CORE2SEQ_INT_REQ,
> +              &socfpga_ecc_hmc_base->rsthandshakectrl);
> +
> +       for (i = 1000; i > 0; i--) {
> +               /* if seq2core[3] = 0, we are good */
> +               if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) &
> +                   DDR_HMC_SEQ2CORE_INT_RESP_MASK))
> +                       break;
> +               WATCHDOG_RESET();
> +               mdelay(1);
> +       }
> +
> +       if (!i) {
> +               printf("DDR: failed to get ack from EMIF\n");
> +               return -2;
> +       }
> +
> +       if (emif_clear()) {
> +               printf("DDR: emif_clear() failed\n");
> +               return -3;
> +       }
> +
> +       printf("DDR: emif_reset triggered successly\n");
> +       return 0;
> +}
> +
> +static int poll_hmc_clock_status(void)
> +{
> +       u32 status, i;
> +
> +       for (i = 1000; i > 0; i--) {
> +               status = readl(&sysmgr_regs->hmc_clk) &
> +                        SYSMGR_HMC_CLK_STATUS_MSK;
> +               udelay(1);
> +               if (status)
> +                       break;
> +               WATCHDOG_RESET();
> +       }
> +       return status;
> +}
> +
> +/**
> + * sdram_mmr_init_full() - Function to initialize SDRAM MMR
> + *
> + * Initialize the SDRAM MMR.

Remove extra comment that says the same thing.

> + */
> +int sdram_mmr_init_full(unsigned int unused)
> +{
> +       u32 update_value, io48_value, ddrioctl;
> +       u32 i, j, cal_success;
> +
> +       /* Enable access to DDR from CPU master */
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);
> +
> +       /* Enable access to DDR from IO master */
> +       clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK);
> +       clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK);
> +
> +       /* this enables nonsecure access to DDR */
> +       /* mpuregion0addr_limit */
> +       writel(0xFFFF0000, 0xF8020118);
> +       writel(0x1F, 0xF802011c);
> +
> +       /* nonmpuregion0addr_limit */
> +       writel(0xFFFF0000, 0xF8020198);
> +       writel(0x1F, 0xF802019C);
> +
> +       /* Enable mpuregion0enable and nonmpuregion0enable */
> +       writel(BIT(0) | BIT(8), 0xF8020100);

Add defines for the above addresses please.

> +
> +       /* Ensure HMC clock is running */
> +       if (!poll_hmc_clock_status()) {
> +               puts("DDR: Error as HMC clock not running\n");
> +               return -1;

Use a valid error code...

> +       }
> +
> +       /* release DDR scheduler from reset */
> +       socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> +
> +       /* Try 3 times to do a calibration */
> +       for (i = 0; i < 3; i++) {
> +               cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) &
> +                             DDR_HMC_DDRCALSTAT_CAL_MSK;
> +               /* A delay to wait for calibration bit to set */
> +               for (j = 0; (j < 1000) && !cal_success; j++) {
> +                       WATCHDOG_RESET();
> +                       mdelay(1);
> +                       cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat)
> +                                     & DDR_HMC_DDRCALSTAT_CAL_MSK;
> +               }
> +
> +               if (cal_success)
> +                       break;
> +               else
> +                       emif_reset();
> +       }
> +
> +       if (!cal_success) {
> +               puts("DDR: Error as SDRAM calibration failed\n");
> +               return -1;

Use a valid error code..

Dinh

[U-Boot] [PATCH v2 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add socdk board support for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  board/altera/stratix10-socdk/MAINTAINERS | 7 +++++++
>  board/altera/stratix10-socdk/Makefile    | 7 +++++++
>  board/altera/stratix10-socdk/socfpga.c   | 7 +++++++
>  3 files changed, 21 insertions(+)
>  create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
>  create mode 100644 board/altera/stratix10-socdk/Makefile
>  create mode 100644 board/altera/stratix10-socdk/socfpga.c
>
> diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS
> new file mode 100644
> index 0000000..6192bc9
> --- /dev/null
> +++ b/board/altera/stratix10-socdk/MAINTAINERS
> @@ -0,0 +1,7 @@
> +SOCFPGA BOARD
> +M:     Chin-Liang See <chin.liang.see@intel.com>
> +M:     Dinh Nguyen <dinh.nguyen@intel.com>

Use dinguyen at kernel.org please.

Dinh

[U-Boot] [PATCH v2 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,  <chin.liang.see@intel.com> wrote:
> From: Chin Liang See <chin.liang.see@intel.com>
>
> Add build support for Stratix SoC
>
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> ---
>  arch/arm/Kconfig                          |   8 +-
>  arch/arm/mach-socfpga/Kconfig             |  13 ++
>  configs/socfpga_stratix10_defconfig       |  39 ++++++
>  include/configs/socfpga_stratix10_socdk.h | 216 ++++++++++++++++++++++++++++++
>  4 files changed, 273 insertions(+), 3 deletions(-)
>  create mode 100644 configs/socfpga_stratix10_defconfig
>  create mode 100644 include/configs/socfpga_stratix10_socdk.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d6d9558..4a6b9da 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -656,21 +656,23 @@ config ARCH_SNAPDRAGON
>
>  config ARCH_SOCFPGA
>         bool "Altera SOCFPGA family"
> -       select CPU_V7
> +       select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
> +       select ARM64 if TARGET_SOCFPGA_STRATIX10
>         select SUPPORT_SPL
>         select OF_CONTROL
>         select SPL_OF_CONTROL
>         select DM
>         select DM_SPI_FLASH
>         select DM_SPI
> -       select ENABLE_ARM_SOC_BOOT0_HOOK
> +       select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
>         select ARCH_EARLY_INIT_R
>         select ARCH_MISC_INIT
>         select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
> -       select SYS_THUMB_BUILD
> +       select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
>         imply CMD_MTDPARTS
>         imply CRC32_VERIFY
>         imply FAT_WRITE
> +       select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
>
>  config ARCH_SUNXI
>         bool "Support sunxi (Allwinner) SoCs"
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 45e5379..03ab956 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5
>         bool
>         select ALTERA_SDRAM
>
> +config TARGET_SOCFPGA_STRATIX10
> +       bool
> +       select ARMV8_MULTIENTRY
> +       select ARMV8_SPIN_TABLE
> +       select ARMV8_SET_SMPEN
> +
>  choice
>         prompt "Altera SOCFPGA board select"
>         optional
> @@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500
>         bool "SR1500 (Cyclone V)"
>         select TARGET_SOCFPGA_CYCLONE5
>
> +config TARGET_SOCFPGA_STRATIX10_SOCDK
> +       bool "Intel SOCFPGA SoCDK (Stratix 10)"
> +       select TARGET_SOCFPGA_STRATIX10
> +
>  config TARGET_SOCFPGA_TERASIC_DE0_NANO
>         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
>         select TARGET_SOCFPGA_CYCLONE5
> @@ -116,12 +126,14 @@ config SYS_BOARD
>         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
>         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
>         default "sr1500" if TARGET_SOCFPGA_SR1500
> +       default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
>         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>
>  config SYS_VENDOR
>         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
>         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
>         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
> +       default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
>         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
>         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
>         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> @@ -145,6 +157,7 @@ config SYS_CONFIG_NAME
>         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
>         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
>         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
> +       default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
>         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>
>  endif
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> new file mode 100644
> index 0000000..e5a7a69
> --- /dev/null
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -0,0 +1,39 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SOCFPGA=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SPL_FAT_SUPPORT=y
> +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
> +CONFIG_IDENT_STRING="socfpga_stratix10"
> +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
> +CONFIG_BOOTDELAY=5
> +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_FAT=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_FS_GENERIC=y
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_SF=y
> +CONFIG_SPL=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_DM_MMC=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_DFU_MMC=y
> +CONFIG_MMC_DW=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> +CONFIG_CADENCE_QSPI=y
> +CONFIG_DM_ETH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_USE_TINY_PRINTF=y
> diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
> new file mode 100644
> index 0000000..0d955f8
> --- /dev/null
> +++ b/include/configs/socfpga_stratix10_socdk.h
> @@ -0,0 +1,216 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
> +#define __CONFIG_SOCFGPA_STRATIX10_H__
> +
> +#include <asm/arch/base_addr_s10.h>
> +
> +/*
> + * U-Boot general configurations
> + */
> +#define CONFIG_SYS_TEXT_BASE           0x1000
> +#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
> +#define CONFIG_LOADADDR                        0x80000
> +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> +#define CONFIG_REMAKE_ELF
> +#define CPU_RELEASE_ADDR               0x80
> +#define CONFIG_SYS_CACHELINE_SIZE      64

Can you trim this file and use socfpga_common.h for alot these defines?

Dinh