From mboxrd@z Thu Jan 1 00:00:00 1970 From: tien.fong.chee at intel.com Date: Fri, 13 Oct 2017 16:08:38 +0800 Subject: [U-Boot] [PATCH v3 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager In-Reply-To: <1507882137-27841-1-git-send-email-tien.fong.chee@intel.com> References: <1507882137-27841-1-git-send-email-tien.fong.chee@intel.com> Message-ID: <1507882137-27841-2-git-send-email-tien.fong.chee@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tien Fong Chee This patch adds description on properties about location of FPGA RBFs are stored, type and functionality of RBF used to configure FPGA. Signed-off-by: Tien Fong Chee --- doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt index 2fd8e7a..47c695b 100644 --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -7,6 +7,14 @@ Required properties: - The second index is for writing FPGA configuration data. - resets : Phandle and reset specifier for the device's reset. - clocks : Clocks used by the device. +- altr,bitstream_periph : FPGA peripheral raw binary file which is used to + initialize FPGA IOs, PLL, IO48 and DDR. +- altr,bitstream_core : FPGA core raw binary file contains FPGA design which is + used to program FPGA CRAM and ERAM. +- altr,bitstream_devpart : Partition of flash device where bitstream files are + stored. + - dev is flash device number, part is + flash device partition. Example: @@ -16,4 +24,7 @@ Example: 0xffcfe400 0x20>; clocks = <&l4_mp_clk>; resets = <&rst FPGAMGR_RESET>; + altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage"; + altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage"; + altr,bitstream_devpart = "0:1"; }; -- 2.2.0