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From: Gerd Hoffmann <kraxel@redhat.com>
Date: Fri, 20 Oct 2017 08:55:25 +0200
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Subject: Re: [Qemu-devel] [PATCH] hw/pci-host: Fix x86 Host Bridges 64bit
 PCI hole
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To: Marcel Apfelbaum <marcel@redhat.com>, Laszlo Ersek <lersek@redhat.com>, qemu-devel@nongnu.org
Cc: mst@redhat.com, pbonzini@redhat.com, ehabkost@redhat.com, Igor Mammedov <imammedo@redhat.com>, "Dr. David Alan Gilbert" <dgilbert@redhat.com>

  Hi,

> > commit message says:
> >=20
> > <quote>
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0It turns out that some 32 bit windows g=
uests crash
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if 64 bit PCI hole size is >2G.
> > </quote>
> >=20
> > Why this suddenly isn't a problem any more?
> >=20
>=20
> I suppose it is, so we need a way to turn it "off".

Or have machine types behave differently, i.e. give q35 a large 64bit
hole and leave pc as-is.

Devices with that large bars are most likely pci express anyway ...

> This is how I started, however Eduardo and (and maybe Michael ?)
> where against letting the upper management software to deal with
> such a low low level detail. They simply can't take such a decision.
> This is why the property you mentioned is not ever linked
> in code anywhere! It is simply not implemented and not used.

Makes sense.

BTW:  Is it safe to just assume 40 bits physical is going to work?  My
workstation:

model name=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0: Intel(R) Core(TM) i7-7700=
K CPU @ 4.20GHz
address sizes=C2=A0=C2=A0=C2=A0: 39 bits physical, 48 bits virtual

Does this imply ept is limited 39 bits physical too?

cheers,
  Gerd