From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matan Azrad Subject: [PATCH v3 1/7] net/mlx4: remove error flows from Tx fast path Date: Mon, 30 Oct 2017 10:07:23 +0000 Message-ID: <1509358049-18854-2-git-send-email-matan@mellanox.com> References: <1508768520-4810-1-git-send-email-ophirmu@mellanox.com> <1509358049-18854-1-git-send-email-matan@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain Cc: dev@dpdk.org, Ophir Munk To: Adrien Mazarguil Return-path: Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-eopbgr10089.outbound.protection.outlook.com [40.107.1.89]) by dpdk.org (Postfix) with ESMTP id C69681B2E5 for ; Mon, 30 Oct 2017 11:07:59 +0100 (CET) In-Reply-To: <1509358049-18854-1-git-send-email-matan@mellanox.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Move unnecessary error flows to DEBUG mode. Signed-off-by: Matan Azrad Acked-by: Adrien Mazarguil --- drivers/net/mlx4/mlx4_rxtx.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c index 67dc712..4f899ff 100644 --- a/drivers/net/mlx4/mlx4_rxtx.c +++ b/drivers/net/mlx4/mlx4_rxtx.c @@ -169,6 +169,7 @@ struct pv { * Make sure we read the CQE after we read the ownership bit. */ rte_rmb(); +#ifndef NDEBUG if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_ERROR)) { struct mlx4_err_cqe *cqe_err = @@ -178,6 +179,7 @@ struct pv { (void *)txq, cqe_err->vendor_err, cqe_err->syndrome); } +#endif /* NDEBUG */ /* Get WQE index reported in the CQE. */ new_index = rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask; @@ -322,7 +324,6 @@ struct pv { uint32_t byte_count; int wqe_real_size; int nr_txbbs; - int rc; struct pv *pv = (struct pv *)txq->bounce_buf; int pv_counter = 0; @@ -337,8 +338,7 @@ struct pv { if (((sq->head - sq->tail) + nr_txbbs + sq->headroom_txbbs) >= sq->txbb_cnt || nr_txbbs > MLX4_MAX_WQE_TXBBS) { - rc = ENOSPC; - goto err; + return -ENOSPC; } /* Get the control and data entries of the WQE. */ ctrl = (struct mlx4_wqe_ctrl_seg *)mlx4_get_send_wqe(sq, head_idx); @@ -354,6 +354,7 @@ struct pv { dseg->addr = rte_cpu_to_be_64(addr); /* Memory region key for this memory pool. */ lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf)); +#ifndef NDEBUG if (unlikely(lkey == (uint32_t)-1)) { /* MR does not exist. */ DEBUG("%p: unable to get MP <-> MR association", @@ -366,9 +367,9 @@ struct pv { ctrl->fence_size = (wqe_real_size >> 4) & 0x3f; mlx4_txq_stamp_freed_wqe(sq, head_idx, (sq->head & sq->txbb_cnt) ? 0 : 1); - rc = EFAULT; - goto err; + return -EFAULT; } +#endif /* NDEBUG */ dseg->lkey = rte_cpu_to_be_32(lkey); if (likely(buf->data_len)) { byte_count = rte_cpu_to_be_32(buf->data_len); @@ -471,9 +472,6 @@ struct pv { MLX4_BIT_WQE_OWN : 0)); sq->head += nr_txbbs; return 0; -err: - rte_errno = rc; - return -rc; } /** @@ -510,8 +508,6 @@ struct pv { assert(max <= elts_n); /* Always leave one free entry in the ring. */ --max; - if (max == 0) - return 0; if (max > pkts_n) max = pkts_n; for (i = 0; (i != max); ++i) { -- 1.8.3.1