[PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Gayatri Kammela]

Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
AVX512_BITALG.

CPUID.(EAX=7,ECX=0):ECX[bit 6]  AVX512_VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 8]  GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 9]  VAES
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG

Detailed information of cpuid bits for these features can be found
in the Intel Architecture Instruction Set Extensions and Future Features
Programming Interface document (refer to Table 1-1. and Table 1-2.).
A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=197239

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Ricardo Neri <ricardo.neri@intel.com>
Cc: Yang Zhong <yang.zhong@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
Changes since v1:
1) Rebased against the tip tree and so removed all the setup_clear flags

 arch/x86/include/asm/cpufeatures.h | 6 ++++++
 arch/x86/kernel/cpu/cpuid-deps.c   | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 401a70992060..b0556f882aa8 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,6 +299,12 @@
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_GFNI	(16*32+ 8) /* Galois Field New Instructions */
+#define X86_FEATURE_VAES	(16*32+ 9) /* Vector AES */
+#define X86_FEATURE_VPCLMULQDQ	(16*32+ 10) /* Carry-Less Multiplication Double Quadword */
+#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
+#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
 #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
 #define X86_FEATURE_LA57	(16*32+16) /* 5-level page tables */
 #define X86_FEATURE_RDPID	(16*32+22) /* RDPID instruction */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index c1d49842a411..c21f22d836ad 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -50,6 +50,12 @@ const static struct cpuid_dep cpuid_deps[] = {
 	{ X86_FEATURE_AVX512BW,		X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512VL,		X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512VBMI,	X86_FEATURE_AVX512F   },
+	{ X86_FEATURE_AVX512_VBMI2,	X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_GFNI,		X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_VAES,		X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_VPCLMULQDQ,	X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_AVX512_VNNI,	X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_AVX512_BITALG,	X86_FEATURE_AVX512VL  },
 	{ X86_FEATURE_AVX512_4VNNIW,	X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512_4FMAPS,	X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F   },
-- 
2.7.4

Re: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Borislav Petkov]

On Mon, Oct 30, 2017 at 06:20:29PM -0700, Gayatri Kammela wrote:
> Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
> in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
> AVX512_BITALG.
> 
> CPUID.(EAX=7,ECX=0):ECX[bit 6]  AVX512_VBMI2
> CPUID.(EAX=7,ECX=0):ECX[bit 8]  GFNI
> CPUID.(EAX=7,ECX=0):ECX[bit 9]  VAES
> CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
> CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> 
> Detailed information of cpuid bits for these features can be found
> in the Intel Architecture Instruction Set Extensions and Future Features
> Programming Interface document (refer to Table 1-1. and Table 1-2.).
> A copy of this document is available at
> https://bugzilla.kernel.org/show_bug.cgi?id=197239
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Andi Kleen <andi.kleen@intel.com>
> Cc: Ravi Shankar <ravi.v.shankar@intel.com>
> Cc: Fenghua Yu <fenghua.yu@intel.com>
> Cc: Ricardo Neri <ricardo.neri@intel.com>
> Cc: Yang Zhong <yang.zhong@intel.com>
> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
> ---
> Changes since v1:
> 1) Rebased against the tip tree and so removed all the setup_clear flags
> 
>  arch/x86/include/asm/cpufeatures.h | 6 ++++++
>  arch/x86/kernel/cpu/cpuid-deps.c   | 6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 401a70992060..b0556f882aa8 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -299,6 +299,12 @@
>  #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/

So we have previous AVX512 feature bits which do not separate AVX512
with a "_" but the new ones do. I think we should unify this and the SDM
should be fixed too.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[tip:x86/fpu] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features

[tip-bot for Gayatri Kammela]

Commit-ID:  c128dbfa0f879f8ce7b79054037889b0b2240728
Gitweb:     https://git.kernel.org/tip/c128dbfa0f879f8ce7b79054037889b0b2240728
Author:     Gayatri Kammela <gayatri.kammela@intel.com>
AuthorDate: Mon, 30 Oct 2017 18:20:29 -0700
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 31 Oct 2017 11:02:26 +0100

x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features

Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
AVX512_BITALG.

 CPUID.(EAX=7,ECX=0):ECX[bit 6]  AVX512_VBMI2
 CPUID.(EAX=7,ECX=0):ECX[bit 8]  GFNI
 CPUID.(EAX=7,ECX=0):ECX[bit 9]  VAES
 CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
 CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
 CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG

Detailed information of CPUID bits for these features can be found
in the Intel Architecture Instruction Set Extensions and Future Features
Programming Interface document (refer to Table 1-1. and Table 1-2.).
A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=197239

Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
Cc: Ricardo Neri <ricardo.neri@intel.com>
Cc: Yang Zhong <yang.zhong@intel.com>
Cc: bp@alien8.de
Link: http://lkml.kernel.org/r/1509412829-23380-1-git-send-email-gayatri.kammela@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/cpufeatures.h | 6 ++++++
 arch/x86/kernel/cpu/cpuid-deps.c   | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 401a709..b0556f8 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,6 +299,12 @@
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_GFNI	(16*32+ 8) /* Galois Field New Instructions */
+#define X86_FEATURE_VAES	(16*32+ 9) /* Vector AES */
+#define X86_FEATURE_VPCLMULQDQ	(16*32+ 10) /* Carry-Less Multiplication Double Quadword */
+#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
+#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
 #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
 #define X86_FEATURE_LA57	(16*32+16) /* 5-level page tables */
 #define X86_FEATURE_RDPID	(16*32+22) /* RDPID instruction */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index c1d4984..c21f22d 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -50,6 +50,12 @@ const static struct cpuid_dep cpuid_deps[] = {
 	{ X86_FEATURE_AVX512BW,		X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512VL,		X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512VBMI,	X86_FEATURE_AVX512F   },
+	{ X86_FEATURE_AVX512_VBMI2,	X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_GFNI,		X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_VAES,		X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_VPCLMULQDQ,	X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_AVX512_VNNI,	X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_AVX512_BITALG,	X86_FEATURE_AVX512VL  },
 	{ X86_FEATURE_AVX512_4VNNIW,	X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512_4FMAPS,	X86_FEATURE_AVX512F   },
 	{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F   },

RE: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Yu, Fenghua]

> On Tuesday, October 31, 2017 3:06 AM, Borislav Petkov wrote:
> On Mon, Oct 30, 2017 at 06:20:29PM -0700, Gayatri Kammela wrote:
> >  #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit
> Manipulation instructions*/
> 
> So we have previous AVX512 feature bits which do not separate AVX512
> with a "_" but the new ones do. I think we should unify this and the SDM
> should be fixed too.

This patch exactly follows the names in the spec.

As you said, the legacy code doesn't follow spec naming strictly and the spec doesn't have uniform naming convention either. We are contacting spec author to see if we can follow the same naming convention in the future specs.

Thanks.

-Fenghua

Re: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Borislav Petkov]

On Tue, Oct 31, 2017 at 06:02:53PM +0000, Yu, Fenghua wrote:
> As you said, the legacy code doesn't follow spec naming strictly
> and the spec doesn't have uniform naming convention either. We are
> contacting spec author to see if we can follow the same naming
> convention in the future specs.

Whatever you do, you should change it before it hits mainline because
then it becomes user-space visible. So you can fix the kernel format
first and then concentrate on changing the spec.

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

RE: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Yu, Fenghua]

> On Tuesday, October 31, 2017 11:03 AM, Yu, Fenghua wrote
> > On Tuesday, October 31, 2017 3:06 AM, Borislav Petkov wrote:
> > On Mon, Oct 30, 2017 at 06:20:29PM -0700, Gayatri Kammela wrote:
> > >  #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit
> > Manipulation instructions*/
> >
> > So we have previous AVX512 feature bits which do not separate AVX512
> > with a "_" but the new ones do. I think we should unify this and the
> > SDM should be fixed too.
> 
> This patch exactly follows the names in the spec.
> 
> As you said, the legacy code doesn't follow spec naming strictly and the spec
> doesn't have uniform naming convention either. We are contacting spec
> author to see if we can follow the same naming convention in the future
> specs.

The spec author doesn't want to change the legacy names to insert "_" in order to have uniform names. The "_" in a name is just for readability. So in the future specs, there will be mixed names, some with "_" and some without "_".

We may need to send a patch to fix a few legacy names that don't match exactly specs, e.g. AVX512VBMI as you mentioned.

Thanks.

-Fenghua

Re: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Borislav Petkov]

On Tue, Oct 31, 2017 at 06:25:55PM +0000, Yu, Fenghua wrote:
> We may need to send a patch to fix a few legacy names that don't match
> exactly specs, e.g. AVX512VBMI as you mentioned.

Or we can make them all uniform and ignore the spec. It's not like they
would be harder to grep afterwards.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

RE: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Yu, Fenghua]

> On Tuesday, October 31, 2017 11:33 AM, Borislav Petkov wrote:
> On Tue, Oct 31, 2017 at 06:25:55PM +0000, Yu, Fenghua wrote:
> > We may need to send a patch to fix a few legacy names that don't match
> > exactly specs, e.g. AVX512VBMI as you mentioned.
> 
> Or we can make them all uniform and ignore the spec. It's not like they would
> be harder to grep afterwards.

Should we change the legacy names as well? User apps may use the names already. Changing the names may break the apps.

If we do make all uniform, do you prefer adding "_" after AVX512?

Thanks.

-Fenghua

Re: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Borislav Petkov]

On Tue, Oct 31, 2017 at 07:37:29PM +0000, Yu, Fenghua wrote:
> Should we change the legacy names as well? User apps may use the names
> already. Changing the names may break the apps.

Yeah, we can't do that.

> If we do make all uniform, do you prefer adding "_" after AVX512?

Well, I think we can forget the whole endeavor. We already have the two
variants, which we can't change anymore:

#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
#define X86_FEATURE_AVX512F     ( 9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_AVX512DQ    ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
#define X86_FEATURE_AVX512IFMA  ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
#define X86_FEATURE_AVX512PF    ( 9*32+26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER    ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD    ( 9*32+28) /* AVX-512 Conflict Detection */
#define X86_FEATURE_AVX512BW    ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
#define X86_FEATURE_AVX512VL    ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
#define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */

:-\

Oh well, as long as the AVX512 prefix is there at least the grepping works.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.