From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: [PATCH v5 22/30] arm64/sve: Add prctl controls for userspace vector length management Date: Tue, 31 Oct 2017 15:51:14 +0000 Message-ID: <1509465082-30427-23-git-send-email-Dave.Martin@arm.com> References: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: linux-arm-kernel@lists.infradead.org Cc: linux-arch@vger.kernel.org, Okamoto Takayuki , libc-alpha@sourceware.org, Ard Biesheuvel , Szabolcs Nagy , Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu List-Id: linux-arch.vger.kernel.org VGhpcyBwYXRjaCBhZGRzIHR3byBhcm02NC1zcGVjaWZpYyBwcmN0bHMsIHRvIHBlcm1pdCB1c2Vy c3BhY2UgdG8KY29udHJvbCBpdHMgdmVjdG9yIGxlbmd0aDoKCiAqIFBSX1NWRV9TRVRfVkw6IHNl dCB0aGUgdGhyZWFkJ3MgU1ZFIHZlY3RvciBsZW5ndGggYW5kIHZlY3RvcgogICBsZW5ndGggaW5o ZXJpdGFuY2UgbW9kZS4KCiAqIFBSX1NWRV9HRVRfVkw6IGdldCB0aGUgc2FtZSBpbmZvcm1hdGlv bi4KCkFsdGhvdWdoIHRoZXNlIHByY3RscyByZXNlbWJsZSBpbnN0cnVjdGlvbiBzZXQgZmVhdHVy ZXMgaW4gdGhlIFNWRQphcmNoaXRlY3R1cmUsIHRoZXkgcHJvdmlkZSBhZGRpdGlvbmFsIGNvbnRy b2w6IHRoZSB2ZWN0b3IgbGVuZ3RoCmluaGVyaXRhbmNlIG1vZGUgaXMgTGludXgtc3BlY2lmaWMg YW5kIG5vdGhpbmcgdG8gZG8gd2l0aCB0aGUKYXJjaGl0ZWN0dXJlLCBhbmQgdGhlIGFyY2hpdGVj dHVyZSBkb2VzIG5vdCBwZXJtaXQgRUwwIHRvIHNldCBpdHMKb3duIHZlY3RvciBsZW5ndGggZGly ZWN0bHkuICBCb3RoIGNhbiBiZSB1c2VkIGluIHBvcnRhYmxlIHRvb2xzCndpdGhvdXQgcmVxdWly aW5nIHRoZSB1c2Ugb2YgU1ZFIGluc3RydWN0aW9ucy4KClNpZ25lZC1vZmYtYnk6IERhdmUgTWFy dGluIDxEYXZlLk1hcnRpbkBhcm0uY29tPgpSZXZpZXdlZC1ieTogQ2F0YWxpbiBNYXJpbmFzIDxj YXRhbGluLm1hcmluYXNAYXJtLmNvbT4KQ2M6IEFsZXggQmVubsOpZSA8YWxleC5iZW5uZWVAbGlu YXJvLm9yZz4KCi0tLQoKKipEcm9wcGVkIGF0IHYzKiogUmV2aWV3ZWQtYnk6IEFsZXggQmVubsOp ZSA8YWxleC5iZW5uZWVAbGluYXJvLm9yZz4KU2VlIHYzIHBvc3RpbmcgZm9yIGhpc3RvcnkuCi0t LQogYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9mcHNpbWQuaCAgICB8IDE0ICsrKysrKysrKysrCiBh cmNoL2FybTY0L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oIHwgIDQgKysrCiBhcmNoL2FybTY0L2tl cm5lbC9mcHNpbWQuYyAgICAgICAgIHwgNTAgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysKIGluY2x1ZGUvdWFwaS9saW51eC9wcmN0bC5oICAgICAgICAgfCAgNCArKysKIGtl cm5lbC9zeXMuYyAgICAgICAgICAgICAgICAgICAgICAgfCAxMiArKysrKysrKysKIDUgZmlsZXMg Y2hhbmdlZCwgODQgaW5zZXJ0aW9ucygrKQoKZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVk ZS9hc20vZnBzaW1kLmggYi9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL2Zwc2ltZC5oCmluZGV4IGQ3 NTRlNWEuLmI4Njg0MTIgMTAwNjQ0Ci0tLSBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vZnBzaW1k LmgKKysrIGIvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9mcHNpbWQuaApAQCAtMTcsNiArMTcsNyBA QAogI2RlZmluZSBfX0FTTV9GUF9ICiAKICNpbmNsdWRlIDxhc20vcHRyYWNlLmg+CisjaW5jbHVk ZSA8YXNtL2Vycm5vLmg+CiAKICNpZm5kZWYgX19BU1NFTUJMWV9fCiAKQEAgLTk4LDYgKzk5LDkg QEAgZXh0ZXJuIHZvaWQgc3ZlX3N5bmNfZnJvbV9mcHNpbWRfemVyb3BhZChzdHJ1Y3QgdGFza19z dHJ1Y3QgKnRhc2spOwogZXh0ZXJuIGludCBzdmVfc2V0X3ZlY3Rvcl9sZW5ndGgoc3RydWN0IHRh c2tfc3RydWN0ICp0YXNrLAogCQkJCSB1bnNpZ25lZCBsb25nIHZsLCB1bnNpZ25lZCBsb25nIGZs YWdzKTsKIAorZXh0ZXJuIGludCBzdmVfc2V0X2N1cnJlbnRfdmwodW5zaWduZWQgbG9uZyBhcmcp OworZXh0ZXJuIGludCBzdmVfZ2V0X2N1cnJlbnRfdmwodm9pZCk7CisKIC8qCiAgKiBQcm9iaW5n IGFuZCBzZXR1cCBmdW5jdGlvbnMuCiAgKiBDYWxscyB0byB0aGVzZSBmdW5jdGlvbnMgbXVzdCBi ZSBzZXJpYWxpc2VkIHdpdGggb25lIGFub3RoZXIuCkBAIC0xMTQsNiArMTE4LDE2IEBAIHN0YXRp YyBpbmxpbmUgdm9pZCBmcHNpbWRfcmVsZWFzZV90YXNrKHN0cnVjdCB0YXNrX3N0cnVjdCAqdGFz aykgeyB9CiBzdGF0aWMgaW5saW5lIHZvaWQgc3ZlX3N5bmNfdG9fZnBzaW1kKHN0cnVjdCB0YXNr X3N0cnVjdCAqdGFzaykgeyB9CiBzdGF0aWMgaW5saW5lIHZvaWQgc3ZlX3N5bmNfZnJvbV9mcHNp bWRfemVyb3BhZChzdHJ1Y3QgdGFza19zdHJ1Y3QgKnRhc2spIHsgfQogCitzdGF0aWMgaW5saW5l IGludCBzdmVfc2V0X2N1cnJlbnRfdmwodW5zaWduZWQgbG9uZyBhcmcpCit7CisJcmV0dXJuIC1F SU5WQUw7Cit9CisKK3N0YXRpYyBpbmxpbmUgaW50IHN2ZV9nZXRfY3VycmVudF92bCh2b2lkKQor eworCXJldHVybiAtRUlOVkFMOworfQorCiBzdGF0aWMgaW5saW5lIHZvaWQgc3ZlX2luaXRfdnFf bWFwKHZvaWQpIHsgfQogc3RhdGljIGlubGluZSB2b2lkIHN2ZV91cGRhdGVfdnFfbWFwKHZvaWQp IHsgfQogc3RhdGljIGlubGluZSBpbnQgc3ZlX3ZlcmlmeV92cV9tYXAodm9pZCkgeyByZXR1cm4g MDsgfQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9wcm9jZXNzb3IuaCBiL2Fy Y2gvYXJtNjQvaW5jbHVkZS9hc20vcHJvY2Vzc29yLmgKaW5kZXggYzZmZGRiMC4uMDIzY2FjYiAx MDA2NDQKLS0tIGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9wcm9jZXNzb3IuaAorKysgYi9hcmNo L2FybTY0L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oCkBAIC0yMTcsNSArMjE3LDkgQEAgc3RhdGlj IGlubGluZSB2b2lkIHNwaW5fbG9ja19wcmVmZXRjaChjb25zdCB2b2lkICpwdHIpCiBpbnQgY3B1 X2VuYWJsZV9wYW4odm9pZCAqX191bnVzZWQpOwogaW50IGNwdV9lbmFibGVfY2FjaGVfbWFpbnRf dHJhcCh2b2lkICpfX3VudXNlZCk7CiAKKy8qIFVzZXJzcGFjZSBpbnRlcmZhY2UgZm9yIFBSX1NW RV97U0VULEdFVH1fVkwgcHJjdGwoKXM6ICovCisjZGVmaW5lIFNWRV9TRVRfVkwoYXJnKQlzdmVf c2V0X2N1cnJlbnRfdmwoYXJnKQorI2RlZmluZSBTVkVfR0VUX1ZMKCkJc3ZlX2dldF9jdXJyZW50 X3ZsKCkKKwogI2VuZGlmIC8qIF9fQVNTRU1CTFlfXyAqLwogI2VuZGlmIC8qIF9fQVNNX1BST0NF U1NPUl9IICovCmRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2tlcm5lbC9mcHNpbWQuYyBiL2FyY2gv YXJtNjQva2VybmVsL2Zwc2ltZC5jCmluZGV4IDU3MTU2MjIuLmNiYjJjNjMgMTAwNjQ0Ci0tLSBh L2FyY2gvYXJtNjQva2VybmVsL2Zwc2ltZC5jCisrKyBiL2FyY2gvYXJtNjQva2VybmVsL2Zwc2lt ZC5jCkBAIC0yOSw2ICsyOSw3IEBACiAjaW5jbHVkZSA8bGludXgvaXJxZmxhZ3MuaD4KICNpbmNs dWRlIDxsaW51eC9pbml0Lmg+CiAjaW5jbHVkZSA8bGludXgvcGVyY3B1Lmg+CisjaW5jbHVkZSA8 bGludXgvcHJjdGwuaD4KICNpbmNsdWRlIDxsaW51eC9wcmVlbXB0Lmg+CiAjaW5jbHVkZSA8bGlu dXgvcHJjdGwuaD4KICNpbmNsdWRlIDxsaW51eC9wdHJhY2UuaD4KQEAgLTU1OCw2ICs1NTksNTUg QEAgaW50IHN2ZV9zZXRfdmVjdG9yX2xlbmd0aChzdHJ1Y3QgdGFza19zdHJ1Y3QgKnRhc2ssCiB9 CiAKIC8qCisgKiBFbmNvZGUgdGhlIGN1cnJlbnQgdmVjdG9yIGxlbmd0aCBhbmQgZmxhZ3MgZm9y IHJldHVybi4KKyAqIFRoaXMgaXMgb25seSByZXF1aXJlZCBmb3IgcHJjdGwoKTogcHRyYWNlIGhh cyBzZXBhcmF0ZSBmaWVsZHMKKyAqCisgKiBmbGFncyBhcmUgYXMgZm9yIHN2ZV9zZXRfdmVjdG9y X2xlbmd0aCgpLgorICovCitzdGF0aWMgaW50IHN2ZV9wcmN0bF9zdGF0dXModW5zaWduZWQgbG9u ZyBmbGFncykKK3sKKwlpbnQgcmV0OworCisJaWYgKGZsYWdzICYgUFJfU1ZFX1NFVF9WTF9PTkVY RUMpCisJCXJldCA9IGN1cnJlbnQtPnRocmVhZC5zdmVfdmxfb25leGVjOworCWVsc2UKKwkJcmV0 ID0gY3VycmVudC0+dGhyZWFkLnN2ZV92bDsKKworCWlmICh0ZXN0X3RocmVhZF9mbGFnKFRJRl9T VkVfVkxfSU5IRVJJVCkpCisJCXJldCB8PSBQUl9TVkVfVkxfSU5IRVJJVDsKKworCXJldHVybiBy ZXQ7Cit9CisKKy8qIFBSX1NWRV9TRVRfVkwgKi8KK2ludCBzdmVfc2V0X2N1cnJlbnRfdmwodW5z aWduZWQgbG9uZyBhcmcpCit7CisJdW5zaWduZWQgbG9uZyB2bCwgZmxhZ3M7CisJaW50IHJldDsK KworCXZsID0gYXJnICYgUFJfU1ZFX1ZMX0xFTl9NQVNLOworCWZsYWdzID0gYXJnICYgfnZsOwor CisJaWYgKCFzeXN0ZW1fc3VwcG9ydHNfc3ZlKCkpCisJCXJldHVybiAtRUlOVkFMOworCisJcmV0 ID0gc3ZlX3NldF92ZWN0b3JfbGVuZ3RoKGN1cnJlbnQsIHZsLCBmbGFncyk7CisJaWYgKHJldCkK KwkJcmV0dXJuIHJldDsKKworCXJldHVybiBzdmVfcHJjdGxfc3RhdHVzKGZsYWdzKTsKK30KKwor LyogUFJfU1ZFX0dFVF9WTCAqLworaW50IHN2ZV9nZXRfY3VycmVudF92bCh2b2lkKQoreworCWlm ICghc3lzdGVtX3N1cHBvcnRzX3N2ZSgpKQorCQlyZXR1cm4gLUVJTlZBTDsKKworCXJldHVybiBz dmVfcHJjdGxfc3RhdHVzKDApOworfQorCisvKgogICogQml0bWFwIGZvciB0ZW1wb3Jhcnkgc3Rv cmFnZSBvZiB0aGUgcGVyLUNQVSBzZXQgb2Ygc3VwcG9ydGVkIHZlY3RvciBsZW5ndGhzCiAgKiBk dXJpbmcgc2Vjb25kYXJ5IGJvb3QuCiAgKi8KZGlmZiAtLWdpdCBhL2luY2x1ZGUvdWFwaS9saW51 eC9wcmN0bC5oIGIvaW5jbHVkZS91YXBpL2xpbnV4L3ByY3RsLmgKaW5kZXggMWI2NDkwMS4uMWVm OTM3MCAxMDA2NDQKLS0tIGEvaW5jbHVkZS91YXBpL2xpbnV4L3ByY3RsLmgKKysrIGIvaW5jbHVk ZS91YXBpL2xpbnV4L3ByY3RsLmgKQEAgLTE5OCw3ICsxOTgsMTEgQEAgc3RydWN0IHByY3RsX21t X21hcCB7CiAjIGRlZmluZSBQUl9DQVBfQU1CSUVOVF9DTEVBUl9BTEwJNAogCiAvKiBhcm02NCBT Y2FsYWJsZSBWZWN0b3IgRXh0ZW5zaW9uIGNvbnRyb2xzICovCisvKiBGbGFnIHZhbHVlcyBtdXN0 IGJlIGtlcHQgaW4gc3luYyB3aXRoIHB0cmFjZSBOVF9BUk1fU1ZFIGludGVyZmFjZSAqLworI2Rl ZmluZSBQUl9TVkVfU0VUX1ZMCQkJNDgJLyogc2V0IHRhc2sgdmVjdG9yIGxlbmd0aCAqLwogIyBk ZWZpbmUgUFJfU1ZFX1NFVF9WTF9PTkVYRUMJCSgxIDw8IDE4KSAvKiBkZWZlciBlZmZlY3QgdW50 aWwgZXhlYyAqLworI2RlZmluZSBQUl9TVkVfR0VUX1ZMCQkJNDkJLyogZ2V0IHRhc2sgdmVjdG9y IGxlbmd0aCAqLworLyogQml0cyBjb21tb24gdG8gUFJfU1ZFX1NFVF9WTCBhbmQgUFJfU1ZFX0dF VF9WTCAqLwogIyBkZWZpbmUgUFJfU1ZFX1ZMX0xFTl9NQVNLCQkweGZmZmYKICMgZGVmaW5lIFBS X1NWRV9WTF9JTkhFUklUCQkoMSA8PCAxNykgLyogaW5oZXJpdCBhY3Jvc3MgZXhlYyAqLwogCmRp ZmYgLS1naXQgYS9rZXJuZWwvc3lzLmMgYi9rZXJuZWwvc3lzLmMKaW5kZXggOWFlYmMyOS4uYzU0 MTkxNiAxMDA2NDQKLS0tIGEva2VybmVsL3N5cy5jCisrKyBiL2tlcm5lbC9zeXMuYwpAQCAtMTEw LDYgKzExMCwxMiBAQAogI2lmbmRlZiBTRVRfRlBfTU9ERQogIyBkZWZpbmUgU0VUX0ZQX01PREUo YSxiKQkoLUVJTlZBTCkKICNlbmRpZgorI2lmbmRlZiBTVkVfU0VUX1ZMCisjIGRlZmluZSBTVkVf U0VUX1ZMKGEpCQkoLUVJTlZBTCkKKyNlbmRpZgorI2lmbmRlZiBTVkVfR0VUX1ZMCisjIGRlZmlu ZSBTVkVfR0VUX1ZMKCkJCSgtRUlOVkFMKQorI2VuZGlmCiAKIC8qCiAgKiB0aGlzIGlzIHdoZXJl IHRoZSBzeXN0ZW0td2lkZSBvdmVyZmxvdyBVSUQgYW5kIEdJRCBhcmUgZGVmaW5lZCwgZm9yCkBA IC0yMzg1LDYgKzIzOTEsMTIgQEAgU1lTQ0FMTF9ERUZJTkU1KHByY3RsLCBpbnQsIG9wdGlvbiwg dW5zaWduZWQgbG9uZywgYXJnMiwgdW5zaWduZWQgbG9uZywgYXJnMywKIAljYXNlIFBSX0dFVF9G UF9NT0RFOgogCQllcnJvciA9IEdFVF9GUF9NT0RFKG1lKTsKIAkJYnJlYWs7CisJY2FzZSBQUl9T VkVfU0VUX1ZMOgorCQllcnJvciA9IFNWRV9TRVRfVkwoYXJnMik7CisJCWJyZWFrOworCWNhc2Ug UFJfU1ZFX0dFVF9WTDoKKwkJZXJyb3IgPSBTVkVfR0VUX1ZMKCk7CisJCWJyZWFrOwogCWRlZmF1 bHQ6CiAJCWVycm9yID0gLUVJTlZBTDsKIAkJYnJlYWs7Ci0tIAoyLjEuNAoKX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18Ka3ZtYXJtIG1haWxpbmcgbGlzdApr dm1hcm1AbGlzdHMuY3MuY29sdW1iaWEuZWR1Cmh0dHBzOi8vbGlzdHMuY3MuY29sdW1iaWEuZWR1 L21haWxtYW4vbGlzdGluZm8va3ZtYXJtCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:37824 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753819AbdJaPwO (ORCPT ); Tue, 31 Oct 2017 11:52:14 -0400 From: Dave Martin Subject: [PATCH v5 22/30] arm64/sve: Add prctl controls for userspace vector length management Date: Tue, 31 Oct 2017 15:51:14 +0000 Message-ID: <1509465082-30427-23-git-send-email-Dave.Martin@arm.com> In-Reply-To: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> References: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Ard Biesheuvel , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Szabolcs Nagy , Okamoto Takayuki , kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Message-ID: <20171031155114.U54Aqx8STdZHGq9iNdqiyRdBkNe-VUuf_bCJyP_zSPk@z> This patch adds two arm64-specific prctls, to permit userspace to control its vector length: * PR_SVE_SET_VL: set the thread's SVE vector length and vector length inheritance mode. * PR_SVE_GET_VL: get the same information. Although these prctls resemble instruction set features in the SVE architecture, they provide additional control: the vector length inheritance mode is Linux-specific and nothing to do with the architecture, and the architecture does not permit EL0 to set its own vector length directly. Both can be used in portable tools without requiring the use of SVE instructions. Signed-off-by: Dave Martin Reviewed-by: Catalin Marinas Cc: Alex Bennée --- **Dropped at v3** Reviewed-by: Alex Bennée See v3 posting for history. --- arch/arm64/include/asm/fpsimd.h | 14 +++++++++++ arch/arm64/include/asm/processor.h | 4 +++ arch/arm64/kernel/fpsimd.c | 50 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/prctl.h | 4 +++ kernel/sys.c | 12 +++++++++ 5 files changed, 84 insertions(+) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index d754e5a..b868412 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -17,6 +17,7 @@ #define __ASM_FP_H #include +#include #ifndef __ASSEMBLY__ @@ -98,6 +99,9 @@ extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task); extern int sve_set_vector_length(struct task_struct *task, unsigned long vl, unsigned long flags); +extern int sve_set_current_vl(unsigned long arg); +extern int sve_get_current_vl(void); + /* * Probing and setup functions. * Calls to these functions must be serialised with one another. @@ -114,6 +118,16 @@ static inline void fpsimd_release_task(struct task_struct *task) { } static inline void sve_sync_to_fpsimd(struct task_struct *task) { } static inline void sve_sync_from_fpsimd_zeropad(struct task_struct *task) { } +static inline int sve_set_current_vl(unsigned long arg) +{ + return -EINVAL; +} + +static inline int sve_get_current_vl(void) +{ + return -EINVAL; +} + static inline void sve_init_vq_map(void) { } static inline void sve_update_vq_map(void) { } static inline int sve_verify_vq_map(void) { return 0; } diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index c6fddb0..023cacb 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -217,5 +217,9 @@ static inline void spin_lock_prefetch(const void *ptr) int cpu_enable_pan(void *__unused); int cpu_enable_cache_maint_trap(void *__unused); +/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ +#define SVE_SET_VL(arg) sve_set_current_vl(arg) +#define SVE_GET_VL() sve_get_current_vl() + #endif /* __ASSEMBLY__ */ #endif /* __ASM_PROCESSOR_H */ diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 5715622..cbb2c63 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -558,6 +559,55 @@ int sve_set_vector_length(struct task_struct *task, } /* + * Encode the current vector length and flags for return. + * This is only required for prctl(): ptrace has separate fields + * + * flags are as for sve_set_vector_length(). + */ +static int sve_prctl_status(unsigned long flags) +{ + int ret; + + if (flags & PR_SVE_SET_VL_ONEXEC) + ret = current->thread.sve_vl_onexec; + else + ret = current->thread.sve_vl; + + if (test_thread_flag(TIF_SVE_VL_INHERIT)) + ret |= PR_SVE_VL_INHERIT; + + return ret; +} + +/* PR_SVE_SET_VL */ +int sve_set_current_vl(unsigned long arg) +{ + unsigned long vl, flags; + int ret; + + vl = arg & PR_SVE_VL_LEN_MASK; + flags = arg & ~vl; + + if (!system_supports_sve()) + return -EINVAL; + + ret = sve_set_vector_length(current, vl, flags); + if (ret) + return ret; + + return sve_prctl_status(flags); +} + +/* PR_SVE_GET_VL */ +int sve_get_current_vl(void) +{ + if (!system_supports_sve()) + return -EINVAL; + + return sve_prctl_status(0); +} + +/* * Bitmap for temporary storage of the per-CPU set of supported vector lengths * during secondary boot. */ diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 1b64901..1ef9370 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -198,7 +198,11 @@ struct prctl_mm_map { # define PR_CAP_AMBIENT_CLEAR_ALL 4 /* arm64 Scalable Vector Extension controls */ +/* Flag values must be kept in sync with ptrace NT_ARM_SVE interface */ +#define PR_SVE_SET_VL 48 /* set task vector length */ # define PR_SVE_SET_VL_ONEXEC (1 << 18) /* defer effect until exec */ +#define PR_SVE_GET_VL 49 /* get task vector length */ +/* Bits common to PR_SVE_SET_VL and PR_SVE_GET_VL */ # define PR_SVE_VL_LEN_MASK 0xffff # define PR_SVE_VL_INHERIT (1 << 17) /* inherit across exec */ diff --git a/kernel/sys.c b/kernel/sys.c index 9aebc29..c541916 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -110,6 +110,12 @@ #ifndef SET_FP_MODE # define SET_FP_MODE(a,b) (-EINVAL) #endif +#ifndef SVE_SET_VL +# define SVE_SET_VL(a) (-EINVAL) +#endif +#ifndef SVE_GET_VL +# define SVE_GET_VL() (-EINVAL) +#endif /* * this is where the system-wide overflow UID and GID are defined, for @@ -2385,6 +2391,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, case PR_GET_FP_MODE: error = GET_FP_MODE(me); break; + case PR_SVE_SET_VL: + error = SVE_SET_VL(arg2); + break; + case PR_SVE_GET_VL: + error = SVE_GET_VL(); + break; default: error = -EINVAL; break; -- 2.1.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave.Martin@arm.com (Dave Martin) Date: Tue, 31 Oct 2017 15:51:14 +0000 Subject: [PATCH v5 22/30] arm64/sve: Add prctl controls for userspace vector length management In-Reply-To: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> References: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> Message-ID: <1509465082-30427-23-git-send-email-Dave.Martin@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds two arm64-specific prctls, to permit userspace to control its vector length: * PR_SVE_SET_VL: set the thread's SVE vector length and vector length inheritance mode. * PR_SVE_GET_VL: get the same information. Although these prctls resemble instruction set features in the SVE architecture, they provide additional control: the vector length inheritance mode is Linux-specific and nothing to do with the architecture, and the architecture does not permit EL0 to set its own vector length directly. Both can be used in portable tools without requiring the use of SVE instructions. Signed-off-by: Dave Martin Reviewed-by: Catalin Marinas Cc: Alex Benn?e --- **Dropped at v3** Reviewed-by: Alex Benn?e See v3 posting for history. --- arch/arm64/include/asm/fpsimd.h | 14 +++++++++++ arch/arm64/include/asm/processor.h | 4 +++ arch/arm64/kernel/fpsimd.c | 50 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/prctl.h | 4 +++ kernel/sys.c | 12 +++++++++ 5 files changed, 84 insertions(+) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index d754e5a..b868412 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -17,6 +17,7 @@ #define __ASM_FP_H #include +#include #ifndef __ASSEMBLY__ @@ -98,6 +99,9 @@ extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task); extern int sve_set_vector_length(struct task_struct *task, unsigned long vl, unsigned long flags); +extern int sve_set_current_vl(unsigned long arg); +extern int sve_get_current_vl(void); + /* * Probing and setup functions. * Calls to these functions must be serialised with one another. @@ -114,6 +118,16 @@ static inline void fpsimd_release_task(struct task_struct *task) { } static inline void sve_sync_to_fpsimd(struct task_struct *task) { } static inline void sve_sync_from_fpsimd_zeropad(struct task_struct *task) { } +static inline int sve_set_current_vl(unsigned long arg) +{ + return -EINVAL; +} + +static inline int sve_get_current_vl(void) +{ + return -EINVAL; +} + static inline void sve_init_vq_map(void) { } static inline void sve_update_vq_map(void) { } static inline int sve_verify_vq_map(void) { return 0; } diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index c6fddb0..023cacb 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -217,5 +217,9 @@ static inline void spin_lock_prefetch(const void *ptr) int cpu_enable_pan(void *__unused); int cpu_enable_cache_maint_trap(void *__unused); +/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ +#define SVE_SET_VL(arg) sve_set_current_vl(arg) +#define SVE_GET_VL() sve_get_current_vl() + #endif /* __ASSEMBLY__ */ #endif /* __ASM_PROCESSOR_H */ diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 5715622..cbb2c63 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -558,6 +559,55 @@ int sve_set_vector_length(struct task_struct *task, } /* + * Encode the current vector length and flags for return. + * This is only required for prctl(): ptrace has separate fields + * + * flags are as for sve_set_vector_length(). + */ +static int sve_prctl_status(unsigned long flags) +{ + int ret; + + if (flags & PR_SVE_SET_VL_ONEXEC) + ret = current->thread.sve_vl_onexec; + else + ret = current->thread.sve_vl; + + if (test_thread_flag(TIF_SVE_VL_INHERIT)) + ret |= PR_SVE_VL_INHERIT; + + return ret; +} + +/* PR_SVE_SET_VL */ +int sve_set_current_vl(unsigned long arg) +{ + unsigned long vl, flags; + int ret; + + vl = arg & PR_SVE_VL_LEN_MASK; + flags = arg & ~vl; + + if (!system_supports_sve()) + return -EINVAL; + + ret = sve_set_vector_length(current, vl, flags); + if (ret) + return ret; + + return sve_prctl_status(flags); +} + +/* PR_SVE_GET_VL */ +int sve_get_current_vl(void) +{ + if (!system_supports_sve()) + return -EINVAL; + + return sve_prctl_status(0); +} + +/* * Bitmap for temporary storage of the per-CPU set of supported vector lengths * during secondary boot. */ diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 1b64901..1ef9370 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -198,7 +198,11 @@ struct prctl_mm_map { # define PR_CAP_AMBIENT_CLEAR_ALL 4 /* arm64 Scalable Vector Extension controls */ +/* Flag values must be kept in sync with ptrace NT_ARM_SVE interface */ +#define PR_SVE_SET_VL 48 /* set task vector length */ # define PR_SVE_SET_VL_ONEXEC (1 << 18) /* defer effect until exec */ +#define PR_SVE_GET_VL 49 /* get task vector length */ +/* Bits common to PR_SVE_SET_VL and PR_SVE_GET_VL */ # define PR_SVE_VL_LEN_MASK 0xffff # define PR_SVE_VL_INHERIT (1 << 17) /* inherit across exec */ diff --git a/kernel/sys.c b/kernel/sys.c index 9aebc29..c541916 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -110,6 +110,12 @@ #ifndef SET_FP_MODE # define SET_FP_MODE(a,b) (-EINVAL) #endif +#ifndef SVE_SET_VL +# define SVE_SET_VL(a) (-EINVAL) +#endif +#ifndef SVE_GET_VL +# define SVE_GET_VL() (-EINVAL) +#endif /* * this is where the system-wide overflow UID and GID are defined, for @@ -2385,6 +2391,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, case PR_GET_FP_MODE: error = GET_FP_MODE(me); break; + case PR_SVE_SET_VL: + error = SVE_SET_VL(arg2); + break; + case PR_SVE_GET_VL: + error = SVE_GET_VL(); + break; default: error = -EINVAL; break; -- 2.1.4