[PATCH v2 0/2] Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

[PATCH v2 0/2] Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

[Vikas C Sajjan]

The platforms which support only IOAPIC mode and whose SCI INT is
greater than 16, passes SCI INT via FADT and not via MADT int src override
structure. In such cases current logic fails to handle it and throws error
"Invalid bus_irq %u for legacy override". This patch handles the above
 mentioned case. While at it, also modify function mp_override_legacy_irq()
to use the newly introduced function mp_register_ioapic_irq().

This series is rebased on 'master' branch of
https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git

Changes since v1:
Patch is split into 2, separating actual fix and code cleanup
as suggested by Rafael.

Vikas C Sajjan (2):
  acpi/x86: Fix improper handling of SCI INT for platforms supporting
    only IOAPIC mode
  acpi/x86: Reuse the mp_register_ioapic_irq() in the function
    mp_override_legacy_irq()

 arch/x86/kernel/acpi/boot.c | 64 +++++++++++++++++++++++++++++----------------
 1 file changed, 41 insertions(+), 23 deletions(-)

-- 
1.9.1

[PATCH v2 1/2] acpi/x86: Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

[Vikas C Sajjan]

The platforms which support only IOAPIC mode and whose SCI INT is
greater than 16, passes SCI INT via FADT and not via MADT int src override
structure. In such cases current logic fails to handle it and throws error
"Invalid bus_irq %u for legacy override". This patch fixes it.

Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
Signed-off-by: Sunil V L <sunil.vl@hpe.com>
Signed-off-by: Abdul Lateef Attar <abdul-lateef.attar@hpe.com>
---
 arch/x86/kernel/acpi/boot.c | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index ef9e02e..40c24d1b 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -429,6 +429,37 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
 	return 0;
 }
 
+static int __init mp_register_ioapic_irq(u8 bus_irq, u8 polarity,
+						u8 trigger, u32 gsi)
+{
+	int ioapic;
+	int pin;
+	struct mpc_intsrc mp_irq;
+
+	/*
+	 * Convert 'gsi' to 'ioapic.pin'.
+	 */
+	ioapic = mp_find_ioapic(gsi);
+	if (ioapic < 0) {
+		pr_warn("Failed to find ioapic for gsi : %u\n", gsi);
+		return ioapic;
+	}
+
+	pin = mp_find_ioapic_pin(ioapic, gsi);
+
+	mp_irq.type = MP_INTSRC;
+	mp_irq.irqtype = mp_INT;
+	mp_irq.irqflag = (trigger << 2) | polarity;
+	mp_irq.srcbus = MP_ISA_BUS;
+	mp_irq.srcbusirq = bus_irq;	/* IRQ */
+	mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
+	mp_irq.dstirq = pin;	/* INTIN# */
+
+	mp_save_irq(&mp_irq);
+
+	return 0;
+}
+
 static int __init
 acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)
 {
@@ -473,7 +504,11 @@ static void __init acpi_sci_ioapic_setup(u8 bus_irq, u16 polarity, u16 trigger,
 	if (acpi_sci_flags & ACPI_MADT_POLARITY_MASK)
 		polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK;
 
-	mp_override_legacy_irq(bus_irq, polarity, trigger, gsi);
+	if (bus_irq < NR_IRQS_LEGACY)
+		mp_override_legacy_irq(bus_irq, polarity, trigger, gsi);
+	else
+		mp_register_ioapic_irq(bus_irq, polarity, trigger, gsi);
+
 	acpi_penalize_sci_irq(bus_irq, trigger, polarity);
 
 	/*
-- 
1.9.1

[PATCH v2 2/2] acpi/x86: Reuse the mp_register_ioapic_irq() in the function mp_override_legacy_irq()

[Vikas C Sajjan]

Modify the function mp_override_legacy_irq() to reuse the newly introduced
function mp_register_ioapic_irq().

Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
---
 arch/x86/kernel/acpi/boot.c | 27 +++++----------------------
 1 file changed, 5 insertions(+), 22 deletions(-)

diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 40c24d1b..6aae067 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -342,13 +342,12 @@ static int acpi_register_lapic(int id, u32 acpiid, u8 enabled)
 #ifdef CONFIG_X86_IO_APIC
 #define MP_ISA_BUS		0
 
+static int __init mp_register_ioapic_irq(u8 bus_irq, u8 polarity,
+						u8 trigger, u32 gsi);
+
 static void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
 					  u32 gsi)
 {
-	int ioapic;
-	int pin;
-	struct mpc_intsrc mp_irq;
-
 	/*
 	 * Check bus_irq boundary.
 	 */
@@ -358,14 +357,6 @@ static void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
 	}
 
 	/*
-	 * Convert 'gsi' to 'ioapic.pin'.
-	 */
-	ioapic = mp_find_ioapic(gsi);
-	if (ioapic < 0)
-		return;
-	pin = mp_find_ioapic_pin(ioapic, gsi);
-
-	/*
 	 * TBD: This check is for faulty timer entries, where the override
 	 *      erroneously sets the trigger to level, resulting in a HUGE
 	 *      increase of timer interrupts!
@@ -373,16 +364,8 @@ static void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
 	if ((bus_irq == 0) && (trigger == 3))
 		trigger = 1;
 
-	mp_irq.type = MP_INTSRC;
-	mp_irq.irqtype = mp_INT;
-	mp_irq.irqflag = (trigger << 2) | polarity;
-	mp_irq.srcbus = MP_ISA_BUS;
-	mp_irq.srcbusirq = bus_irq;	/* IRQ */
-	mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
-	mp_irq.dstirq = pin;	/* INTIN# */
-
-	mp_save_irq(&mp_irq);
-
+	if (mp_register_ioapic_irq(bus_irq, polarity, trigger, gsi) < 0)
+		return;
 	/*
 	 * Reset default identity mapping if gsi is also an legacy IRQ,
 	 * otherwise there will be more than one entry with the same GSI
-- 
1.9.1

Re: [PATCH v2 1/2] acpi/x86: Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

[Thomas Gleixner]

On Thu, 16 Nov 2017, Vikas C Sajjan wrote:

Thanks for splitting this up.

> The platforms which support only IOAPIC mode and whose SCI INT is
> greater than 16, passes SCI INT via FADT and not via MADT int src override

greater? I think that's >= 16 because the legacy space is 0-15

> structure. In such cases current logic fails to handle it and throws error
> "Invalid bus_irq %u for legacy override".

Up to this point the changelog is informative. It just lacks the
information WHY the current logic fails to handle it.

> This patch fixes it.

This part is completely useless. You should at least explain the concept of
the fix, not the details (they can be seen from the code).

Let me give you an example:

 Platforms which support only IOAPIC mode pass the SCI information of
 interrupts above the legacy space (0-15) via the FADT mechanism and not
 via MADT, i.e. the table parser ends up calling acpi_sci_ioapic_setup().

 acpi_sci_ioapic_setup() uses mp_override_legacy_irq() to register SCI
 interrupts, which fails for interrupts >= 16, because it only handles
 interrupts 0-15.

 Provide a separate function to handle SCI interrupts >= 16 and invoke it
 conditional in acpi_sci_ioapic_setup().

 This creates some code duplication, which will be cleaned up in a separate
 patch.

See?
 
> Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
> Signed-off-by: Sunil V L <sunil.vl@hpe.com>
> Signed-off-by: Abdul Lateef Attar <abdul-lateef.attar@hpe.com>

This Signed-off-by chain is broken. It says:

     Vikas wrote the patch and handed it to Sunil
     Sunil handed it to Abdul
     Abdul sent it to lkml

Which is obviously not the case.

> ---
>  arch/x86/kernel/acpi/boot.c | 37 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
> index ef9e02e..40c24d1b 100644
> --- a/arch/x86/kernel/acpi/boot.c
> +++ b/arch/x86/kernel/acpi/boot.c
> @@ -429,6 +429,37 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
>  	return 0;
>  }
>  
> +static int __init mp_register_ioapic_irq(u8 bus_irq, u8 polarity,
> +						u8 trigger, u32 gsi)
> +{
> +	int ioapic;
> +	int pin;
> +	struct mpc_intsrc mp_irq;

I know you copied that, but please get rid of the extra line and sort the
variables in reverse fir tree fashion, i.e.:

	struct mpc_intsrc mp_irq;
	int ioapic, pin;

That takes less space and is better to read/parse.

> +
> +	/*
> +	 * Convert 'gsi' to 'ioapic.pin'.
> +	 */

Please make this a one line comment. It's useful, but not that important to
stand out.

> +	ioapic = mp_find_ioapic(gsi);
> +	if (ioapic < 0) {
> +		pr_warn("Failed to find ioapic for gsi : %u\n", gsi);
> +		return ioapic;
> +	}
> +
> +	pin = mp_find_ioapic_pin(ioapic, gsi);
> +
> +	mp_irq.type = MP_INTSRC;
> +	mp_irq.irqtype = mp_INT;
> +	mp_irq.irqflag = (trigger << 2) | polarity;
> +	mp_irq.srcbus = MP_ISA_BUS;
> +	mp_irq.srcbusirq = bus_irq;	/* IRQ */

Please get rid of these tail comments. First of all tail comments are
disturbing the reading flow. Secondly these comment have exactly zero value.

> +	mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
> +	mp_irq.dstirq = pin;	/* INTIN# */

except for this one, but that information should go into that other comment
above, i.e.:

       /* Convert 'gsi' to ioapic.pin (INTIN#) */

Other than these more formal nitpicks, the patch is fine.

Thanks,

	tglx

Re: [PATCH v2 2/2] acpi/x86: Reuse the mp_register_ioapic_irq() in the function mp_override_legacy_irq()

[Thomas Gleixner]

On Thu, 16 Nov 2017, Vikas C Sajjan wrote:

> Modify the function mp_override_legacy_irq() to reuse the newly introduced
> function mp_register_ioapic_irq().

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

RE: [PATCH v2 1/2] acpi/x86: Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

[Sajjan, Vikas C]

Thanks for review, Thomas.

-----Original Message-----
From: Thomas Gleixner [mailto:tglx@linutronix.de] 
Sent: Thursday, November 16, 2017 4:35 PM
To: Sajjan, Vikas C <vikas.cha.sajjan@hpe.com>
Cc: rjw@rjwysocki.net; rafael.j.wysocki@intel.com; linux-pm@vger.kernel.org; linux-acpi@vger.kernel.org; linux-kernel@vger.kernel.org; kkamagui@gmail.com; mingo@kernel.org; Lakshminarasimha, Sunil Vishwanathpur <sunil.vl@hpe.com>; Attar, Abdul Lateef <abdul-lateef.attar@hpe.com>
Subject: Re: [PATCH v2 1/2] acpi/x86: Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

On Thu, 16 Nov 2017, Vikas C Sajjan wrote:

Thanks for splitting this up.

> The platforms which support only IOAPIC mode and whose SCI INT is 
> greater than 16, passes SCI INT via FADT and not via MADT int src 
> override

greater? I think that's >= 16 because the legacy space is 0-15

yes, It should be >=16. Will modify it.

> structure. In such cases current logic fails to handle it and throws 
> error "Invalid bus_irq %u for legacy override".

Up to this point the changelog is informative. It just lacks the information WHY the current logic fails to handle it.

> This patch fixes it.

This part is completely useless. You should at least explain the concept of the fix, not the details (they can be seen from the code).

Sure, will remove this part.

Let me give you an example:

 Platforms which support only IOAPIC mode pass the SCI information of  interrupts above the legacy space (0-15) via the FADT mechanism and not  via MADT, i.e. the table parser ends up calling acpi_sci_ioapic_setup().

 acpi_sci_ioapic_setup() uses mp_override_legacy_irq() to register SCI  interrupts, which fails for interrupts >= 16, because it only handles  interrupts 0-15.

 Provide a separate function to handle SCI interrupts >= 16 and invoke it  conditional in acpi_sci_ioapic_setup().

 This creates some code duplication, which will be cleaned up in a separate  patch.

See?
Thanks for the example. Will give details on why the current logic fails and high level view of the fix.
 
> Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
> Signed-off-by: Sunil V L <sunil.vl@hpe.com>
> Signed-off-by: Abdul Lateef Attar <abdul-lateef.attar@hpe.com>

This Signed-off-by chain is broken. It says:

     Vikas wrote the patch and handed it to Sunil
     Sunil handed it to Abdul
     Abdul sent it to lkml

Which is obviously not the case.
3 of us worked on it, hence I had put all the 3 "Signed-off-by". Are you suggesting to call-out who did what.  Is that what you mean, when you say  "Signed-off-by chain is broken".

> ---
>  arch/x86/kernel/acpi/boot.c | 37 
> ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c 
> index ef9e02e..40c24d1b 100644
> --- a/arch/x86/kernel/acpi/boot.c
> +++ b/arch/x86/kernel/acpi/boot.c
> @@ -429,6 +429,37 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
>  	return 0;
>  }
>  
> +static int __init mp_register_ioapic_irq(u8 bus_irq, u8 polarity,
> +						u8 trigger, u32 gsi)
> +{
> +	int ioapic;
> +	int pin;
> +	struct mpc_intsrc mp_irq;

I know you copied that, but please get rid of the extra line and sort the variables in reverse fir tree fashion, i.e.:

	struct mpc_intsrc mp_irq;
	int ioapic, pin;

That takes less space and is better to read/parse.
Sure, will do.
> +
> +	/*
> +	 * Convert 'gsi' to 'ioapic.pin'.
> +	 */

Please make this a one line comment. It's useful, but not that important to stand out.
OK.

> +	ioapic = mp_find_ioapic(gsi);
> +	if (ioapic < 0) {
> +		pr_warn("Failed to find ioapic for gsi : %u\n", gsi);
> +		return ioapic;
> +	}
> +
> +	pin = mp_find_ioapic_pin(ioapic, gsi);
> +
> +	mp_irq.type = MP_INTSRC;
> +	mp_irq.irqtype = mp_INT;
> +	mp_irq.irqflag = (trigger << 2) | polarity;
> +	mp_irq.srcbus = MP_ISA_BUS;
> +	mp_irq.srcbusirq = bus_irq;	/* IRQ */

Please get rid of these tail comments. First of all tail comments are disturbing the reading flow. Secondly these comment have exactly zero value.
OK.

> +	mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
> +	mp_irq.dstirq = pin;	/* INTIN# */

except for this one, but that information should go into that other comment above, i.e.:

       /* Convert 'gsi' to ioapic.pin (INTIN#) */

Other than these more formal nitpicks, the patch is fine.
Thank you, Thomas.
 
Thanks,

	Tglx

Thanks 
Vikas Sajjan

RE: [PATCH v2 2/2] acpi/x86: Reuse the mp_register_ioapic_irq() in the function mp_override_legacy_irq()

[Sajjan, Vikas C]

-----Original Message-----
From: Thomas Gleixner [mailto:tglx@linutronix.de] 
Sent: Thursday, November 16, 2017 4:35 PM
To: Sajjan, Vikas C <vikas.cha.sajjan@hpe.com>
Cc: rjw@rjwysocki.net; rafael.j.wysocki@intel.com; linux-pm@vger.kernel.org; linux-acpi@vger.kernel.org; linux-kernel@vger.kernel.org; kkamagui@gmail.com; mingo@kernel.org
Subject: Re: [PATCH v2 2/2] acpi/x86: Reuse the mp_register_ioapic_irq() in the function mp_override_legacy_irq()

On Thu, 16 Nov 2017, Vikas C Sajjan wrote:

> Modify the function mp_override_legacy_irq() to reuse the newly 
> introduced function mp_register_ioapic_irq().

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

Thanks.

RE: [PATCH v2 1/2] acpi/x86: Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

[Thomas Gleixner]

On Thu, 16 Nov 2017, Sajjan, Vikas C wrote:
> -----Original Message-----
> From: Thomas Gleixner [mailto:tglx@linutronix.de] 
> Sent: Thursday, November 16, 2017 4:35 PM
> To: Sajjan, Vikas C <vikas.cha.sajjan@hpe.com>
> Cc: rjw@rjwysocki.net; rafael.j.wysocki@intel.com; linux-pm@vger.kernel.org; linux-acpi@vger.kernel.org; linux-kernel@vger.kernel.org; kkamagui@gmail.com; mingo@kernel.org; Lakshminarasimha, Sunil Vishwanathpur <sunil.vl@hpe.com>; Attar, Abdul Lateef <abdul-lateef.attar@hpe.com>
> Subject: Re: [PATCH v2 1/2] acpi/x86: Fix improper handling of SCI INT for platforms supporting only IOAPIC mode

Can you please fix your mail client to not pointlessly copy the full mail
header?

 On Thu, 16 Nov 2017, Thomas Gleixner wrote:

is enough. The rest is in the real mail headers already.

> On Thu, 16 Nov 2017, Vikas C Sajjan wrote:
> > Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
> > Signed-off-by: Sunil V L <sunil.vl@hpe.com>
> > Signed-off-by: Abdul Lateef Attar <abdul-lateef.attar@hpe.com>
> 
> This Signed-off-by chain is broken. It says:
> 
>      Vikas wrote the patch and handed it to Sunil
>      Sunil handed it to Abdul
>      Abdul sent it to lkml
> 
> Which is obviously not the case.

> 3 of us worked on it, hence I had put all the 3 "Signed-off-by". Are you
> suggesting to call-out who did what.  Is that what you mean, when you say
> "Signed-off-by chain is broken".

No. As I explained above. The Signed-off-by is a chain. The first one is
from the author. The following ones are from people who handled,
transported or applied the patch.

See Documentation/process/submitting-patches.rst the chapter:

  Developer's Certificate of Origin 1.1

for further clarification.

Unfortunately we have no canonical way to express joint develoment, but we
have used non formal tags for that, like

     Co-developed-by:

which give credits to the people who were involved in the development.

Thanks,

	tglx