From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sinan Kaya Subject: [PATCH V2 4/7] PCI: wait device ready after pci_pm_reset() Date: Mon, 27 Nov 2017 01:20:25 -0500 Message-ID: <1511763628-11856-5-git-send-email-okaya@codeaurora.org> References: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> Return-path: In-Reply-To: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: linux-pci@vger.kernel.org, timur@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , Bjorn Helgaas , open list List-Id: linux-arm-msm@vger.kernel.org Rev 3.1 Sec 2.3.1 Request Handling Rules says a device can issue CRS following a D3hot->D0 transition. Add pci_dev_wait() call to see if device is available before returning. Signed-off-by: Sinan Kaya --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ed3c3bc..87e4688 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3990,7 +3990,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return 0; + return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); } void pci_reset_secondary_bus(struct pci_dev *dev) -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751231AbdK0GVk (ORCPT ); Mon, 27 Nov 2017 01:21:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:48784 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdK0GUl (ORCPT ); Mon, 27 Nov 2017 01:20:41 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6071A69B2F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , Bjorn Helgaas , linux-kernel@vger.kernel.org (open list) Subject: [PATCH V2 4/7] PCI: wait device ready after pci_pm_reset() Date: Mon, 27 Nov 2017 01:20:25 -0500 Message-Id: <1511763628-11856-5-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> References: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rev 3.1 Sec 2.3.1 Request Handling Rules says a device can issue CRS following a D3hot->D0 transition. Add pci_dev_wait() call to see if device is available before returning. Signed-off-by: Sinan Kaya --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ed3c3bc..87e4688 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3990,7 +3990,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return 0; + return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); } void pci_reset_secondary_bus(struct pci_dev *dev) -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org Subject: [PATCH V2 4/7] PCI: wait device ready after pci_pm_reset() Date: Mon, 27 Nov 2017 01:20:25 -0500 Message-Id: <1511763628-11856-5-git-send-email-okaya@codeaurora.org> In-Reply-To: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> References: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sinan Kaya , linux-arm-msm@vger.kernel.org, Bjorn Helgaas , open list , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: Rev 3.1 Sec 2.3.1 Request Handling Rules says a device can issue CRS following a D3hot->D0 transition. Add pci_dev_wait() call to see if device is available before returning. Signed-off-by: Sinan Kaya --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ed3c3bc..87e4688 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3990,7 +3990,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return 0; + return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); } void pci_reset_secondary_bus(struct pci_dev *dev) -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: okaya@codeaurora.org (Sinan Kaya) Date: Mon, 27 Nov 2017 01:20:25 -0500 Subject: [PATCH V2 4/7] PCI: wait device ready after pci_pm_reset() In-Reply-To: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> References: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> Message-ID: <1511763628-11856-5-git-send-email-okaya@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Rev 3.1 Sec 2.3.1 Request Handling Rules says a device can issue CRS following a D3hot->D0 transition. Add pci_dev_wait() call to see if device is available before returning. Signed-off-by: Sinan Kaya --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ed3c3bc..87e4688 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3990,7 +3990,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return 0; + return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); } void pci_reset_secondary_bus(struct pci_dev *dev) -- 1.9.1