From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Subject: Re: [PATCH] Documentation: binding: Update endianness usage Date: Tue, 05 Dec 2017 14:07:39 -0600 Message-ID: <1512504459.10062.9.camel@buserror.net> References: <1511954855-8593-1-git-send-email-prabhakar.kushwaha@nxp.com> <1512105209.10062.1.camel@buserror.net> <1512165311.10062.3.camel@buserror.net> <1512441957.10062.6.camel@buserror.net> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Prabhakar Kushwaha , "linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" Cc: "dedekind1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" , "computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" List-Id: devicetree@vger.kernel.org On Tue, 2017-12-05 at 09:45 +0000, Prabhakar Kushwaha wrote: > > -----Original Message----- > > From: Scott Wood [mailto:oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org] > > Sent: Tuesday, December 05, 2017 8:16 AM > > To: Prabhakar Kushwaha ; linux- > > mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > > Cc: dedekind1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org > > Subject: Re: [PATCH] Documentation: binding: Update endianness usage > > > > I now see your patch to of_flash_probe... where is the non-IFC-specific > > binding that says the *parent* of a CFI node should be looked at for this? > > Where in general are endian properties kept in the parent of the node with > > "reg"?  The right answer is to add endianness to mtd-physmap.txt. > > > > Flashes are always littler endian.  We wouldn't be having this discussion if that were true... This is about how it presents to the CPU, not about how the actual pins on the chip are numbered. > It is because of IFC controller behavior, endianness is required.   > So as per my understanding, this info should go in IFC binding.  If the info should go in the IFC binding why is the code in a non-IFC-specific place? -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from baldur.buserror.net ([165.227.176.147]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eMJXi-0003IQ-1w for linux-mtd@lists.infradead.org; Tue, 05 Dec 2017 20:10:15 +0000 Message-ID: <1512504459.10062.9.camel@buserror.net> From: Scott Wood To: Prabhakar Kushwaha , "linux-mtd@lists.infradead.org" , "devicetree@vger.kernel.org" Cc: "dedekind1@gmail.com" , "computersforpeace@gmail.com" Date: Tue, 05 Dec 2017 14:07:39 -0600 In-Reply-To: References: <1511954855-8593-1-git-send-email-prabhakar.kushwaha@nxp.com> <1512105209.10062.1.camel@buserror.net> <1512165311.10062.3.camel@buserror.net> <1512441957.10062.6.camel@buserror.net> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: Re: [PATCH] Documentation: binding: Update endianness usage List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 2017-12-05 at 09:45 +0000, Prabhakar Kushwaha wrote: > > -----Original Message----- > > From: Scott Wood [mailto:oss@buserror.net] > > Sent: Tuesday, December 05, 2017 8:16 AM > > To: Prabhakar Kushwaha ; linux- > > mtd@lists.infradead.org; devicetree@vger.kernel.org > > Cc: dedekind1@gmail.com; computersforpeace@gmail.com > > Subject: Re: [PATCH] Documentation: binding: Update endianness usage > > > > I now see your patch to of_flash_probe... where is the non-IFC-specific > > binding that says the *parent* of a CFI node should be looked at for this? > > Where in general are endian properties kept in the parent of the node with > > "reg"?  The right answer is to add endianness to mtd-physmap.txt. > > > > Flashes are always littler endian.  We wouldn't be having this discussion if that were true... This is about how it presents to the CPU, not about how the actual pins on the chip are numbered. > It is because of IFC controller behavior, endianness is required.   > So as per my understanding, this info should go in IFC binding.  If the info should go in the IFC binding why is the code in a non-IFC-specific place? -Scott