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* [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files
@ 2017-12-08 21:41 Jackie Li
  2017-12-08 21:41 ` [PATCH v3 2/5] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (5 more replies)
  0 siblings, 6 replies; 12+ messages in thread
From: Jackie Li @ 2017-12-08 21:41 UTC (permalink / raw)
  To: intel-gfx

intel_guc_reg.h should only include definition for GuC registers
and related register bits. GuC WOPCM related values should not
be defined in intel_guc_reg.h

This patch creates a better file structure by moving GuC WOPCM
related definitions int to a new header intel_guc_wopcm.h
and moving GuC WOPCM related functions to a new source file
intel_guc_wopcm.c

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/Makefile          |  1 +
 drivers/gpu/drm/i915/intel_guc.c       | 11 --------
 drivers/gpu/drm/i915/intel_guc.h       |  2 +-
 drivers/gpu/drm/i915/intel_guc_reg.h   |  3 ---
 drivers/gpu/drm/i915/intel_guc_wopcm.c | 47 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_wopcm.h | 38 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c        |  2 +-
 drivers/gpu/drm/i915/intel_uc_fw.c     |  2 +-
 8 files changed, 89 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 091aef2..1588b2e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -87,6 +87,7 @@ i915-y += intel_uc.o \
 	  intel_guc_fw.o \
 	  intel_guc_log.o \
 	  intel_guc_submission.o \
+	  intel_guc_wopcm.o \
 	  intel_huc.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 177ee69..76519a7 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -370,14 +370,3 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	i915_gem_object_put(obj);
 	return vma;
 }
-
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
-	u32 wopcm_size = GUC_WOPCM_TOP;
-
-	/* On BXT, the top of WOPCM is reserved for RC6 context */
-	if (IS_GEN9_LP(dev_priv))
-		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
-	return wopcm_size;
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 5985672..bfdc887 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
 #include "intel_guc_ct.h"
 #include "intel_guc_log.h"
 #include "intel_guc_reg.h"
+#include "intel_guc_wopcm.h"
 #include "intel_uc_fw.h"
 #include "i915_vma.h"
 
@@ -126,6 +127,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct drm_i915_private *dev_priv);
 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 19a9247..144cd74 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -76,9 +76,6 @@
 
 /* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
-#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
 
 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
 #define GUC_GGTT_TOP			0xFEE00000
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
new file mode 100644
index 0000000..87643a0
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_wopcm.h"
+#include "i915_drv.h"
+
+/*
+ * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
+ * @guc: intel guc.
+ *
+ * Get the platform specific GuC WOPCM size.
+ *
+ * Return: size of the GuC WOPCM.
+ */
+u32 intel_guc_wopcm_size(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	u32 wopcm_size = GUC_WOPCM_TOP;
+
+	/* On BXT, the top of WOPCM is reserved for RC6 context */
+	if (IS_GEN9_LP(i915))
+		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
+
+	return wopcm_size;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
new file mode 100644
index 0000000..04d61c8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _INTEL_GUC_WOPCM_H_
+#define _INTEL_GUC_WOPCM_H_
+
+#include <linux/types.h>
+
+struct intel_guc;
+
+/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
+#define GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
+#define BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
+
+u32 intel_guc_wopcm_size(struct intel_guc *guc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 461047c..44deb80 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -218,7 +218,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	}
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
 		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
 
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 784eff9..24945cf 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -97,7 +97,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 
 	/* Header and uCode will be loaded to WOPCM */
 	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > intel_guc_wopcm_size(dev_priv)) {
+	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
 		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
 			 intel_uc_fw_type_repr(uc_fw->type));
 		err = -E2BIG;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v3 2/5] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
@ 2017-12-08 21:41 ` Jackie Li
  2017-12-08 21:41 ` [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning Jackie Li
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 12+ messages in thread
From: Jackie Li @ 2017-12-08 21:41 UTC (permalink / raw)
  To: intel-gfx

GuC related exported functions should start with "intel_guc_"
prefix and pass intel_guc as the first parameter since its guc
related. Current guc_ggtt_offset() failed to follow this code
convention.

This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset
and updates the related code to pass intel_guc pointer to
this function call. so that we have a unified coding style for
GuC code.

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c            | 12 +++++++-----
 drivers/gpu/drm/i915/intel_guc.h            | 10 ++++++++--
 drivers/gpu/drm/i915/intel_guc_ct.c         |  5 +++--
 drivers/gpu/drm/i915/intel_guc_fw.c         |  2 +-
 drivers/gpu/drm/i915/intel_guc_log.c        |  2 +-
 drivers/gpu/drm/i915/intel_guc_submission.c | 20 ++++++++++----------
 drivers/gpu/drm/i915/intel_huc.c            |  6 ++++--
 7 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 76519a7..41aee96 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -130,8 +130,10 @@ void intel_guc_init_params(struct intel_guc *guc)
 
 	/* If GuC submission is enabled, set up additional parameters here */
 	if (USES_GUC_SUBMISSION(dev_priv)) {
-		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
-		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
+		u32 ads = intel_guc_ggtt_offset(guc,
+						guc->ads_vma) >> PAGE_SHIFT;
+		u32 pgs = intel_guc_ggtt_offset(guc,
+						dev_priv->guc.stage_desc_pool);
 		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
 
 		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
@@ -279,7 +281,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 	data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 	/* any value greater than GUC_POWER_D0 */
 	data[1] = GUC_POWER_D1;
-	data[2] = guc_ggtt_offset(guc->shared_data);
+	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -302,7 +304,7 @@ int intel_guc_reset_engine(struct intel_guc *guc,
 	data[3] = 0;
 	data[4] = 0;
 	data[5] = guc->execbuf_client->stage_id;
-	data[6] = guc_ggtt_offset(guc->shared_data);
+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -324,7 +326,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 
 	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 	data[1] = GUC_POWER_D0;
-	data[2] = guc_ggtt_offset(guc->shared_data);
+	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index bfdc887..399612d 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -101,13 +101,19 @@ static inline void intel_guc_notify(struct intel_guc *guc)
 	guc->notify(guc);
 }
 
-/*
+/* intel_guc_ggtt_offset() - Get the GGTT offset of @vma.
+ * @guc: intel guc.
+ * @vma: i915 graphics virtual memory area.
+ *
  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ *
+ * Return: GGTT offset that meets the GuC gfx address requirement.
  */
-static inline u32 guc_ggtt_offset(struct i915_vma *vma)
+static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
+					struct i915_vma *vma)
 {
 	u32 offset = i915_ggtt_offset(vma);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index 24ad557..0a0d3d5 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -156,7 +156,8 @@ static int ctch_init(struct intel_guc *guc,
 		err = PTR_ERR(blob);
 		goto err_vma;
 	}
-	DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
+	DRM_DEBUG_DRIVER("CT: vma base=%#x\n",
+			 intel_guc_ggtt_offset(guc, ctch->vma));
 
 	/* store pointers to desc and cmds */
 	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
@@ -202,7 +203,7 @@ static int ctch_open(struct intel_guc *guc,
 	}
 
 	/* vma should be already allocated and map'ed */
-	base = guc_ggtt_offset(ctch->vma);
+	base = intel_guc_ggtt_offset(guc, ctch->vma);
 
 	/* (re)initialize descriptors
 	 * cmds buffers are in the second half of the blob page
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index cbc51c9..2369ff7 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -174,7 +174,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
 	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 
 	/* Set the source address for the new blob */
-	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
+	offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 1a2c5ee..41c2529 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -572,7 +572,7 @@ int intel_guc_log_create(struct intel_guc *guc)
 		(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
 		(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
 
-	offset = guc_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
+	offset = intel_guc_ggtt_offset(guc, vma) >> PAGE_SHIFT; /* in pages */
 	guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 912ff14..8bdbe48 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -401,8 +401,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 		lrc->context_desc = lower_32_bits(ce->lrc_desc);
 
 		/* The state page is after PPHWSP */
-		lrc->ring_lrca =
-			guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
+		lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
+				 LRC_STATE_PN * PAGE_SIZE;
 
 		/* XXX: In direct submission, the GuC wants the HW context id
 		 * here. In proxy submission, it wants the stage id
@@ -410,7 +410,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 		lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
 				(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
 
-		lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
+		lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
 		lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
 		lrc->ring_next_free_location = lrc->ring_begin;
 		lrc->ring_current_tail_pointer_value = 0;
@@ -426,7 +426,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 	 * The doorbell, process descriptor, and workqueue are all parts
 	 * of the client object, which the GuC will reference via the GGTT
 	 */
-	gfx_addr = guc_ggtt_offset(client->vma);
+	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
 	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
 				client->doorbell_offset;
 	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
@@ -649,7 +649,7 @@ static void inject_preempt_context(struct work_struct *work)
 	data[3] = engine->guc_id;
 	data[4] = guc->execbuf_client->priority;
 	data[5] = guc->execbuf_client->stage_id;
-	data[6] = guc_ggtt_offset(guc->shared_data);
+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
 		execlists_clear_active(&engine->execlists,
@@ -1139,7 +1139,7 @@ static void guc_policies_init(struct guc_policies *policies)
 static int guc_ads_create(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-	struct i915_vma *vma;
+	struct i915_vma *vma, *rcs_state;
 	struct page *page;
 	/* The ads obj includes the struct itself and buffers passed to GuC */
 	struct {
@@ -1185,9 +1185,9 @@ static int guc_ads_create(struct intel_guc *guc)
 	 * to find it. Note that we have to skip our header (1 page),
 	 * because our GuC shared data is there.
 	 */
-	blob->ads.golden_context_lrca =
-		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
-		skipped_offset;
+	rcs_state = dev_priv->kernel_context->engine[RCS].state;
+	blob->ads.golden_context_lrca = intel_guc_ggtt_offset(guc, rcs_state) +
+					skipped_offset;
 
 	/*
 	 * The GuC expects us to exclude the portion of the context image that
@@ -1199,7 +1199,7 @@ static int guc_ads_create(struct intel_guc *guc)
 		blob->ads.eng_state_size[engine->guc_id] =
 			engine->context_size - skipped_size;
 
-	base = guc_ggtt_offset(vma);
+	base = intel_guc_ggtt_offset(guc, vma);
 	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
 	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
 	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 974be3d..6482174 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -148,7 +148,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* Set the source address for the uCode */
-	offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
+	offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
+		 huc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 
@@ -224,7 +225,8 @@ int intel_huc_auth(struct intel_huc *huc)
 	}
 
 	ret = intel_guc_auth_huc(guc,
-				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
+				 intel_guc_ggtt_offset(guc, vma) +
+				 huc->fw.rsa_offset);
 	if (ret) {
 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 		goto out;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning
  2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
  2017-12-08 21:41 ` [PATCH v3 2/5] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
@ 2017-12-08 21:41 ` Jackie Li
  2017-12-08 21:57   ` Chris Wilson
  2017-12-08 21:41 ` [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL Jackie Li
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 12+ messages in thread
From: Jackie Li @ 2017-12-08 21:41 UTC (permalink / raw)
  To: intel-gfx; +Cc: Sujaritha Sundaresan

Hardware may have specific restrictions on GuC WOPCM partition
size versus HuC firmware size. With static WOPCM partitioning,
there's no way to adjust the GuC WOPCM partition size based on
the actual HuC firmware size, so that GuC/HuC loading failure
would occur even if there was enough WOPCM space for both
GuC and HuC firmware.

This patch enables the dynamic calculation of the WOPCM aperture
sizes used by GuC and HuC firmware. GuC WOPCM offset is set to
HuC size + reserved WOPCM size. GuC WOPCM size is set to
total WOPCM size - GuC WOPCM offset - RC6CTX size. In this case,
GuC WOPCM offset will be updated based on the size of HuC firmware
while GuC WOPCM size will be set to use all the remaining WOPCM space.

v2:
 - Removed intel_wopcm_init (Ville/Sagar/Joonas)
 - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
 - Removed unnecessary function calls (Joonas)
 - Init GuC WOPCM partition as soon as firmware fetching is completed

v3:
 - Fixed indentation issues (Chris)
 - Removed layering violation code (Chris/Michal)
 - Created separat files for GuC wopcm code  (Michal)
 - Used inline function to avoid code duplication (Michal)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |  12 ++--
 drivers/gpu/drm/i915/intel_guc.c        |   4 +-
 drivers/gpu/drm/i915/intel_guc.h        |  12 ++--
 drivers/gpu/drm/i915/intel_guc_wopcm.c  | 102 ++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_guc_wopcm.h  |  25 ++++++--
 drivers/gpu/drm/i915/intel_huc.c        |   2 +-
 drivers/gpu/drm/i915/intel_uc.c         |  39 +++++++++++-
 drivers/gpu/drm/i915/intel_uc_fw.c      |  11 +++-
 drivers/gpu/drm/i915/intel_uc_fw.h      |  16 +++++
 9 files changed, 192 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 21ce374..89ecf2c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,16 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	ctx->desc_template =
 		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
-	 * present or not in use we still need a small bias as ring wraparound
-	 * at offset 0 sometimes hangs. No idea why.
+	/* GuC requires the ring to be placed above GuC WOPCM top. Since GuC
+	 * WOPCM won't be available until intel_uc_init_hw(), we will place
+	 * the context above WOPCM instead if GuC WOPCM wasn't initialized.
+	 * if GuC is not present or not in use we still need a small bias as
+	 * ring wraparound at offset 0 sometimes hangs. No idea why.
 	 */
 	if (USES_GUC(dev_priv))
-		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+		ctx->ggtt_offset_bias = dev_priv->guc.wopcm.valid ?
+			dev_priv->guc.wopcm.top : WOPCM_DEFAULT_SIZE;
+
 	else
 		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
 
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 41aee96..8b830f1 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -339,7 +339,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
  * This is a wrapper to create an object for use with the GuC. In order to
  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
  * both some backing storage and a range inside the Global GTT. We must pin
- * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
+ * it in the GGTT somewhere other than than [0, GuC WOPCM top) because that
  * range is reserved inside GuC.
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
@@ -360,7 +360,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 		goto err;
 
 	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
-			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->wopcm.top);
 	if (ret) {
 		vma = ERR_PTR(ret);
 		goto err;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 399612d..b8248ba 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -49,6 +49,7 @@ struct intel_guc {
 	struct intel_uc_fw fw;
 	struct intel_guc_log log;
 	struct intel_guc_ct ct;
+	struct intel_guc_wopcm wopcm;
 
 	/* Log snapshot if GuC errors during load */
 	struct drm_i915_gem_object *load_err_log;
@@ -105,10 +106,10 @@ static inline void intel_guc_notify(struct intel_guc *guc)
  * @guc: intel guc.
  * @vma: i915 graphics virtual memory area.
  *
- * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
- * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
- * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
- * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ * GuC does not allow any gfx GGTT address that falls into range
+ * [0, GuC WOPCM top), which is reserved for Boot ROM, SRAM and WOPCM.
+ * All gfx objects used by GuC is pinned with PIN_OFFSET_BIAS along with
+ * top of WOPCM.
  *
  * Return: GGTT offset that meets the GuC gfx address requirement.
  */
@@ -117,7 +118,8 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
 	u32 offset = i915_ggtt_offset(vma);
 
-	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
+	GEM_BUG_ON(!guc->wopcm.valid);
+	GEM_BUG_ON(offset < guc->wopcm.top);
 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
 	return offset;
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
index 87643a0..61faf8f 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -25,23 +25,105 @@
 #include "intel_guc_wopcm.h"
 #include "i915_drv.h"
 
+static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	/* On BXT, the top of WOPCM is reserved for RC6 context */
+	if (IS_GEN9_LP(i915))
+		return BXT_WOPCM_RC6_RESERVED;
+
+	return 0;
+}
+
+static inline int gen9_wocpm_size_check(struct drm_i915_private *i915)
+{
+	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
+	u32 wopcm_base;
+	u32 delta;
+
+	/*
+	 * Check hardware restriction on Gen9
+	 * GuC WOPCM size is at least 4 bytes larger than GuC WOPCM base due
+	 * to hardware limitation on Gen9.
+	 */
+	wopcm_base = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
+	if (unlikely(wopcm_base > wopcm->size))
+		return -E2BIG;
+
+	delta = wopcm->size - wopcm_base;
+	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
+		return -E2BIG;
+
+	return 0;
+}
+
+static inline int guc_wopcm_size_check(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	if (IS_GEN9(i915))
+		return gen9_wocpm_size_check(i915);
+
+	return 0;
+}
+
 /*
- * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
+ * intel_guc_wopcm_init() - Initialize the GuC WOPCM partition.
  * @guc: intel guc.
+ * @guc_fw_size: size of GuC firmware.
+ * @huc_fw_size: size of HuC firmware.
  *
- * Get the platform specific GuC WOPCM size.
+ * This function tries to initialize the WOPCM partition based on HuC firmware
+ * size and the reserved WOPCM memory size.
  *
- * Return: size of the GuC WOPCM.
+ * Return: 0 on success, non-zero error code on failure.
  */
-u32 intel_guc_wopcm_size(struct intel_guc *guc)
+int intel_guc_init_wopcm(struct intel_guc *guc, u32 guc_fw_size,
+			 u32 huc_fw_size)
 {
-	struct drm_i915_private *i915 = guc_to_i915(guc);
+	u32 reserved = guc_reserved_wopcm_size(guc);
+	u32 offset, size, top;
+	int err;
 
-	u32 wopcm_size = GUC_WOPCM_TOP;
+	if (!guc_fw_size)
+		return -EINVAL;
 
-	/* On BXT, the top of WOPCM is reserved for RC6 context */
-	if (IS_GEN9_LP(i915))
-		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
+	if (reserved >= WOPCM_DEFAULT_SIZE)
+		return -E2BIG;
+
+	offset = huc_fw_size + WOPCM_RESERVED_SIZE;
+	if (offset >= WOPCM_DEFAULT_SIZE)
+		return -E2BIG;
+
+	/* Hardware requires GuC WOPCM offset needs to be 16K aligned. */
+	offset = ALIGN(offset, WOPCM_OFFSET_ALIGNMENT);
+	if ((offset + reserved) >= WOPCM_DEFAULT_SIZE)
+		return -E2BIG;
+
+	top = WOPCM_DEFAULT_SIZE - offset;
+	size = top - reserved;
+
+	/*
+	 * GuC size needs to be less than or equal to GuC WOPCM size.
+	 * Need extra 8K stack for GuC.
+	 */
+	if ((guc_fw_size + GUC_WOPCM_STACK_RESERVED) > size)
+		return -E2BIG;
+
+	guc->wopcm.offset = offset;
+	guc->wopcm.size = size;
+	guc->wopcm.top = top;
+
+	/* Check platform specific restrictions */
+	err = guc_wopcm_size_check(guc);
+	if (err)
+		return err;
+
+	guc->wopcm.valid = true;
+
+	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
+			 offset >> 10, size >> 10, top >> 10);
 
-	return wopcm_size;
+	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
index 04d61c8..cabf005 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -29,10 +29,27 @@
 
 struct intel_guc;
 
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
-#define BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
+/* Default WOPCM size 1MB */
+#define WOPCM_DEFAULT_SIZE		(0x1 << 20)
+/* Reserved WOPCM size 16KB */
+#define WOPCM_RESERVED_SIZE		(0x4000)
+/* GUC WOPCM Offset need to be 16KB aligned */
+#define WOPCM_OFFSET_ALIGNMENT		(0x4000)
+/* 8KB stack reserved for GuC FW*/
+#define GUC_WOPCM_STACK_RESERVED	(0x2000)
+/* 24KB WOPCM reserved for RC6 CTX on BXT */
+#define BXT_WOPCM_RC6_RESERVED		(0x6000)
 
-u32 intel_guc_wopcm_size(struct intel_guc *guc);
+#define GEN9_GUC_WOPCM_DELTA		4
+#define GEN9_GUC_WOPCM_OFFSET		(0x24000)
+
+struct intel_guc_wopcm {
+	u32 offset;
+	u32 size;
+	u32 top;
+	bool valid;
+};
+
+int intel_guc_init_wopcm(struct intel_guc *guc, u32 guc_size, u32 huc_size);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6482174..dda2955 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -217,7 +217,7 @@ int intel_huc_auth(struct intel_huc *huc)
 		return -ENOEXEC;
 
 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				PIN_OFFSET_BIAS | guc->wopcm.top);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 44deb80..8c4b8ae 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -187,6 +187,37 @@ static void guc_disable_communication(struct intel_guc *guc)
 	guc->send = intel_guc_send_nop;
 }
 
+static int intel_uc_wopcm_partition_init(struct drm_i915_private *i915)
+{
+	struct intel_guc *guc = &i915->guc;
+	struct intel_huc *huc = &i915->huc;
+	u32 guc_fw_size = intel_uc_fw_get_size(&guc->fw);
+	u32 huc_fw_size = intel_uc_fw_get_size(&huc->fw);
+	int err;
+
+	if (guc->wopcm.valid)
+		return 0;
+
+	err = intel_guc_init_wopcm(guc, guc_fw_size, huc_fw_size);
+	if (err) {
+		if (!huc_fw_size)
+			return err;
+
+		huc_fw_size = 0;
+
+		/* Try to enable GuC only */
+		err = intel_guc_init_wopcm(guc, guc_fw_size, 0);
+		if (err)
+			return err;
+	}
+
+	/* Partitioning succeed without HuC */
+	if (!huc_fw_size)
+		intel_uc_fw_fini(&huc->fw);
+
+	return 0;
+}
+
 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
@@ -201,6 +232,10 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		goto err_out;
 	}
 
+	ret = intel_uc_wopcm_partition_init(dev_priv);
+	if (ret)
+		goto err_out;
+
 	guc_disable_communication(guc);
 	gen9_reset_guc_interrupts(dev_priv);
 
@@ -218,9 +253,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	}
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
+	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
-		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
+		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
 
 	/* WaEnableuKernelHeaderValidFix:skl */
 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 24945cf..791263a 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -95,9 +95,13 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
 	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 
-	/* Header and uCode will be loaded to WOPCM */
+	/*
+	 * Header and uCode will be loaded to WOPCM
+	 * Only check the size against the overall available WOPCM here. Will
+	 * continue to check the size during WOPCM partition calculation.
+	 */
 	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
+	if (size > WOPCM_DEFAULT_SIZE) {
 		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
 			 intel_uc_fw_type_repr(uc_fw->type));
 		err = -E2BIG;
@@ -207,6 +211,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 		       int (*xfer)(struct intel_uc_fw *uc_fw,
 				   struct i915_vma *vma))
 {
+	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
 	struct i915_vma *vma;
 	int err;
 
@@ -230,7 +235,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 	}
 
 	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
-				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				       PIN_OFFSET_BIAS | i915->guc.wopcm.top);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..d00d888 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
 	return uc_fw->path != NULL;
 }
 
+/*
+ * intel_uc_fw_get_size() - Get the size of the firmware.
+ * @uc_fw: intel_uc_fw structure.
+ *
+ * Get the size of the firmware that will be placed in WOPCM.
+ *
+ * Return: Zero on invalid firmware status. actual size on success.
+ */
+static inline u32 intel_uc_fw_get_size(struct intel_uc_fw *uc_fw)
+{
+	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
+		return 0;
+
+	return uc_fw->header_size + uc_fw->ucode_size;
+}
+
 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		       struct intel_uc_fw *uc_fw);
 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL
  2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
  2017-12-08 21:41 ` [PATCH v3 2/5] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
  2017-12-08 21:41 ` [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning Jackie Li
@ 2017-12-08 21:41 ` Jackie Li
  2017-12-08 23:03   ` Chris Wilson
  2017-12-08 21:41 ` [PATCH v3 5/5] HAX Enable GuC Submission for CI Jackie Li
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 12+ messages in thread
From: Jackie Li @ 2017-12-08 21:41 UTC (permalink / raw)
  To: intel-gfx

CNL has different WOPCM size and hardware restriction on GuC
WOPCM size.

This patch returns the correct WOPCM reserved size on CNL and
adds the GuC WOPCM size check for CNL.

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_wopcm.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_wopcm.h |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
index 61faf8f..b5d5501 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -33,6 +33,9 @@ static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
 	if (IS_GEN9_LP(i915))
 		return BXT_WOPCM_RC6_RESERVED;
 
+	if (IS_GEN10(i915))
+		return CNL_WOPCM_RESERVED;
+
 	return 0;
 }
 
@@ -58,6 +61,21 @@ static inline int gen9_wocpm_size_check(struct drm_i915_private *i915)
 	return 0;
 }
 
+static inline int cnl_a0_wopcm_size_check(struct drm_i915_private *i915)
+{
+	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
+	u32 huc_size = intel_uc_fw_get_size(&i915->huc.fw);
+
+	/*
+	 * On CNL A0, hardware requires guc size to be larger than or equal to
+	 * HuC kernel size.
+	 */
+	if ((wopcm->size - GEN10_GUC_WOPCM_OFFSET) < huc_size)
+		return -E2BIG;
+
+	return 0;
+}
+
 static inline int guc_wopcm_size_check(struct intel_guc *guc)
 {
 	struct drm_i915_private *i915 = guc_to_i915(guc);
@@ -65,6 +83,9 @@ static inline int guc_wopcm_size_check(struct intel_guc *guc)
 	if (IS_GEN9(i915))
 		return gen9_wocpm_size_check(i915);
 
+	if (IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))
+		return cnl_a0_wopcm_size_check(i915);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
index cabf005..63fa237 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -39,9 +39,12 @@ struct intel_guc;
 #define GUC_WOPCM_STACK_RESERVED	(0x2000)
 /* 24KB WOPCM reserved for RC6 CTX on BXT */
 #define BXT_WOPCM_RC6_RESERVED		(0x6000)
+/* 36KB WOPCM reserved on CNL */
+#define CNL_WOPCM_RESERVED		(0x9000)
 
 #define GEN9_GUC_WOPCM_DELTA		4
 #define GEN9_GUC_WOPCM_OFFSET		(0x24000)
+#define GEN10_GUC_WOPCM_OFFSET		(0x4000)
 
 struct intel_guc_wopcm {
 	u32 offset;
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v3 5/5] HAX Enable GuC Submission for CI
  2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (2 preceding siblings ...)
  2017-12-08 21:41 ` [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL Jackie Li
@ 2017-12-08 21:41 ` Jackie Li
  2017-12-08 22:30 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Patchwork
  2017-12-11  9:31 ` [PATCH v3 1/5] " Joonas Lahtinen
  5 siblings, 0 replies; 12+ messages in thread
From: Jackie Li @ 2017-12-08 21:41 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 792ce26..0ab0733 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, 3) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning
  2017-12-08 21:41 ` [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning Jackie Li
@ 2017-12-08 21:57   ` Chris Wilson
  2017-12-08 22:47     ` Yaodong Li
  0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2017-12-08 21:57 UTC (permalink / raw)
  To: Jackie Li, intel-gfx; +Cc: Sujaritha Sundaresan

Quoting Jackie Li (2017-12-08 21:41:50)
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 21ce374..89ecf2c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -312,12 +312,16 @@ __create_hw_context(struct drm_i915_private *dev_priv,
>         ctx->desc_template =
>                 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>  
> -       /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
> -        * present or not in use we still need a small bias as ring wraparound
> -        * at offset 0 sometimes hangs. No idea why.
> +       /* GuC requires the ring to be placed above GuC WOPCM top. Since GuC
> +        * WOPCM won't be available until intel_uc_init_hw(), we will place
> +        * the context above WOPCM instead if GuC WOPCM wasn't initialized.
> +        * if GuC is not present or not in use we still need a small bias as
> +        * ring wraparound at offset 0 sometimes hangs. No idea why.

So preset it to the worstcase value in early guc init.
-Chris

>          */
>         if (USES_GUC(dev_priv))
> -               ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
> +               ctx->ggtt_offset_bias = dev_priv->guc.wopcm.valid ?
> +                       dev_priv->guc.wopcm.top : WOPCM_DEFAULT_SIZE;
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/guc: Move GuC WOPCM related code into separate files
  2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (3 preceding siblings ...)
  2017-12-08 21:41 ` [PATCH v3 5/5] HAX Enable GuC Submission for CI Jackie Li
@ 2017-12-08 22:30 ` Patchwork
  2017-12-11  9:31 ` [PATCH v3 1/5] " Joonas Lahtinen
  5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-12-08 22:30 UTC (permalink / raw)
  To: Jackie Li; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/5] drm/i915/guc: Move GuC WOPCM related code into separate files
URL   : https://patchwork.freedesktop.org/series/35118/
State : failure

== Summary ==

Series 35118v1 series starting with [v3,1/5] drm/i915/guc: Move GuC WOPCM related code into separate files
https://patchwork.freedesktop.org/api/1.0/series/35118/revisions/1/mbox/

Test core_auth:
        Subgroup basic-auth:
                pass       -> SKIP       (fi-gdg-551)
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                pass       -> SKIP       (fi-elk-e7500)
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
                pass       -> SKIP       (fi-ivb-3520m)
                pass       -> SKIP       (fi-ivb-3770)
                pass       -> SKIP       (fi-byt-j1900)
                pass       -> SKIP       (fi-byt-n2820)
                pass       -> SKIP       (fi-hsw-4770)
                pass       -> SKIP       (fi-hsw-4770r)
                pass       -> SKIP       (fi-bdw-5557u)
                pass       -> SKIP       (fi-bdw-gvtdvm)
                pass       -> SKIP       (fi-bsw-n3050)
Test core_prop_blob:
        Subgroup basic:
                pass       -> SKIP       (fi-gdg-551)
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                pass       -> SKIP       (fi-elk-e7500)
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
                pass       -> SKIP       (fi-ivb-3520m)
                pass       -> SKIP       (fi-ivb-3770)
                pass       -> SKIP       (fi-byt-j1900)
                pass       -> SKIP       (fi-byt-n2820)
                pass       -> SKIP       (fi-hsw-4770)
                pass       -> SKIP       (fi-hsw-4770r)
                pass       -> SKIP       (fi-bdw-5557u)
                pass       -> SKIP       (fi-bdw-gvtdvm)
                pass       -> SKIP       (fi-bsw-n3050)
Test debugfs_test:
        Subgroup read_all_entries:
                pass       -> SKIP       (fi-gdg-551)
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                dmesg-warn -> SKIP       (fi-elk-e7500) fdo#103989 +16
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
                pass       -> SKIP       (fi-ivb-3520m)
                pass       -> SKIP       (fi-ivb-3770)
                pass       -> SKIP       (fi-byt-j1900)
                pass       -> SKIP       (fi-byt-n2820)
                pass       -> SKIP       (fi-hsw-4770)
                pass       -> SKIP       (fi-hsw-4770r)
                pass       -> SKIP       (fi-bdw-5557u)
                pass       -> SKIP       (fi-bdw-gvtdvm) fdo#103938 +1
                pass       -> SKIP       (fi-bsw-n3050)
                pass       -> DMESG-WARN (fi-skl-6260u)
                pass       -> DMESG-WARN (fi-skl-6600u)
                pass       -> DMESG-WARN (fi-skl-6700hq)
                pass       -> DMESG-WARN (fi-skl-6700k)
                pass       -> DMESG-WARN (fi-skl-6770hq)
                pass       -> DMESG-WARN (fi-skl-gvtdvm)
                pass       -> DMESG-WARN (fi-bxt-dsi)
                pass       -> DMESG-WARN (fi-bxt-j4205)
                pass       -> DMESG-WARN (fi-kbl-7500u) fdo#103285
                pass       -> DMESG-WARN (fi-kbl-7560u)
                pass       -> DMESG-WARN (fi-kbl-7567u)
                pass       -> DMESG-WARN (fi-kbl-r)
Test drv_getparams_basic:
        Subgroup basic-eu-total:
                pass       -> SKIP       (fi-gdg-551)
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                pass       -> SKIP       (fi-elk-e7500)
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
                pass       -> SKIP       (fi-ivb-3520m)
                pass       -> SKIP       (fi-ivb-3770)
                pass       -> SKIP       (fi-byt-j1900)
                pass       -> SKIP       (fi-byt-n2820)
                pass       -> SKIP       (fi-hsw-4770)
                pass       -> SKIP       (fi-hsw-4770r)
                pass       -> SKIP       (fi-bdw-5557u)
                pass       -> SKIP       (fi-bdw-gvtdvm)
                pass       -> SKIP       (fi-bsw-n3050)
        Subgroup basic-subslice-total:
                pass       -> SKIP       (fi-gdg-551)
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                pass       -> SKIP       (fi-elk-e7500)
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
WARNING: Long output truncated

06dd422e3209a968c420e10504f75fbbe897f06c drm-tip: 2017y-12m-08d-21h-06m-35s UTC integration manifest
6756c1c5fd37 HAX Enable GuC Submission for CI
92482fca94a1 drm/i915/guc: Add WOPCM partitioning support for CNL
a214f8e23561 drm/i915/guc: Implement dynamic WOPCM partitioning
0e3051c7813e drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
d1a973f3505c drm/i915/guc: Move GuC WOPCM related code into separate files

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7456/issues.html
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning
  2017-12-08 21:57   ` Chris Wilson
@ 2017-12-08 22:47     ` Yaodong Li
  0 siblings, 0 replies; 12+ messages in thread
From: Yaodong Li @ 2017-12-08 22:47 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx; +Cc: Sujaritha Sundaresan

On 12/08/2017 01:57 PM, Chris Wilson wrote:
> Quoting Jackie Li (2017-12-08 21:41:50)
>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
>> index 21ce374..89ecf2c 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> @@ -312,12 +312,16 @@ __create_hw_context(struct drm_i915_private *dev_priv,
>>          ctx->desc_template =
>>                  default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>>   
>> -       /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
>> -        * present or not in use we still need a small bias as ring wraparound
>> -        * at offset 0 sometimes hangs. No idea why.
>> +       /* GuC requires the ring to be placed above GuC WOPCM top. Since GuC
>> +        * WOPCM won't be available until intel_uc_init_hw(), we will place
>> +        * the context above WOPCM instead if GuC WOPCM wasn't initialized.
>> +        * if GuC is not present or not in use we still need a small bias as
>> +        * ring wraparound at offset 0 sometimes hangs. No idea why.
> So preset it to the worstcase value in early guc init.
> -Chris
Thank you very much Chris! This is very helpful. Can you also help to 
review and
comment on the rest of the patch and the other patches in this serial?
Really appreciate your help! :)
>>           */
>>          if (USES_GUC(dev_priv))
>> -               ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
>> +               ctx->ggtt_offset_bias = dev_priv->guc.wopcm.valid ?
>> +                       dev_priv->guc.wopcm.top : WOPCM_DEFAULT_SIZE;

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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL
  2017-12-08 21:41 ` [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL Jackie Li
@ 2017-12-08 23:03   ` Chris Wilson
  2017-12-12  0:16     ` Yaodong Li
  0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2017-12-08 23:03 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2017-12-08 21:41:51)
> +static inline int cnl_a0_wopcm_size_check(struct drm_i915_private *i915)
> +{
> +       struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
> +       u32 huc_size = intel_uc_fw_get_size(&i915->huc.fw);
> +
> +       /*
> +        * On CNL A0, hardware requires guc size to be larger than or equal to
> +        * HuC kernel size.
> +        */

I couldn't find anything that told me that wopcm->size had to be greater
than GEN10_GUC_WOPCM_OFFSET. Either that is always true by construction,
in which case GEM_BUG_ON() here, or it may be too small in which case
add the test.

> +       if ((wopcm->size - GEN10_GUC_WOPCM_OFFSET) < huc_size)

((((Do) you) like) brackets)?
-Chris
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files
  2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (4 preceding siblings ...)
  2017-12-08 22:30 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Patchwork
@ 2017-12-11  9:31 ` Joonas Lahtinen
  5 siblings, 0 replies; 12+ messages in thread
From: Joonas Lahtinen @ 2017-12-11  9:31 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

On Fri, 2017-12-08 at 13:41 -0800, Jackie Li wrote:
> intel_guc_reg.h should only include definition for GuC registers
> and related register bits. GuC WOPCM related values should not
> be defined in intel_guc_reg.h
> 
> This patch creates a better file structure by moving GuC WOPCM
> related definitions int to a new header intel_guc_wopcm.h
> and moving GuC WOPCM related functions to a new source file
> intel_guc_wopcm.c
> 
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Jackie Li <yaodong.li@intel.com>

Please add Cc:s to patches for people who comment on the previous
iterations of the patches.

> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> +u32 intel_guc_wopcm_size(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +
> +	u32 wopcm_size = GUC_WOPCM_TOP;
> +
> +	/* On BXT, the top of WOPCM is reserved for RC6 context */
> +	if (IS_GEN9_LP(i915))
> +		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;

This is still bit confusing. How exactly is WOPCM size different from
the WOPCM top? If the WOPCM is used also by the hardware, when GuC is
disabled, then it should be intel_wopcm_*. If we only need this
information for the single GuC register programming, then I think this
should instead be local to programming that GuC register.

There should be a very clear split in the registers/functions to show
what is specific to the some hardware function and what is more
generic.

If this is all GuC related and only ever needs to be programmed for GuC
as the current naming suggest, then it's a great question why we are
not programming the register according to some firmware reported size
instead of replicating here.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL
  2017-12-08 23:03   ` Chris Wilson
@ 2017-12-12  0:16     ` Yaodong Li
  0 siblings, 0 replies; 12+ messages in thread
From: Yaodong Li @ 2017-12-12  0:16 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

On 12/08/2017 03:03 PM, Chris Wilson wrote:
> Quoting Jackie Li (2017-12-08 21:41:51)
>> +static inline int cnl_a0_wopcm_size_check(struct drm_i915_private *i915)
>> +{
>> +       struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
>> +       u32 huc_size = intel_uc_fw_get_size(&i915->huc.fw);
>> +
>> +       /*
>> +        * On CNL A0, hardware requires guc size to be larger than or equal to
>> +        * HuC kernel size.
>> +        */
> I couldn't find anything that told me that wopcm->size had to be greater
> than GEN10_GUC_WOPCM_OFFSET. Either that is always true by construction,
> in which case GEM_BUG_ON() here, or it may be too small in which case
> add the test.
It's a known HW limitation on CNL A0. And Yes, it should be unlikely to 
happen,
but once it happened, we only want to disable GuC loading and submission.
>> +       if ((wopcm->size - GEN10_GUC_WOPCM_OFFSET) < huc_size)
> ((((Do) you) like) brackets)?
Will Fix it. :-) Thanks!
> -Chris
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v3 5/5] HAX enable GuC submission for CI
  2017-11-03 14:21 [PATCH v3 1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps Michal Wajdeczko
@ 2017-11-03 14:21 ` Michal Wajdeczko
  0 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2017-11-03 14:21 UTC (permalink / raw)
  To: intel-gfx

Also revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions"

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++------
 drivers/gpu/drm/i915/i915_params.h  | 4 ++--
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0684d5d..a351ddf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3562,17 +3562,13 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-	GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
-
 	i915->ggtt.invalidate = guc_ggtt_invalidate;
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
-	/* We should only be called after i915_ggtt_enable_guc() */
-	GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
-
-	i915->ggtt.invalidate = gen6_ggtt_invalidate;
+	if (i915->ggtt.invalidate == guc_ggtt_invalidate)
+		i915->ggtt.invalidate = gen6_ggtt_invalidate;
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index c729226..c38cef0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,8 +44,8 @@
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc_loading, 0) \
-	param(int, enable_guc_submission, 0) \
+	param(int, enable_guc_loading, 1) \
+	param(int, enable_guc_submission, 1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2017-12-12  0:18 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-08 21:41 [PATCH v3 1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
2017-12-08 21:41 ` [PATCH v3 2/5] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
2017-12-08 21:41 ` [PATCH v3 3/5] drm/i915/guc: Implement dynamic WOPCM partitioning Jackie Li
2017-12-08 21:57   ` Chris Wilson
2017-12-08 22:47     ` Yaodong Li
2017-12-08 21:41 ` [PATCH v3 4/5] drm/i915/guc: Add WOPCM partitioning support for CNL Jackie Li
2017-12-08 23:03   ` Chris Wilson
2017-12-12  0:16     ` Yaodong Li
2017-12-08 21:41 ` [PATCH v3 5/5] HAX Enable GuC Submission for CI Jackie Li
2017-12-08 22:30 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/guc: Move GuC WOPCM related code into separate files Patchwork
2017-12-11  9:31 ` [PATCH v3 1/5] " Joonas Lahtinen
  -- strict thread matches above, loose matches on Subject: below --
2017-11-03 14:21 [PATCH v3 1/5] drm/i915/guc: Split GuC firmware xfer function into clear steps Michal Wajdeczko
2017-11-03 14:21 ` [PATCH v3 5/5] HAX enable GuC submission for CI Michal Wajdeczko

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