From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: [RFC PATCH 1/2] platform/x86: add Atom PMC quirk to disable SATA Date: Wed, 13 Dec 2017 21:33:33 +0200 Message-ID: <1513193613.7000.58.camel@linux.intel.com> References: <20170906204237.24x6fzlfmq7jmuce@sig21.net> <20170925191749.2oamusbajgs6clcg@sig21.net> <20170925192109.rty2fnm7c4jnj3vx@sig21.net> <34396652.fljU28PShI@aspire.rjw.lan> <20171213162206.GA7337@sig21.net> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com ([134.134.136.24]:36867 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753197AbdLMTdi (ORCPT ); Wed, 13 Dec 2017 14:33:38 -0500 In-Reply-To: Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: Hans de Goede , Johannes Stezenbach Cc: Michael Turquette , "Rafael J. Wysocki" , Mika Westerberg , Pierre-Louis Bossart , linux-clk , Linux PM list , Carlo Caione , Darren Hart , Enric Balletbo i Serra , Takashi Iwai , ACPI Devel Maling List On Wed, 2017-12-13 at 17:37 +0100, Hans de Goede wrote: > Hi, > > On 13-12-17 17:22, Johannes Stezenbach wrote: > > > > Please don't get confused with the other thread about clocks. > > This issue sets the "disable IP" bit, found by doing stupid > > experiments to enable S0ix on E200HA. > > Ah my bad. Oh, perhaps I also need to refresh my memory from that buglink. > > 1. no idea if Cherry Trail even has SATA IP, maybe this is a > > meaningless bit but PMC firmware carried over from > > Bay Trail looks at it > > > There are no CHT SoCs with SATA AFAIK, but Braswell SoCs, > which I believe is the same die do have SATA. > > I think the best fix here is to look at the model-string part > of the CPU-id and do a quirk based on that, setting the "disable IP" > bit for the SATA on all SoC models known to not have SATA > (Z8300, Z8350, Z8500, Z8550, Z8700, Z8750). > > Rafael, Andy how does that sound as a solution? Yeah, that bit is a property of PMC microcontroller and thus belongs to its driver in Linux kernel. To make it strict we need a matching property. AFAIR CPU model ID is all the same for all CHT and BSW SoCs, so, can't be used to distinguish them. So, you are thinking about comparing CPU model name then? It might work. However, SATA itself is a part of PCH, and thus can not exactly be matched by CPU ID. Btw, Pentium Celeron N-series according to spec has SATA host. -- Andy Shevchenko Intel Finland Oy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-ID: <1513193613.7000.58.camel@linux.intel.com> Subject: Re: [RFC PATCH 1/2] platform/x86: add Atom PMC quirk to disable SATA From: Andy Shevchenko To: Hans de Goede , Johannes Stezenbach Cc: Michael Turquette , "Rafael J. Wysocki" , Mika Westerberg , Pierre-Louis Bossart , linux-clk , Linux PM list , Carlo Caione , Darren Hart , Enric Balletbo i Serra , Takashi Iwai , ACPI Devel Maling List Date: Wed, 13 Dec 2017 21:33:33 +0200 In-Reply-To: References: <20170906204237.24x6fzlfmq7jmuce@sig21.net> <20170925191749.2oamusbajgs6clcg@sig21.net> <20170925192109.rty2fnm7c4jnj3vx@sig21.net> <34396652.fljU28PShI@aspire.rjw.lan> <20171213162206.GA7337@sig21.net> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-ID: On Wed, 2017-12-13 at 17:37 +0100, Hans de Goede wrote: > Hi, > > On 13-12-17 17:22, Johannes Stezenbach wrote: > > > > Please don't get confused with the other thread about clocks. > > This issue sets the "disable IP" bit, found by doing stupid > > experiments to enable S0ix on E200HA. > > Ah my bad. Oh, perhaps I also need to refresh my memory from that buglink. > > 1. no idea if Cherry Trail even has SATA IP, maybe this is a > > meaningless bit but PMC firmware carried over from > > Bay Trail looks at it > > > There are no CHT SoCs with SATA AFAIK, but Braswell SoCs, > which I believe is the same die do have SATA. > > I think the best fix here is to look at the model-string part > of the CPU-id and do a quirk based on that, setting the "disable IP" > bit for the SATA on all SoC models known to not have SATA > (Z8300, Z8350, Z8500, Z8550, Z8700, Z8750). > > Rafael, Andy how does that sound as a solution? Yeah, that bit is a property of PMC microcontroller and thus belongs to its driver in Linux kernel. To make it strict we need a matching property. AFAIR CPU model ID is all the same for all CHT and BSW SoCs, so, can't be used to distinguish them. So, you are thinking about comparing CPU model name then? It might work. However, SATA itself is a part of PCH, and thus can not exactly be matched by CPU ID. Btw, Pentium Celeron N-series according to spec has SATA host. -- Andy Shevchenko Intel Finland Oy