From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ravi Kumar Subject: [PATCH v3 09/19] crypto/ccp: support ccp hwrng feature Date: Wed, 10 Jan 2018 04:42:49 -0500 Message-ID: <1515577379-18453-9-git-send-email-Ravi1.kumar@amd.com> References: <1515145198-97367-1-git-send-email-Ravi1.kumar@amd.com> <1515577379-18453-1-git-send-email-Ravi1.kumar@amd.com> Mime-Version: 1.0 Content-Type: text/plain Cc: pablo.de.lara.guarch@intel.com To: dev@dpdk.org Return-path: Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0066.outbound.protection.outlook.com [104.47.37.66]) by dpdk.org (Postfix) with ESMTP id 61EDB1B231 for ; Wed, 10 Jan 2018 10:43:35 +0100 (CET) In-Reply-To: <1515577379-18453-1-git-send-email-Ravi1.kumar@amd.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Ravi Kumar --- drivers/crypto/ccp/ccp_dev.c | 20 ++++++++++++++++++++ drivers/crypto/ccp/ccp_dev.h | 11 +++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/crypto/ccp/ccp_dev.c b/drivers/crypto/ccp/ccp_dev.c index fee90e3..d8c0ab4 100644 --- a/drivers/crypto/ccp/ccp_dev.c +++ b/drivers/crypto/ccp/ccp_dev.c @@ -88,6 +88,26 @@ ccp_allot_queue(struct rte_cryptodev *cdev, int slot_req) return NULL; } +int +ccp_read_hwrng(uint32_t *value) +{ + struct ccp_device *dev; + + TAILQ_FOREACH(dev, &ccp_list, next) { + void *vaddr = (void *)(dev->pci.mem_resource[2].addr); + + while (dev->hwrng_retries++ < CCP_MAX_TRNG_RETRIES) { + *value = CCP_READ_REG(vaddr, TRNG_OUT_REG); + if (*value) { + dev->hwrng_retries = 0; + return 0; + } + } + dev->hwrng_retries = 0; + } + return -1; +} + static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size, diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h index cfb3b03..a5c9ef3 100644 --- a/drivers/crypto/ccp/ccp_dev.h +++ b/drivers/crypto/ccp/ccp_dev.h @@ -47,6 +47,7 @@ /**< CCP sspecific */ #define MAX_HW_QUEUES 5 +#define CCP_MAX_TRNG_RETRIES 10 /**< CCP Register Mappings */ #define Q_MASK_REG 0x000 @@ -223,6 +224,8 @@ struct ccp_device { /**< protection for shared lsb region allocation */ int qidx; /**< current queue index */ + int hwrng_retries; + /**< retry counter for CCP TRNG */ } __rte_cache_aligned; /**< CCP H/W engine related */ @@ -454,4 +457,12 @@ int ccp_probe_devices(const struct rte_pci_id *ccp_id); */ struct ccp_queue *ccp_allot_queue(struct rte_cryptodev *dev, int slot_req); +/** + * read hwrng value + * + * @param trng_value data pointer to write RNG value + * @return 0 on success otherwise -1 + */ +int ccp_read_hwrng(uint32_t *trng_value); + #endif /* _CCP_DEV_H_ */ -- 2.7.4