From mboxrd@z Thu Jan 1 00:00:00 1970 From: wei.guo.simon@gmail.com Subject: [PATCH 07/26] KVM: PPC: Book3S PR: add TEXASR related macros Date: Thu, 11 Jan 2018 18:11:20 +0800 Message-ID: <1515665499-31710-8-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo To: linuxppc-dev@lists.ozlabs.org Return-path: Received: from mail-pg0-f65.google.com ([74.125.83.65]:40886 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933227AbeAKKMP (ORCPT ); Thu, 11 Jan 2018 05:12:15 -0500 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-owner@vger.kernel.org List-ID: From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/reg.h | 21 ++++++++++++++++++++- arch/powerpc/platforms/powernv/copy-paste.h | 3 +-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b779f3c..6c293bc 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -146,6 +146,12 @@ #define MSR_64BIT 0 #endif +/* Condition Register related */ +#define CR0_SHIFT 28 +#define CR0_MASK 0xF +#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ + + /* Power Management - Processor Stop Status and Control Register Fields */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ @@ -237,8 +243,21 @@ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ -#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ +#define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ +#define TEXASR_PR_LG (63 - 35) /* Privilege level */ +#define TEXASR_FS_LG (63 - 36) /* failure summary */ +#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ +#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ +#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) +#define TEXASR_HV __MASK(TEXASR_HV_LG) +#define TEXASR_PR __MASK(TEXASR_PR_LG) +#define TEXASR_FS __MASK(TEXASR_FS_LG) +#define TEXASR_EX __MASK(TEXASR_EX_LG) +#define TEXASR_ROT __MASK(TEXASR_ROT_LG) + #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ + #define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_CTRLF 0x088 #define SPRN_CTRLT 0x098 diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h index c9a5036..3fa62de 100644 --- a/arch/powerpc/platforms/powernv/copy-paste.h +++ b/arch/powerpc/platforms/powernv/copy-paste.h @@ -7,9 +7,8 @@ * 2 of the License, or (at your option) any later version. */ #include +#include -#define CR0_SHIFT 28 -#define CR0_MASK 0xF /* * Copy/paste instructions: * -- 1.8.3.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: wei.guo.simon@gmail.com Date: Thu, 11 Jan 2018 10:11:20 +0000 Subject: [PATCH 07/26] KVM: PPC: Book3S PR: add TEXASR related macros Message-Id: <1515665499-31710-8-git-send-email-wei.guo.simon@gmail.com> List-Id: References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/reg.h | 21 ++++++++++++++++++++- arch/powerpc/platforms/powernv/copy-paste.h | 3 +-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b779f3c..6c293bc 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -146,6 +146,12 @@ #define MSR_64BIT 0 #endif +/* Condition Register related */ +#define CR0_SHIFT 28 +#define CR0_MASK 0xF +#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ + + /* Power Management - Processor Stop Status and Control Register Fields */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ @@ -237,8 +243,21 @@ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ -#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ +#define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ +#define TEXASR_PR_LG (63 - 35) /* Privilege level */ +#define TEXASR_FS_LG (63 - 36) /* failure summary */ +#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ +#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ +#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) +#define TEXASR_HV __MASK(TEXASR_HV_LG) +#define TEXASR_PR __MASK(TEXASR_PR_LG) +#define TEXASR_FS __MASK(TEXASR_FS_LG) +#define TEXASR_EX __MASK(TEXASR_EX_LG) +#define TEXASR_ROT __MASK(TEXASR_ROT_LG) + #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ + #define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_CTRLF 0x088 #define SPRN_CTRLT 0x098 diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h index c9a5036..3fa62de 100644 --- a/arch/powerpc/platforms/powernv/copy-paste.h +++ b/arch/powerpc/platforms/powernv/copy-paste.h @@ -7,9 +7,8 @@ * 2 of the License, or (at your option) any later version. */ #include +#include -#define CR0_SHIFT 28 -#define CR0_MASK 0xF /* * Copy/paste instructions: * -- 1.8.3.1