From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751545AbeAOS6I (ORCPT + 1 other); Mon, 15 Jan 2018 13:58:08 -0500 Received: from mga11.intel.com ([192.55.52.93]:2465 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751278AbeAOS6H (ORCPT ); Mon, 15 Jan 2018 13:58:07 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,364,1511856000"; d="scan'208";a="11038406" From: kan.liang@intel.com To: tglx@linutronix.de, mingo@redhat.com, peterz@infradead.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, eranian@google.com, ak@linux.intel.com, Kan Liang Subject: [PATCH V5 1/8] perf/x86/intel/uncore: customized event_read for client IMC uncore Date: Mon, 15 Jan 2018 10:57:02 -0800 Message-Id: <1516042629-387021-1-git-send-email-kan.liang@intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Kan Liang There are two free running counters for client IMC uncore. The custom event_init() function hardcode their index to 'UNCORE_PMC_IDX_FIXED' and 'UNCORE_PMC_IDX_FIXED + 1'. To support the 'UNCORE_PMC_IDX_FIXED + 1' case, the generic uncore_perf_event_update is obscurely hacked. The code quality issue will bring problem when new counter index is introduced into generic code. For example, free running counter index. Introduce customized event_read function for client IMC uncore. The customized function is exactly copied from previous generic uncore_pmu_event_read. The 'UNCORE_PMC_IDX_FIXED + 1' case will be isolated for client IMC uncore only. Signed-off-by: Kan Liang --- No changes since V4 arch/x86/events/intel/uncore_snb.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c index aee5e84..df53521 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -450,6 +450,35 @@ static void snb_uncore_imc_event_start(struct perf_event *event, int flags) uncore_pmu_start_hrtimer(box); } +static void snb_uncore_imc_event_read(struct perf_event *event) +{ + struct intel_uncore_box *box = uncore_event_to_box(event); + u64 prev_count, new_count, delta; + int shift; + + /* + * There are two free running counters in IMC. + * The index for the second one is hardcoded to + * UNCORE_PMC_IDX_FIXED + 1. + */ + if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) + shift = 64 - uncore_fixed_ctr_bits(box); + else + shift = 64 - uncore_perf_ctr_bits(box); + + /* the hrtimer might modify the previous event value */ +again: + prev_count = local64_read(&event->hw.prev_count); + new_count = uncore_read_counter(box, event); + if (local64_xchg(&event->hw.prev_count, new_count) != prev_count) + goto again; + + delta = (new_count << shift) - (prev_count << shift); + delta >>= shift; + + local64_add(delta, &event->count); +} + static void snb_uncore_imc_event_stop(struct perf_event *event, int flags) { struct intel_uncore_box *box = uncore_event_to_box(event); @@ -472,7 +501,7 @@ static void snb_uncore_imc_event_stop(struct perf_event *event, int flags) * Drain the remaining delta count out of a event * that we are disabling: */ - uncore_perf_event_update(box, event); + snb_uncore_imc_event_read(event); hwc->state |= PERF_HES_UPTODATE; } } @@ -534,7 +563,7 @@ static struct pmu snb_uncore_imc_pmu = { .del = snb_uncore_imc_event_del, .start = snb_uncore_imc_event_start, .stop = snb_uncore_imc_event_stop, - .read = uncore_pmu_event_read, + .read = snb_uncore_imc_event_read, }; static struct intel_uncore_ops snb_uncore_imc_ops = { -- 2.7.4