From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756091AbeASP0H (ORCPT ); Fri, 19 Jan 2018 10:26:07 -0500 Received: from mail-by2nam03on0088.outbound.protection.outlook.com ([104.47.42.88]:9152 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755718AbeASPZL (ORCPT ); Fri, 19 Jan 2018 10:25:11 -0500 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=fail action=none header.from=nxp.com; From: Dong Aisheng To: CC: , , , , , , , , , Dong Aisheng Subject: [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs Date: Fri, 19 Jan 2018 21:11:08 +0800 Message-ID: <1516367470-24340-9-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516367470-24340-1-git-send-email-aisheng.dong@nxp.com> References: <1516367470-24340-1-git-send-email-aisheng.dong@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131608491085177074;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(396003)(346002)(376002)(39380400002)(39860400002)(2980300002)(1110001)(1109001)(339900001)(54534003)(199004)(189003)(85426001)(498600001)(8676002)(50226002)(48376002)(50466002)(305945005)(2351001)(356003)(2906002)(77096007)(53936002)(26005)(86362001)(16586007)(54906003)(316002)(97736004)(8936002)(36756003)(81166006)(81156014)(68736007)(450100002)(4326008)(6666003)(6916009)(2950100002)(76176011)(51416003)(106466001)(5660300001)(105606002)(104016004)(59450400001)(47776003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1PR03MB2364;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; X-Microsoft-Exchange-Diagnostics: 1;BN1AFFO11FD005;1:X18eH/+386sZDDnnfEPWyvGOQq9Q9oB2o+4Gvh0IFuolsBNFYueZ5mnIyJbT0K3oZ/AkiIkMpS5fNBSwD4Bn29jpjC+7a3FtRc5MhVAXPztWi03sISHMOaQOhzgtOjsx MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b21c19a2-ce07-4201-de30-08d55f50d300 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(5600026)(4604075)(2017052603307);SRVR:CY1PR03MB2364; X-Microsoft-Exchange-Diagnostics: 1;CY1PR03MB2364;3:4U+kzIRMkaEjG2YszNK/6BQ9BarLB9noCeoAU/OHKf4h372vJVj1jWsY5OBo6NgwQHNE/FhdJK4zN4WCEhi9b87/7Y//+kjWYA1l2JBvqg8+MunCIBJypgsLGhUt8AhwWK+GfIqh69B7X6w/lgOxBQFvAwPCiG05ewVvk3EID3CCjC4/ZMAJU4RkCRM3XqUqXOQBxuaku8yur7Sl+Ug5rNmbRSDC2k7E0uDZ4Fg3+PG71w0znkkcMcxA4QT0r4oOvWxnw6c/YPgugOXpY7AAXfNcbNG27lIpJ19ASjB1BGf8hLr7zK6yGUhJhDfz/hKTPTIT5P2c5ser8hpvQHSflOQDhVO9w/W1Wwcgkf9kre4=;25:aYoGQXeSp9sVtef/HXIRi1jLbGJg2v3lwgbsD5Lir0gip523JWRoePa0YHu1T8nzojCcKk31j+G+zj6kFUTgsM23ekyHYhV+ZOk3J744hSS8F0QxPcjERrg9OgfmxnJNu07gE0oGVTWGc1vu1Bd+i7XSJDrhCYWXlb8WJH1uF44VkIc6yg/9ErG7aVM45dxh1L43zyCzJgT0EgHDluq6BnRo1VPq99sYMwp20q452zzO0hghx38zymx/9v36SNu4VJ8qc7DXhR/ox+2hlbjGgjqUZJW2PUVW8FWb8Q6QE1JNzxJcY4gbzOxDA9FnYQVtcZF2EzUCcAgkmNeAww8ucw== X-MS-TrafficTypeDiagnostic: CY1PR03MB2364: X-Microsoft-Exchange-Diagnostics: 1;CY1PR03MB2364;31:r5cQTxnOB+tATLe0l2gSd41NUKPsFwrkMhN2xLTclG4anAyGA2CfR4s96XkTI2Ad/0k7O8mxF0vBV0xquLlLPwICpnRTDiiVXMDUUmzosp/sOoLrDXZQe+wPcVTTrmjGtt4gN/V+sZqPNscR9fhrTkNuiVdqH5Pdy/4tjMEZC3S+oSElOjrNxF0EicKNyDgFc3ZtmoEc4TP0FkrvhRX7UyQ1Ms2izolYV7GgCCwyZxs=;4:qRez+LrForeZVvsEGXbMcas+cytUS1sr4c5gXqYVy1nLNKeOdIeEaofrKS3nNvpc4Lam3wiBiiSnyWwk8n82449TZHNEK1G5WNd/gSip1LENaDffkVBozVLdrcdr6YqUmS3+A5aUNlx+HQQhW+QBH7FVParyIlzsyL/EbsGaa451Gf25DuodNy1X1eGLvBLlAFFKn2N72TYl5lECekH0sv9lvwsh02Su7s4sZ4i1HAP09hDLJHaNEekssTUafRB4lOqE6kex+Y11MzoSsHxXvLt7RNHsXHtjK7Vh56dWe4Xp5r35eRbLJq3RNxgb+aeR X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(6095135)(2401047)(8121501046)(5005006)(93006095)(93001095)(3002001)(3231023)(2400079)(944501161)(10201501046)(6055026)(6096035)(20161123556025)(20161123561025)(20161123563025)(20161123559100)(20161123565025)(201703131430075)(201703131448075)(201703131433075)(201703151042153)(201708071742011);SRVR:CY1PR03MB2364;BCL:0;PCL:0;RULEID:(100000803101)(100110400095)(400006);SRVR:CY1PR03MB2364; X-Forefront-PRVS: 0557CBAD84 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;CY1PR03MB2364;23:WI0dgTmRI91EFibc3k0uFseORBVIQzJvS0bvkUMZf?= =?us-ascii?Q?9Aa5pEeHV4j44GXrtL+xAaZHcXOo2UQ5DMQYPd4XlqrfHzJmFojPsRYo28nK?= =?us-ascii?Q?vjnn4LNpsx7e+TYMAEeDW2gUdxCl90wu5oxQnyAcUVArhwoJBQln//PQAk+X?= =?us-ascii?Q?qTP3wgeM6CboKq2GIED+lGEVO3RH8ykkw1kGcSuyid1X/YgDg1hiIWfTlETb?= =?us-ascii?Q?OY5hi9IWExUfjYWSkVaSczDzhkGxKrbxX26ADN1GzmQ5YykZzj9b4HZoFh/C?= =?us-ascii?Q?zZwsZAbDmaZJZcjij9xvntYYWoiiDdwCUrmj+kBT3DWg9w2+0k1OuHleiiit?= =?us-ascii?Q?Rc3MXp13vNn5JWrFCLqY/3VhoQPrJ8iBmMSOPsbCQklyWXtL1yaG80S7Ap3n?= =?us-ascii?Q?a92q7RFORdowD1k+KJn+4nNat3dL8kX+ifvmRP3NxACM5Zpa1BMptdCHPLBg?= =?us-ascii?Q?wIcSg23IEY5vKC/wgMUvMw9WpSBwXoK+P2pRZkQmJoE92mayzwyXLbCmJljI?= =?us-ascii?Q?eq2gDdgmiv0yl5M+o1NORSy1QJ42/VPABkCnJ8c613xPPpqjU9XJzUJrcqVv?= =?us-ascii?Q?4P0844Vd4dCE4UaEnh05Oovtix+DYFM0OIGiyXuDbjKSNhCT/c4S/ZR3oXpO?= =?us-ascii?Q?evRpSjWGQqdUM4bLYN+HUyQ8Y4hBzNxTCU83+5gHwQBypEsA84ElILDFu3y5?= =?us-ascii?Q?V03RkhGCYoxb++J1fuqkfqMyO+FzRn8fBVVII1y5JStPpgrm4PPAkJ3RRIB7?= =?us-ascii?Q?k5L4m4Wakt8yRaBMepHH6vihp/SpAL1oXhQ7hYdQl++PribjY1WW1kZpXBsN?= =?us-ascii?Q?VmUmpAtp2fJn/oGbbsgd6bEm7FrMui6lIgDeSrQ6MnQtq+o0qui3g571F+cr?= =?us-ascii?Q?zQg17RWMws0naV4nSyd98HCfo4edDTY4/i0QCJoNiSNHYjVJr1Jk96DWcN1u?= =?us-ascii?Q?Bk5yTe5t5ZQY4tfbm1mw/yrRMYzZ3xE73EVZ4txbiFfbLUOWd5vTCX9W9ZvL?= =?us-ascii?Q?ABIdNnVXjTMe0XSKT8mInqcLaxbE51p7mdKa8FB4c2UmqYlrxOlVihUt5quz?= =?us-ascii?Q?v6OtQQc45a5QBIjjigDkOLWoKg6ckPhvq/fSaapYuJALubnSLXcCXkPI8DeQ?= =?us-ascii?Q?e6SP8c4WbkPMu4NIB28CFE2qEgsz5DD?= X-Microsoft-Exchange-Diagnostics: 1;CY1PR03MB2364;6:lVYO3tjZBAGtnvkAVa/LBjGHpi6XJpTEaR6v0kMxt5w4M/qVMRibEIuXYbuvDimMAkSg28TTZFS4qPODSooBPo/sEi0uyhxepUiwuZu2RmARKEoP+LEyPVRxN4ADVbsDTS5RX82iImQP8RZjXFJHifhtRso07uGyv693wvdsTnpoPKIFLpAOygO7phfhJtcem2YdOAjCa26ERc4y1CfzZZ6/sABGRfPvCQMS+AoLxthGYthP7jPrGjEgiojC35OFhhcdgLP5ZFBrMW2vSjWfu+clyL0e1s9PbO3LCgEaWS0GosCIY2nHWBUeZxk+v2k5wfuHd00CImjMfhiFyM+aUBgseLmk9QN4ScnQxFfykeE=;5:CZSrFI/Uk8pOOpDo36fot4aeIPRyd/OdvqRY/U4rWHkgtCutSEHCgOpRYPtRPI9bZ9CQlgTwrolr9H2psg4IIm1y/rYW3A4comv/gGcOUWINO+Xh0dHKnIQ9IRHhSfcKBVxO4ED9rZXB27OXajfnl1FdToP786c0MCSCEYBJ2dQ=;24:jsJaJjS96iuCdptLEUz+apKjI14vokE6CEhxS1DhaFEWLYxZw754QOmGbQ/kBPLSOWwj4QEDF2hM09xTF0KMkGcjx5bGlTAH8Pg1HklouDg=;7:2Vjo3g8EinZdGwfWx7oCh1bMOZ2YDZ8TiwseC/m+UMLVqqTfXxSvCE6dUbaab/EbbTbrv6q7DCDrKv+noYkIPazTkRoOOyphhl6DaBCeaF1gY+GLP7HOTBPspykhPNfQMz+Ws5c2tOBej5dhAQBPtiJC2XtXtF2h0N+JPnsnCP5xocRZVyoTWrGicKgu7l8jE35as7CniTuNRBuPuRaeCfLaGqVdNa1kwL53XqhaSL2bnl7es4muhad/n9Gtxti/ SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2018 15:25:06.0840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b21c19a2-ce07-4201-de30-08d55f50d300 X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[192.88.168.50];Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR03MB2364 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++++++++++++++++++ drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 9074e69..1efed86 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count) i, PTR_ERR(clks[i])); } +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); +} + static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; @@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock( return clk; } +struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name) +{ + struct clk *clk; + + clk = of_clk_get_by_name(np, name); + if (IS_ERR(clk)) + return ERR_PTR(-ENOENT); + + return __clk_get_hw(clk); +} + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 956155c..3d58420 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -8,6 +8,7 @@ extern spinlock_t imx_ccm_lock; void imx_check_clocks(struct clk *clks[], unsigned int count); +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); void imx_register_uart_clocks(struct clk ** const clks[]); extern void imx_cscmr1_fixup(u32 *val); @@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); +struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name); + struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); @@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate) return clk_register_fixed_rate(NULL, name, NULL, 0, rate); } +static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) @@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) @@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width, unsigned long flags) +{ + return clk_hw_register_divider(NULL, name, parent, flags, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider2(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { @@ -136,6 +168,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, shift, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -208,6 +247,17 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, + u8 shift, u8 width, + const char * const *parents, + int num_parents) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | + CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, @@ -218,6 +268,18 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, + void __iomem *reg, u8 shift, + u8 width, + const char * const *parents, + int num_parents, + unsigned long flags) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Dong Aisheng To: Subject: [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs Date: Fri, 19 Jan 2018 21:11:08 +0800 Message-ID: <1516367470-24340-9-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1516367470-24340-1-git-send-email-aisheng.dong@nxp.com> References: <1516367470-24340-1-git-send-email-aisheng.dong@nxp.com> MIME-Version: 1.0 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dong Aisheng , ping.bai@nxp.com, Anson.Huang@nxp.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, fabio.estevam@nxp.com, shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+mturquette=baylibre.com@lists.infradead.org List-ID: Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++++++++++++++++++ drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 9074e69..1efed86 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count) i, PTR_ERR(clks[i])); } +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); +} + static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; @@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock( return clk; } +struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name) +{ + struct clk *clk; + + clk = of_clk_get_by_name(np, name); + if (IS_ERR(clk)) + return ERR_PTR(-ENOENT); + + return __clk_get_hw(clk); +} + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 956155c..3d58420 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -8,6 +8,7 @@ extern spinlock_t imx_ccm_lock; void imx_check_clocks(struct clk *clks[], unsigned int count); +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); void imx_register_uart_clocks(struct clk ** const clks[]); extern void imx_cscmr1_fixup(u32 *val); @@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); +struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name); + struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); @@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate) return clk_register_fixed_rate(NULL, name, NULL, 0, rate); } +static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) @@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) @@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width, unsigned long flags) +{ + return clk_hw_register_divider(NULL, name, parent, flags, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider2(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { @@ -136,6 +168,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, shift, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -208,6 +247,17 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, + u8 shift, u8 width, + const char * const *parents, + int num_parents) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | + CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, @@ -218,6 +268,18 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, + void __iomem *reg, u8 shift, + u8 width, + const char * const *parents, + int num_parents, + unsigned long flags) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: aisheng.dong@nxp.com (Dong Aisheng) Date: Fri, 19 Jan 2018 21:11:08 +0800 Subject: [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs In-Reply-To: <1516367470-24340-1-git-send-email-aisheng.dong@nxp.com> References: <1516367470-24340-1-git-send-email-aisheng.dong@nxp.com> Message-ID: <1516367470-24340-9-git-send-email-aisheng.dong@nxp.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++++++++++++++++++ drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 9074e69..1efed86 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count) i, PTR_ERR(clks[i])); } +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); +} + static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; @@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock( return clk; } +struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name) +{ + struct clk *clk; + + clk = of_clk_get_by_name(np, name); + if (IS_ERR(clk)) + return ERR_PTR(-ENOENT); + + return __clk_get_hw(clk); +} + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 956155c..3d58420 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -8,6 +8,7 @@ extern spinlock_t imx_ccm_lock; void imx_check_clocks(struct clk *clks[], unsigned int count); +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); void imx_register_uart_clocks(struct clk ** const clks[]); extern void imx_cscmr1_fixup(u32 *val); @@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); +struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name); + struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); @@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate) return clk_register_fixed_rate(NULL, name, NULL, 0, rate); } +static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) @@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) @@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width, unsigned long flags) +{ + return clk_hw_register_divider(NULL, name, parent, flags, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider2(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { @@ -136,6 +168,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, shift, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -208,6 +247,17 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, + u8 shift, u8 width, + const char * const *parents, + int num_parents) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | + CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, @@ -218,6 +268,18 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } +static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, + void __iomem *reg, u8 shift, + u8 width, + const char * const *parents, + int num_parents, + unsigned long flags) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); -- 2.7.4