From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226im/HQyJwbgbVyuEmiQVQXOxtVOVTWSkpSB+r+yl/XXaO1n++Q7EyJybGjJAHG7Ei1buec ARC-Seal: i=1; a=rsa-sha256; t=1516813053; cv=none; d=google.com; s=arc-20160816; b=CC1CdoGJkd4vdMseDacIJQju0cDbTtVV2m6clt4icO6rhbPJCKPv9zsc2eNrXQ7Fm3 eCSwQlhMIM/CTc9XSSEN42GKFJFaLzjm3q5MPEzgZaABkB7UU2gknwuEwo9Wp2B8djXP AALQMCR12Dn2cFNOWdF7wuAMf4F5t2EeakrtVQyr8kB/Aj5Cb/UChrs9xy3H8me73rQa uhVbgcmk/nvjiJ2oNt8QYO95bdiFzugdd8ULCZPvZlhsnjkttzD938WaygxYfD/5iAQs 3gbahIk4U/gH2ttuDDSbyn2Qan7IcwFZj89PaHEMQ0YC8k4aXgtRswxSvmz7w1sIkB+T t4DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:to:from:dkim-signature :arc-authentication-results; bh=S3pJhEs+oNl+ahQGBo2pnXasS4PynMDPUdVYV35Hs10=; b=votGYrEZABc5zNPRp5BqAyaOcX+alXnspD3GaQ9d1rib8LcXBS7fhDeu2bwcSOCWBS KTijbpTNbKqxa3zKRwYw5ssLfydBDOFjB0F7fCopxPJ+7FqN8dHXyHmeJ3+yDQh2qXf1 Cg0VwpJjmYKjvfEzcxfwkqUqXbStExYWEIoSsKk3AJ0aHckfg1f+N2kJ2nHK8LFYKeoo NN/9dFRkAWAYeoLGeUZPobWuwJ4fqVFf8z7fr0Nbpkl6ouyRDY7ulLFksSFt9N3ZZQRs xpekzcrzdPjrsw7PVhoBFohXalRbQCoayXUeiOQHelvoyHCt2Ao/V433FjqgI8VGfQN8 NqWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=tpsfRyqU; spf=pass (google.com: domain of prvs=55583cd03=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=55583cd03=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=tpsfRyqU; spf=pass (google.com: domain of prvs=55583cd03=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=55583cd03=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,408,1511827200"; d="scan'208";a="705132967" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk Subject: [PATCH v3 0/6] Basic Speculation Control feature support Date: Wed, 24 Jan 2018 16:56:59 +0000 Message-Id: <1516813025-10794-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590493764137166199?= X-GMAIL-MSGID: =?utf-8?q?1590493764137166199?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Baby steps... this is just the basic CPUID and MSR definitions for AMD and Intel, followed by the complete no-brainer: Disable KPTI on Intel CPUs which set the RDCL_NO bit to say that they don't need it. Roll in the microcode blacklist patch as I'm about to send that out again anyway so it might as well be part of this. Treat it as an RFC perhaps. v2: Cleanups, add AMD bits for STIBP/SPEC_CTRL. v3: Add more CPUs to the exemption for KPTI and clean that up. Add microcode blacklist (RFC) David Woodhouse (6): x86/cpufeatures: Add CPUID_7_EDX CPUID leaf x86/cpufeatures: Add Intel feature bits for Speculation Control x86/cpufeatures: Add AMD feature bits for Speculation Control x86/msr: Add definitions for new speculation control MSRs x86/pti: Do not enable PTI on processors which are not vulnerable to Meltdown x86/cpufeature: Blacklist SPEC_CTRL on early Spectre v2 microcodes arch/x86/include/asm/cpufeature.h | 7 ++- arch/x86/include/asm/cpufeatures.h | 14 ++++-- arch/x86/include/asm/disabled-features.h | 3 +- arch/x86/include/asm/msr-index.h | 12 +++++ arch/x86/include/asm/required-features.h | 3 +- arch/x86/kernel/cpu/common.c | 35 ++++++++++++++- arch/x86/kernel/cpu/intel.c | 76 ++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/scattered.c | 2 - 8 files changed, 141 insertions(+), 11 deletions(-) -- 2.7.4