From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x225bdN/zxT+16g/O5pqyyjrh+uavwABlTj0ugTVioa/ubaICsnBoGETbfxNdqI3bUVdnxxw0 ARC-Seal: i=1; a=rsa-sha256; t=1516872226; cv=none; d=google.com; s=arc-20160816; b=W4gQMvX0jkzXdWiQknxWWb86lp9gl4QWLXgPzgZj8cxhZK2UJG8ikonRGIgLiATNmw 4Dv+deBKwQw3NpWo6oerQwbM0q7mWsu7qtLdpyH2NyosoNQ9+5e9pvhI3mMlCZD6zYCY Ki4Zp+oW+U3YahxIK14qXmNWkH7pwRRZN3Ost5Axj5XpD3seKn+pcsLdCLlBWT/CF6Al X4m3mJuEbCeQdsWKirmsUecBhy55gup5ZO8eigWB9wSc2ve81h19nRvAwKiWaA9u38Ye TrEaDRxd/iWhTmRtdjEo1W4Y9Mt8vVEGJoABJm7oGuyTbnrOjvfRft0SCtmeNC6jrkuX HJpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=+agi30b5qPdf3MYHcaOVMGI+hD4bJ5FkjjKj5Un7BRI=; b=W7ggXa/gqx9am63VJJ82tgoXczd6FdYE+5VaeJ+l6YRrj1AsmWkiJpZiR3ZvRq1E53 fo8r4p5kSjXNF5tdazrK+O68hvUcO4yJ5jbQEb2FjJJA9uyF9RwWDX8NZe1I1Tfkt1Wx 21TLh/ql6pMT6qtC7m0LFaSKSBu/icF42l5sTMCqGdhmoFXjsKQXfBrhb2Y8XccWUngq pI2YGOrzlk7s44SnaMq6LUBLvjlIayaGU/KyuDS5bnRiVpveEjBeo0Fzu2WotsCuO2HN 4BOJyGRINYdVkvob9xSxPx8KC11rE1D0tzYW+8YhBxASL4XbMHrmLvYzb7wmCNLY0f5h 4xnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=k/UodW2A; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.190.10 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=k/UodW2A; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.190.10 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,411,1511827200"; d="scan'208";a="717039787" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v4 2/7] x86/cpufeatures: Add Intel feature bits for Speculation Control Date: Thu, 25 Jan 2018 09:23:04 +0000 Message-Id: <1516872189-16577-3-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555812493666698?= X-GMAIL-MSGID: =?utf-8?q?1590555812493666698?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add three feature bits exposed by new microcode on Intel CPUs for speculation control. Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman Reviewed-by: Borislav Petkov --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7b25cf3..0a51070 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -320,6 +320,9 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation Control (IBRS + IBPB) */ +#define X86_FEATURE_STIBP (18*32+27) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ /* * BUG word(s) -- 2.7.4