From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753723AbdGJLFo (ORCPT ); Mon, 10 Jul 2017 07:05:44 -0400 Received: from gloria.sntech.de ([95.129.55.99]:54192 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753677AbdGJLFm (ORCPT ); Mon, 10 Jul 2017 07:05:42 -0400 From: Heiko Stuebner To: Elaine Zhang Cc: mturquette@baylibre.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, huangtao@rock-chips.com, cl@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: Re: [PATCH v2] clk: fractional-divider: fix up the fractional clk's jitter Date: Mon, 10 Jul 2017 13:05:30 +0200 Message-ID: <1517147.8QBNcir4nx@phil> User-Agent: KMail/5.2.3 (Linux/4.9.0-2-amd64; KDE/5.28.0; x86_64; ; ) In-Reply-To: <1499395943-19516-1-git-send-email-zhangqing@rock-chips.com> References: <1499395943-19516-1-git-send-email-zhangqing@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Elaine, Am Freitag, 7. Juli 2017, 10:52:23 CEST schrieb Elaine Zhang: > add clk_fractional_divider_special_ops for rockchip specific requirements, > fractional divider must set that denominator is 20 times larger than > numerator to generate precise clock frequency. > Otherwise the CLK jitter is very big, poor quality of the clock signal. > > RK document description: > 3.1.9 Fractional divider usage > To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by > fractional divider. Generally you must set that denominator is 20 times > larger than numerator to generate precise clock frequency. So the > fractional divider applies only to generate low frequency clock like > I2S, UART.igned-off-by: Elaine Zhang > > Signed-off-by: Elaine Zhang > --- > drivers/clk/clk-fractional-divider.c | 32 ++++++++++++++++++++++++++++++++ > drivers/clk/rockchip/clk.c | 2 +- > include/linux/clk-provider.h | 1 + > 3 files changed, 34 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c > index aab904618eb6..3107b33327f9 100644 > --- a/drivers/clk/clk-fractional-divider.c > +++ b/drivers/clk/clk-fractional-divider.c > @@ -158,6 +158,38 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, > } > EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider); > > +static long clk_fd_round_rate_special(struct clk_hw *hw, unsigned long rate, > + unsigned long *parent_rate) > +{ this obviously still encodes Rockchip-specific things into the generic fractional-divider driver. And it's of course only special for Rockchip fractional dividers and will end it chaos if every implementation wants to add a "special" function there. Did you have a look at the patch I added to the last mail (for real this time)? Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko Stuebner) Date: Mon, 10 Jul 2017 13:05:30 +0200 Subject: [PATCH v2] clk: fractional-divider: fix up the fractional clk's jitter In-Reply-To: <1499395943-19516-1-git-send-email-zhangqing@rock-chips.com> References: <1499395943-19516-1-git-send-email-zhangqing@rock-chips.com> Message-ID: <1517147.8QBNcir4nx@phil> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Elaine, Am Freitag, 7. Juli 2017, 10:52:23 CEST schrieb Elaine Zhang: > add clk_fractional_divider_special_ops for rockchip specific requirements, > fractional divider must set that denominator is 20 times larger than > numerator to generate precise clock frequency. > Otherwise the CLK jitter is very big, poor quality of the clock signal. > > RK document description: > 3.1.9 Fractional divider usage > To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by > fractional divider. Generally you must set that denominator is 20 times > larger than numerator to generate precise clock frequency. So the > fractional divider applies only to generate low frequency clock like > I2S, UART.igned-off-by: Elaine Zhang > > Signed-off-by: Elaine Zhang > --- > drivers/clk/clk-fractional-divider.c | 32 ++++++++++++++++++++++++++++++++ > drivers/clk/rockchip/clk.c | 2 +- > include/linux/clk-provider.h | 1 + > 3 files changed, 34 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c > index aab904618eb6..3107b33327f9 100644 > --- a/drivers/clk/clk-fractional-divider.c > +++ b/drivers/clk/clk-fractional-divider.c > @@ -158,6 +158,38 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, > } > EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider); > > +static long clk_fd_round_rate_special(struct clk_hw *hw, unsigned long rate, > + unsigned long *parent_rate) > +{ this obviously still encodes Rockchip-specific things into the generic fractional-divider driver. And it's of course only special for Rockchip fractional dividers and will end it chaos if every implementation wants to add a "special" function there. Did you have a look at the patch I added to the last mail (for real this time)? Heiko