From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2277aduIYpl+4emDg6C7D72bzMAkXUdtXzdWjSor+k+dJJXmY8XcAzy1ow4cVclm2xPHhIIm ARC-Seal: i=1; a=rsa-sha256; t=1517263513; cv=none; d=google.com; s=arc-20160816; b=KWOhtVRVaDlz1z3gm68BwopwdlL4Gkb4fwGajerREPv1Z//sdEcJIOpNZnbS+hSZfN PCwmxtllLW/5R6lqdg4Kvz/WxZFnWOuHP1U9fzz1bEQRZrK3o9pq1jJn6YIp4aaXyV5p WXSZDc3XLyPDTrwAOS9rA0uqkxkktviTZqTj8WSMAlqRC82rA+gxABrpNeniG0zDOrcQ DsUz+voSEBEftXnUo6rtXYIzWI/+2DFRm7/E46hyaOKeEw2/J/Km3DsFnXFRYOFl9vEj UwG0ZBT554U2wDPfuFqW/cdBMgk21AAxLQ0Ei9WHDEDCpTw7wA08j3PCjSahUagn+8Cp 5srQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=precedence:content-transfer-encoding:mime-version:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=1dfz5YPk3SCSLHXzW8OyyjfnXBJbnqVw5bOIX3hLuPo=; b=OxD1YCuBY8Kye50izgNt7aALWqmoyN9ZD0hpCvKD+aN2HPCT/SOZ9wo3vR6czfC11j d/qHMfSwhBrWuB544z687kwyumVuFS12+Zwdw7XzdWG6N6pzf6yQmt4CypFiiOqsEsgl Xrozix+MdPK29FeBMtTXkNBuv1kqjkIw61aVx/Y3uAYEF7kdhggWCLjT57Jb4ITkjQNL 3B54lh1Kk5RFApIn4nxCCw6OafrwRIwpzq/MXIUza25SJt0RFB4lLlfIk7CXKgPZZ4Si 2oBkPIaCVKpamND+jQzsYhp5Kdam31aDCltE/QUMzP17fBNES3ZJnhAIXgepd9dvs4AF N45w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=qu0bMrUf; spf=pass (google.com: domain of prvs=5600f5902=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=5600f5902=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=qu0bMrUf; spf=pass (google.com: domain of prvs=5600f5902=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=5600f5902=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,432,1511827200"; d="scan'208";a="591069749" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, mingo@kernel.org, luto@kernel.org, linux@dominikbrodowski.net Subject: [PATCH] x86/speculation: Use Indirect Branch Prediction Barrier in context switch Date: Mon, 29 Jan 2018 22:04:47 +0000 Message-Id: <1517263487-3708-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590966106432961445?= X-GMAIL-MSGID: =?utf-8?q?1590966106432961445?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Tim Chen Flush indirect branches when switching into a process that marked itself non dumpable. This protects high value processes like gpg better, without having too high performance overhead. If done naïvely, we could switch to a kernel idle thread and then back to the original process, such as: process A -> idle -> process A In such scenario, we do not have to do IBPB here even though the process is non-dumpable, as we are switching back to the same process after a hiatus. To avoid the redundant IBPB, which is expensive, we track the last mm user context ID. The cost is to have an extra u64 mm context id to track the last mm we were using before switching to the init_mm used by idle. Avoiding the extra IBPB is probably worth the extra memory for this common scenario. For those cases where tlb_defer_switch_to_init_mm() returns true (non PCID), lazy tlb will defer switch to init_mm, so we will not be changing the mm for the process A -> idle -> process A switch. So IBPB will be skipped for this case. Thanks to the reviewers and Andy Lutomirski for the suggestion of using ctx_id which got rid of the problem of mm pointer recycling. Signed-off-by: Tim Chen Signed-off-by: David Woodhouse --- arch/x86/include/asm/tlbflush.h | 2 ++ arch/x86/mm/tlb.c | 33 ++++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 3effd3c..4405c4b 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -174,6 +174,8 @@ struct tlb_state { struct mm_struct *loaded_mm; u16 loaded_mm_asid; u16 next_asid; + /* last user mm's ctx id */ + u64 last_ctx_id; /* * We can be in one of several states: diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index a156195..7489890 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -6,13 +6,14 @@ #include #include #include +#include #include #include +#include #include #include #include -#include /* * TLB flushing, formerly SMP-only @@ -219,6 +220,27 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, } else { u16 new_asid; bool need_flush; + u64 last_ctx_id = this_cpu_read(cpu_tlbstate.last_ctx_id); + + /* + * Avoid user/user BTB poisoning by flushing the branch + * predictor when switching between processes. This stops + * one process from doing Spectre-v2 attacks on another. + * + * As an optimization, flush indirect branches only when + * switching into processes that disable dumping. This + * protects high value processes like gpg, without having + * too high performance overhead. IBPB is *expensive*! + * + * This will not flush branches when switching into kernel + * threads. It will also not flush if we switch to idle + * thread and back to the same process. It will flush if we + * switch to a different non-dumpable process. + */ + if (tsk && tsk->mm && + tsk->mm->context.ctx_id != last_ctx_id && + get_dumpable(tsk->mm) != SUID_DUMP_USER) + indirect_branch_prediction_barrier(); if (IS_ENABLED(CONFIG_VMAP_STACK)) { /* @@ -268,6 +290,14 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0); } + /* + * Record last user mm's context id, so we can avoid + * flushing branch buffer with IBPB if we switch back + * to the same user. + */ + if (next != &init_mm) + this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id); + this_cpu_write(cpu_tlbstate.loaded_mm, next); this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); } @@ -345,6 +375,7 @@ void initialize_tlbstate_and_flush(void) write_cr3(build_cr3(mm->pgd, 0)); /* Reinitialize tlbstate. */ + this_cpu_write(cpu_tlbstate.last_ctx_id, mm->context.ctx_id); this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0); this_cpu_write(cpu_tlbstate.next_asid, 1); this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id); -- 2.7.4