From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752509AbeBIDjD (ORCPT ); Thu, 8 Feb 2018 22:39:03 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:26970 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752203AbeBIDjB (ORCPT ); Thu, 8 Feb 2018 22:39:01 -0500 X-UUID: b3c1aed328fd40598717a8456b24e102-20180209 Message-ID: <1518147536.9025.9.camel@mtkswgap22> Subject: Re: [PATCH v2 01/16] dt-bindings: clock: mediatek: add missing required #reset-cells From: Sean Wang To: Matthias Brugger CC: , , , , , , Rob Herring , Stephen Boyd Date: Fri, 9 Feb 2018 11:38:56 +0800 In-Reply-To: <391278e5-9b72-1142-0262-5d286fe17d8d@gmail.com> References: <391278e5-9b72-1142-0262-5d286fe17d8d@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2018-02-07 at 11:45 +0100, Matthias Brugger wrote: > > On 02/06/2018 10:52 AM, sean.wang@mediatek.com wrote: > > From: Sean Wang > > > > All ethsys, pciesys and ssusbsys internally include reset controller, so > > explicitly add back these missing cell definitions to related bindings > > and examples. > > > > Signed-off-by: Sean Wang > > Cc: Rob Herring > > Cc: Stephen Boyd > > Reviewed-by: Rob Herring > > --- > > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 2 ++ > > Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ > > Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ > > 3 files changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > index 7aa3fa1..8f5335b 100644 > > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > @@ -9,6 +9,7 @@ Required Properties: > > - "mediatek,mt2701-ethsys", "syscon" > > - "mediatek,mt7622-ethsys", "syscon" > > - #clock-cells: Must be 1 > > +- #reset-cells: Must be 1 > > > > The ethsys controller uses the common clk binding from > > Documentation/devicetree/bindings/clock/clock-bindings.txt > > @@ -20,4 +21,5 @@ ethsys: clock-controller@1b000000 { > > compatible = "mediatek,mt2701-ethsys", "syscon"; > > reg = <0 0x1b000000 0 0x1000>; > > #clock-cells = <1>; > > + #reset-cells = <1>; > > The example is already fixed upstream, but I forgot the binding description, > please rebase this patch. > > And please don't forget to add all clock maintainers. > okay, i will do it. > Regards, > Matthias > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Wang Subject: Re: [PATCH v2 01/16] dt-bindings: clock: mediatek: add missing required #reset-cells Date: Fri, 9 Feb 2018 11:38:56 +0800 Message-ID: <1518147536.9025.9.camel@mtkswgap22> References: <391278e5-9b72-1142-0262-5d286fe17d8d@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <391278e5-9b72-1142-0262-5d286fe17d8d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Matthias Brugger Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Stephen Boyd List-Id: devicetree@vger.kernel.org On Wed, 2018-02-07 at 11:45 +0100, Matthias Brugger wrote: > > On 02/06/2018 10:52 AM, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote: > > From: Sean Wang > > > > All ethsys, pciesys and ssusbsys internally include reset controller, so > > explicitly add back these missing cell definitions to related bindings > > and examples. > > > > Signed-off-by: Sean Wang > > Cc: Rob Herring > > Cc: Stephen Boyd > > Reviewed-by: Rob Herring > > --- > > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 2 ++ > > Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ > > Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ > > 3 files changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > index 7aa3fa1..8f5335b 100644 > > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > @@ -9,6 +9,7 @@ Required Properties: > > - "mediatek,mt2701-ethsys", "syscon" > > - "mediatek,mt7622-ethsys", "syscon" > > - #clock-cells: Must be 1 > > +- #reset-cells: Must be 1 > > > > The ethsys controller uses the common clk binding from > > Documentation/devicetree/bindings/clock/clock-bindings.txt > > @@ -20,4 +21,5 @@ ethsys: clock-controller@1b000000 { > > compatible = "mediatek,mt2701-ethsys", "syscon"; > > reg = <0 0x1b000000 0 0x1000>; > > #clock-cells = <1>; > > + #reset-cells = <1>; > > The example is already fixed upstream, but I forgot the binding description, > please rebase this patch. > > And please don't forget to add all clock maintainers. > okay, i will do it. > Regards, > Matthias > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: sean.wang@mediatek.com (Sean Wang) Date: Fri, 9 Feb 2018 11:38:56 +0800 Subject: [PATCH v2 01/16] dt-bindings: clock: mediatek: add missing required #reset-cells In-Reply-To: <391278e5-9b72-1142-0262-5d286fe17d8d@gmail.com> References: <391278e5-9b72-1142-0262-5d286fe17d8d@gmail.com> Message-ID: <1518147536.9025.9.camel@mtkswgap22> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 2018-02-07 at 11:45 +0100, Matthias Brugger wrote: > > On 02/06/2018 10:52 AM, sean.wang at mediatek.com wrote: > > From: Sean Wang > > > > All ethsys, pciesys and ssusbsys internally include reset controller, so > > explicitly add back these missing cell definitions to related bindings > > and examples. > > > > Signed-off-by: Sean Wang > > Cc: Rob Herring > > Cc: Stephen Boyd > > Reviewed-by: Rob Herring > > --- > > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 2 ++ > > Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ > > Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ > > 3 files changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > index 7aa3fa1..8f5335b 100644 > > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > > @@ -9,6 +9,7 @@ Required Properties: > > - "mediatek,mt2701-ethsys", "syscon" > > - "mediatek,mt7622-ethsys", "syscon" > > - #clock-cells: Must be 1 > > +- #reset-cells: Must be 1 > > > > The ethsys controller uses the common clk binding from > > Documentation/devicetree/bindings/clock/clock-bindings.txt > > @@ -20,4 +21,5 @@ ethsys: clock-controller at 1b000000 { > > compatible = "mediatek,mt2701-ethsys", "syscon"; > > reg = <0 0x1b000000 0 0x1000>; > > #clock-cells = <1>; > > + #reset-cells = <1>; > > The example is already fixed upstream, but I forgot the binding description, > please rebase this patch. > > And please don't forget to add all clock maintainers. > okay, i will do it. > Regards, > Matthias >