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From: Alexandru Stefan ISAILA <aisaila@bitdefender.com>
To: "andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>,
	"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Cc: "boris.ostrovsky@oracle.com" <boris.ostrovsky@oracle.com>,
	"tamas@tklengyel.com" <tamas@tklengyel.com>,
	"jbeulich@suse.com" <jbeulich@suse.com>,
	"suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>,
	"rcojocaru@bitdefender.com" <rcojocaru@bitdefender.com>
Subject: Re: [PATCH v3 2/4] hvm/svm: Enable Breakpoint events
Date: Tue, 13 Feb 2018 12:48:49 +0000	[thread overview]
Message-ID: <1518526129.4963.14.camel@bitdefender.com> (raw)
In-Reply-To: <5aba8de5-4cca-9a4b-0f82-ec032eb48b96@citrix.com>

On Lu, 2018-02-12 at 15:54 +0000, Andrew Cooper wrote:
> On 12/02/18 15:08, Alexandru Isaila wrote:
> >
> > @@ -2619,14 +2634,31 @@ void svm_vmexit_handler(struct
> > cpu_user_regs *regs)
> >          break;
> >
> >      case VMEXIT_EXCEPTION_BP:
> > -        if ( !v->domain->debugger_attached )
> > -            goto unexpected_exit_type;
> > -        /* AMD Vol2, 15.11: INT3, INTO, BOUND intercepts do not
> > update RIP. */
> > -        if ( (inst_len = __get_instruction_length(v, INSTR_INT3))
> > == 0 )
> > +        inst_len = __get_instruction_length(v, INSTR_INT3);
> There are multiple ways of ending up with this vmexit, and INT3 is
> not
> the only way.
>
> The old code was somewhat broken (but only in the case that a
> debugger
> was attached), but now with  this introspection hook active,
> executing
> `0xcd 0x03` will end up crashing the domain because of a length
> mismatch
> looking for 0xcc.
>
> You need to inspect EXITINTINFO to work out what went on here, and
> distinguish INT3 from INT $3.
>
> Can I suggest that you run this unit test
> http://xenbits.xen.org/docs/xtf/test-swint-emulation.html under debug
> introspection an check that you get all expected events?  Every time
> we
> touch this code, we seem to break it :(
>
> ~Andrew
>
Hi Andrew,

I've executed the test-swint-emulation and the domain did not crash.
The result is right here:
(d1) --- Xen Test Framework ---
(d1) Environment: HVM 64bit (Long mode 4 levels)
(d1) Software interrupt emulation
(d1) FEP support not detected - some tests will be skipped
(d1) Test cpl0: all perms ok
(d1)   Testing int3
(d1)   Testing int $3
(d1)   Testing icebp
(d1)   Testing int $1
(d1)   Testing into
(d1) Test cpl0: p=0
(d1)   Testing int3
(d1)   Testing int $3
(d1)   Testing icebp
(d1)   Testing int $1
(d1)   Testing into
(d1) Test cpl3: all perms ok
(d1)   Testing int3
(d1)   Testing int $3
(d1)   Testing icebp
(d1)   Testing int $1
(d1)   Testing into
(d1) Test cpl3: p=0
(d1)   Testing int3
(d1)   Testing int $3
(d1)   Testing icebp
(d1)   Testing int $1
(d1)   Testing into
(d1) Test cpl3: dpl=0
(d1)   Testing int3
(d1)   Testing int $3
(d1)   Testing icebp
(d1)   Testing int $1
(d1)   Testing into
(d1) Test result: SKIP


If you think we need to be safe, I can add a test like if (
exitintinfo.type !=  INSTR_INT3) break;

~Alex

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  parent reply	other threads:[~2018-02-13 12:48 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-12 15:08 [PATCH v3 0/4] hvm/svm: Enable vm events for SVM Alexandru Isaila
2018-02-12 15:08 ` [PATCH v3 1/4] asm-x86/monitor: Fix monitor capability reporting on SVM systems Alexandru Isaila
2018-02-12 15:13   ` Andrew Cooper
2018-02-14 17:47     ` Andrew Cooper
2018-02-14 17:56       ` Razvan Cojocaru
2018-02-14 21:34         ` Tamas K Lengyel
2018-02-12 15:08 ` [PATCH v3 2/4] hvm/svm: Enable Breakpoint events Alexandru Isaila
2018-02-12 15:49   ` Tamas K Lengyel
2018-02-12 15:54   ` Andrew Cooper
2018-02-12 16:03     ` Tamas K Lengyel
2018-02-13 12:48     ` Alexandru Stefan ISAILA [this message]
2018-02-14 16:10     ` Alexandru Stefan ISAILA
2018-02-14 18:22       ` Andrew Cooper
2018-02-14 19:11         ` Andrew Cooper
2018-02-15  8:20           ` Alexandru Stefan ISAILA
2018-02-12 15:08 ` [PATCH v3 3/4] hvm/svm: Enable MSR events Alexandru Isaila
2018-02-12 15:08 ` [PATCH v3 4/4] hvm/svm: Enable CR events Alexandru Isaila

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