[PATCH] drm/i915: Enable VBT based BL control for DP (v3)

[PATCH] drm/i915: Enable VBT based BL control for DP (v3)

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec)
to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP
backlight controller on MRB (BXT) platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and return
   the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73..f9b922d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+        int backlight_controller = dev_priv->vbt.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable VBT based BL control for DP (v3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3)
URL   : https://patchwork.freedesktop.org/series/38559/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
50f1199ece18 drm/i915: Enable VBT based BL control for DP (v3)
-:9: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#9: 
This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec)

-:31: ERROR: code indent should use tabs where possible
#31: FILE: drivers/gpu/drm/i915/intel_dp.c:660:
+        int backlight_controller = dev_priv->vbt.backlight.controller;$

-:31: WARNING: please, no spaces at the start of a line
#31: FILE: drivers/gpu/drm/i915/intel_dp.c:660:
+        int backlight_controller = dev_priv->vbt.backlight.controller;$

total: 1 errors, 2 warnings, 0 checks, 29 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Series 38559v1 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revisions/1/mbox/

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:427s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:498s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:285s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:479s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:487s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:469s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:457s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:574s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:565s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:417s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:286s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:515s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:394s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:411s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:459s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:459s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:499s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:455s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:594s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:432s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:507s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:534s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:492s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:491s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:417s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:426s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:527s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:393s

2ca2a369fc68ac59f42f359b62a978273425e531 drm-tip: 2018y-02m-19d-20h-39m-49s UTC integration manifest
50f1199ece18 drm/i915: Enable VBT based BL control for DP (v3)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8071/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[V3] drm/i915: Enable VBT based BL control for DP

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec)
to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP
backlight controller on MRB (BXT) platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and return
   the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73..f9b922d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller = dev_priv->vbt.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable VBT based BL control for DP (v3) (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev2)
URL   : https://patchwork.freedesktop.org/series/38559/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
10e3cca20783 drm/i915: Enable VBT based BL control for DP
-:9: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#9: 
This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec)

total: 0 errors, 1 warnings, 0 checks, 29 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[V3] drm/i915: Enable VBT based BL control for DP

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controller on MRB (BXT)
platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and
   return the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73..f9b922d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller = dev_priv->vbt.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Enable VBT based BL control for DP (v3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912
Test perf:
        Subgroup oa-exponents:
                pass       -> FAIL       (shard-apl) fdo#102254
Test gem_eio:
        Subgroup in-flight:
                pass       -> FAIL       (shard-hsw) fdo#104676

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676

shard-apl        total:3343 pass:1752 dwarn:1   dfail:0   fail:13  skip:1576 time:12175s
shard-hsw        total:3434 pass:1761 dwarn:1   dfail:0   fail:3   skip:1668 time:11789s
shard-snb        total:3434 pass:1352 dwarn:1   dfail:0   fail:2   skip:2079 time:6878s
Blacklisted hosts:
shard-kbl        total:3410 pass:1918 dwarn:1   dfail:0   fail:13  skip:1476 time:9057s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8071/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev2)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Series 38559v2 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revisions/2/mbox/

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:376s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:483s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:287s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:482s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:482s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:467s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:456s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:558s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:577s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:419s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:283s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:515s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:390s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:410s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:452s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:497s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:458s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:499s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:592s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:435s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:511s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:526s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:492s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:483s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:415s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:429s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:524s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:395s

2ca2a369fc68ac59f42f359b62a978273425e531 drm-tip: 2018y-02m-19d-20h-39m-49s UTC integration manifest
10e3cca20783 drm/i915: Enable VBT based BL control for DP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8072/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev3)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Series 38559v3 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revisions/3/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-cnl-y3) fdo#103191

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:418s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:427s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:375s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:483s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:286s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:481s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:485s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:470s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:458s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:568s
fi-cnl-y3        total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:579s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:412s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:281s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:393s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:456s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:458s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:503s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:451s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:498s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:589s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:509s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:529s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:491s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:472s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:415s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:523s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:400s

2ca2a369fc68ac59f42f359b62a978273425e531 drm-tip: 2018y-02m-19d-20h-39m-49s UTC integration manifest
6a0e25d9572e drm/i915: Enable VBT based BL control for DP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8074/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev3)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Test perf:
        Subgroup buffer-fill:
                fail       -> PASS       (shard-apl) fdo#103755
        Subgroup oa-exponents:
                pass       -> FAIL       (shard-hsw) fdo#102254 +1
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912
Test gem_eio:
        Subgroup in-flight:
                pass       -> FAIL       (shard-hsw) fdo#104676
Test kms_flip:
        Subgroup plain-flip-ts-check:
                pass       -> FAIL       (shard-hsw) fdo#100368

fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-apl        total:3343 pass:1753 dwarn:1   dfail:0   fail:12  skip:1576 time:12194s
shard-hsw        total:3434 pass:1759 dwarn:1   dfail:0   fail:5   skip:1668 time:11650s
shard-snb        total:3434 pass:1352 dwarn:1   dfail:0   fail:2   skip:2079 time:6648s
Blacklisted hosts:
shard-kbl        total:3410 pass:1918 dwarn:1   dfail:0   fail:13  skip:1476 time:9033s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8074/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V3] drm/i915: Enable VBT based BL control for DP

[Chris Wilson]

Quoting Mustamin B Mustaffa (2018-02-20 06:52:49)
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
> 
> This patch will tell which BXT_PP registers (there are two set of
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
> table) and this will enabled eDP backlight controller on MRB (BXT)
> platform.
> 
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
> 
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1868f73..f9b922d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>  {
>         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  

Ah, a purveyor of newlines.

> +       int backlight_controller = dev_priv->vbt.backlight.controller;

Isn't the vbt->backlight.controller sanitized to the
panel->backlight.controller at this point?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V3] drm/i915: Enable VBT based BL control for DP

[Mustaffa, Mustamin B]

Hi Chris, 

Would you rather for me to use following line instead? 

+       int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;

Best regard 

Mustamin


-----Original Message-----
From: Chris Wilson [mailto:chris@chris-wilson.co.uk] 
Sent: Tuesday, February 20, 2018 4:39 PM
To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
Subject: Re: [Intel-gfx] [V3] drm/i915: Enable VBT based BL control for DP

Quoting Mustamin B Mustaffa (2018-02-20 06:52:49)
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
> 
> This patch will tell which BXT_PP registers (there are two set of 
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> Timing
> table) and this will enabled eDP backlight controller on MRB (BXT) 
> platform.
> 
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
> 
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> b/drivers/gpu/drm/i915/intel_dp.c index 1868f73..f9b922d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct 
> drm_i915_private *dev_priv)  {
>         struct drm_i915_private *dev_priv = 
> to_i915(intel_dp_to_dev(intel_dp));
>  

Ah, a purveyor of newlines.

> +       int backlight_controller = dev_priv->vbt.backlight.controller;

Isn't the vbt->backlight.controller sanitized to the
panel->backlight.controller at this point?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V3] drm/i915: Enable VBT based BL control for DP

[Chris Wilson]

Quoting Mustaffa, Mustamin B (2018-02-20 08:44:45)
> Hi Chris, 
> 
> Would you rather for me to use following line instead? 
> 
> +       int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;

I think so, Jani would be best to answer the question about how
vbt/panel tie together with backlight and which is meant to be used.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[V4] drm/i915: Enable VBT based BL control for DP

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controller on MRB (BXT)
platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and
   return the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.
V4:
 - Use sanitized panel backlight controller instead of vbt backlight
   controller

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73..f9b922d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V3] drm/i915: Enable VBT based BL control for DP

[Jani Nikula]

On Tue, 20 Feb 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Mustaffa, Mustamin B (2018-02-20 08:44:45)
>> Hi Chris, 
>> 
>> Would you rather for me to use following line instead? 
>> 
>> +       int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;
>
> I think so, Jani would be best to answer the question about how
> vbt/panel tie together with backlight and which is meant to be used.

We discussed this previously, and the following sequence would lead to
panel.backlight.controller being used uninitialized in
bxt_power_sequencer_idx because it gets set at
intel_panel_setup_backlight:

- intel_edp_init_connector
  +- intel_dp_pps_init
  |  +- intel_dp_init_panel_power_sequencer_registers
  |     +- intel_pps_get_registers
  |        +- bxt_power_sequencer_idx
  +- intel_panel_setup_backlight

I decided it wasn't worth blocking a reasonable fix (that might warrant
cc: stable actually) on a refactoring. We can (and should) do the
refactoring later though.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable VBT based BL control for DP (v3) (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev4)
URL   : https://patchwork.freedesktop.org/series/38559/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e4ce0242c53b drm/i915: Enable VBT based BL control for DP
-:35: WARNING: line over 80 characters
#35: FILE: drivers/gpu/drm/i915/intel_dp.c:660:
+	int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;

total: 0 errors, 1 warnings, 0 checks, 29 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev4)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Series 38559v4 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revisions/4/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713 +1
Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                fail       -> PASS       (fi-gdg-551) fdo#102575
Test kms_chamelium:
        Subgroup dp-crc-fast:
                dmesg-fail -> PASS       (fi-kbl-7500u) fdo#103841

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:412s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:421s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:370s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:481s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:282s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:475s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:479s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:462s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:453s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:568s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:417s
fi-gdg-551       total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 time:281s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:508s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:388s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:405s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:457s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:408s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:453s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:494s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:491s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:585s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:503s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:514s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:487s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:476s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:404s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:429s
fi-snb-2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:390s

67f148034b8b6afdb0811e88245b67ad7730bb1a drm-tip: 2018y-02m-20d-09h-12m-29s UTC integration manifest
e4ce0242c53b drm/i915: Enable VBT based BL control for DP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8076/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915: Enable VBT based BL control for DP (v3) (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev4)
URL   : https://patchwork.freedesktop.org/series/38559/
State : failure

== Summary ==

Test gem_softpin:
        Subgroup noreloc-s3:
                pass       -> SKIP       (shard-snb) fdo#103375 +1
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> SKIP       (shard-snb) fdo#103880
Test gem_exec_flush:
        Subgroup basic-uc-prw-default:
                pass       -> INCOMPLETE (shard-hsw)

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880

shard-apl        total:3358 pass:1758 dwarn:1   dfail:0   fail:8   skip:1590 time:12157s
shard-hsw        total:3334 pass:1709 dwarn:1   dfail:0   fail:1   skip:1621 time:11386s
shard-snb        total:3429 pass:1349 dwarn:1   dfail:0   fail:1   skip:2078 time:6518s
Blacklisted hosts:
shard-kbl        total:3429 pass:1925 dwarn:1   dfail:0   fail:9   skip:1494 time:9524s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8076/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V4] drm/i915: Enable VBT based BL control for DP

[Ville Syrjälä]

On Tue, Feb 20, 2018 at 05:42:59PM +0800, Mustamin B Mustaffa wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
> 
> This patch will tell which BXT_PP registers (there are two set of
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
> table) and this will enabled eDP backlight controller on MRB (BXT)
> platform.
> 
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
> V4:
>  - Use sanitized panel backlight controller instead of vbt backlight
>    controller
> 
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1868f73..f9b922d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)

Your git diff is clearly broken. This makes patch review harder than
it has to be. Please consider updating to a non-broken version.

>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  
> +	int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;
> +
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
>  	/* We should never land here with regular DP ports */
>  	WARN_ON(!intel_dp_is_edp(intel_dp));
>  
> -	/*
> -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> -	 * use instance #0 always.
> -	 */
>  	if (!intel_dp->pps_reset)
> -		return 0;
> +		return backlight_controller;
>  
>  	intel_dp->pps_reset = false;
>  
> @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
>  
> -	return 0;
> +	return backlight_controller;
>  }
>  
>  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Enable VBT based BL control for DP (v3)

[Rodrigo Vivi]

On Tue, Feb 20, 2018 at 10:46:45AM +0800, Mustamin B Mustaffa wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
> 
> This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in the spec)
> to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP
> backlight controller on MRB (BXT) platform.
> 
> v2:
>  - Remove unnecessary information in commit message.

what was unnecessary? Do you have any Bugzilla entry or Fixes tag?

>  - Assign vbt.backlight.controller to a backlight_controller variable and return
>    the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
> 
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1868f73..f9b922d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  
> +        int backlight_controller = dev_priv->vbt.backlight.controller;

The patch looks right.

But I wonder if we could use somehow the already set panel->backlight.controller.
instead of duplicating this vbt association.
(set at bxt_setup_backlight)

> +
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
>  	/* We should never land here with regular DP ports */
>  	WARN_ON(!intel_dp_is_edp(intel_dp));
>  
> -	/*
> -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> -	 * use instance #0 always.
> -	 */
>  	if (!intel_dp->pps_reset)
> -		return 0;
> +		return backlight_controller;
>  
>  	intel_dp->pps_reset = false;
>  
> @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
>  
> -	return 0;
> +	return backlight_controller;
>  }
>  
>  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V3] drm/i915: Enable VBT based BL control for DP

[Rodrigo Vivi]

On Tue, Feb 20, 2018 at 11:43:57AM +0200, Jani Nikula wrote:
> On Tue, 20 Feb 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > Quoting Mustaffa, Mustamin B (2018-02-20 08:44:45)
> >> Hi Chris, 
> >> 
> >> Would you rather for me to use following line instead? 
> >> 
> >> +       int backlight_controller = intel_dp->attached_connector->panel.backlight.controller;
> >
> > I think so, Jani would be best to answer the question about how
> > vbt/panel tie together with backlight and which is meant to be used.
> 
> We discussed this previously, and the following sequence would lead to
> panel.backlight.controller being used uninitialized in
> bxt_power_sequencer_idx because it gets set at
> intel_panel_setup_backlight:
> 
> - intel_edp_init_connector
>   +- intel_dp_pps_init
>   |  +- intel_dp_init_panel_power_sequencer_registers
>   |     +- intel_pps_get_registers
>   |        +- bxt_power_sequencer_idx
>   +- intel_panel_setup_backlight
> 
> I decided it wasn't worth blocking a reasonable fix (that might warrant
> cc: stable actually) on a refactoring. We can (and should) do the
> refactoring later though.

Oh! please ignore the email I just sent...
I hadn't noticed this discussion here before...

So, with this info here:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> BR,
> Jani.
> 
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V4] drm/i915: Enable VBT based BL control for DP

[Mustaffa, Mustamin B]

Hi Ville, 

Can you point out what makes you says the git diff is broken? 

Best regard 

Mustamin


-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
Sent: Tuesday, February 20, 2018 10:26 PM
To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

On Tue, Feb 20, 2018 at 05:42:59PM +0800, Mustamin B Mustaffa wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
> 
> This patch will tell which BXT_PP registers (there are two set of 
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> Timing
> table) and this will enabled eDP backlight controller on MRB (BXT) 
> platform.
> 
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
> V4:
>  - Use sanitized panel backlight controller instead of vbt backlight
>    controller
> 
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> b/drivers/gpu/drm/i915/intel_dp.c index 1868f73..f9b922d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct 
> drm_i915_private *dev_priv)

Your git diff is clearly broken. This makes patch review harder than it has to be. Please consider updating to a non-broken version.

>  {
>  	struct drm_i915_private *dev_priv = 
> to_i915(intel_dp_to_dev(intel_dp));
>  
> +	int backlight_controller = 
> +intel_dp->attached_connector->panel.backlight.controller;
> +
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
>  	/* We should never land here with regular DP ports */
>  	WARN_ON(!intel_dp_is_edp(intel_dp));
>  
> -	/*
> -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> -	 * use instance #0 always.
> -	 */
>  	if (!intel_dp->pps_reset)
> -		return 0;
> +		return backlight_controller;
>  
>  	intel_dp->pps_reset = false;
>  
> @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
>  
> -	return 0;
> +	return backlight_controller;
>  }
>  
>  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> --
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V4] drm/i915: Enable VBT based BL control for DP

[Rodrigo Vivi]

On Wed, Feb 21, 2018 at 12:04:43AM +0000, Mustaffa, Mustamin B wrote:
> Hi Ville, 
> 
> Can you point out what makes you says the git diff is broken? 

Because your diff shows like the change was in vlv_ fucntion,
not on bxt_ one...

If it wasn't by the TODO comment block I'd reply that your code was
wrong. But I opened the code to check myself that TODO was only on
bxt function and that it was only your diff that was broken....

> 
> Best regard 
> 
> Mustamin
> 
> 
> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
> Sent: Tuesday, February 20, 2018 10:26 PM
> To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP
> 
> On Tue, Feb 20, 2018 at 05:42:59PM +0800, Mustamin B Mustaffa wrote:
> > Currently, BXT_PP is hardcoded with value '0'.
> > It practically disabled eDP backlight on MRB (BXT) platform.
> > 
> > This patch will tell which BXT_PP registers (there are two set of 
> > PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> > Timing
> > table) and this will enabled eDP backlight controller on MRB (BXT) 
> > platform.
> > 
> > v2:
> >  - Remove unnecessary information in commit message.
> >  - Assign vbt.backlight.controller to a backlight_controller variable and
> >    return the variable value.
> > v3:
> >  - Rebased to latest code base.
> >  - updated commit title.
> > V4:
> >  - Use sanitized panel backlight controller instead of vbt backlight
> >    controller
> > 
> > Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
> >  1 file changed, 4 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c index 1868f73..f9b922d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct 
> > drm_i915_private *dev_priv)
> 
> Your git diff is clearly broken. This makes patch review harder than it has to be. Please consider updating to a non-broken version.
> 
> >  {
> >  	struct drm_i915_private *dev_priv = 
> > to_i915(intel_dp_to_dev(intel_dp));
> >  
> > +	int backlight_controller = 
> > +intel_dp->attached_connector->panel.backlight.controller;
> > +
> >  	lockdep_assert_held(&dev_priv->pps_mutex);
> >  
> >  	/* We should never land here with regular DP ports */
> >  	WARN_ON(!intel_dp_is_edp(intel_dp));
> >  
> > -	/*
> > -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> > -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> > -	 * use instance #0 always.
> > -	 */
> >  	if (!intel_dp->pps_reset)
> > -		return 0;
> > +		return backlight_controller;
> >  
> >  	intel_dp->pps_reset = false;
> >  
> > @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
> >  	 */
> >  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> >  
> > -	return 0;
> > +	return backlight_controller;
> >  }
> >  
> >  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> > --
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] [V4] drm/i915: Enable VBT based BL control for DP

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controller on MRB (BXT)
platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and
   return the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.
V4:
 - Use sanitized panel backlight controller instead of vbt backlight
   controller

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..b9068bd1943f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller =
+		intel_dp->attached_connector->panel.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +674,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
2.16.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev5)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Series 38559v5 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revisions/5/mbox/

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:414s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:424s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:481s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:284s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:476s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:481s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:462s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:452s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:572s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:416s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:279s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:508s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:384s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:408s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:457s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:409s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:449s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:496s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:491s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:584s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:430s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:519s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:488s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:466s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:408s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:425s
fi-snb-2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:388s

f727568c3b37c1349f635efcc67d64ac3cf77108 drm-tip: 2018y-02m-20d-20h-39m-03s UTC integration manifest
e73e0f3ac45e drm/i915: Enable VBT based BL control for DP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8095/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] [V4] drm/i915: Enable VBT based BL control for DP

[Jani Nikula]

On Wed, 21 Feb 2018, Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com> wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
>
> This patch will tell which BXT_PP registers (there are two set of
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
> table) and this will enabled eDP backlight controller on MRB (BXT)
> platform.
>
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
> V4:
>  - Use sanitized panel backlight controller instead of vbt backlight
>    controller

I thought we concluded in the earlier thread already that it will not be
sanitized or initialized when you actually need it.

BR,
Jani.



>
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1868f73f730c..b9068bd1943f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  
> +	int backlight_controller =
> +		intel_dp->attached_connector->panel.backlight.controller;
> +
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
>  	/* We should never land here with regular DP ports */
>  	WARN_ON(!intel_dp_is_edp(intel_dp));
>  
> -	/*
> -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> -	 * use instance #0 always.
> -	 */
>  	if (!intel_dp->pps_reset)
> -		return 0;
> +		return backlight_controller;
>  
>  	intel_dp->pps_reset = false;
>  
> @@ -676,7 +674,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>  	 */
>  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
>  
> -	return 0;
> +	return backlight_controller;
>  }
>  
>  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev5)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Test kms_cursor_crc:
        Subgroup cursor-256x256-suspend:
                incomplete -> PASS       (shard-hsw) fdo#103375 +1
Test kms_chv_cursor_fail:
        Subgroup pipe-b-256x256-left-edge:
                pass       -> DMESG-WARN (shard-snb) fdo#105185
Test perf:
        Subgroup oa-exponents:
                pass       -> FAIL       (shard-apl) fdo#102254
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252
Test kms_flip:
        Subgroup flip-vs-absolute-wf_vblank-interruptible:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test gem_eio:
        Subgroup in-flight-contexts:
                fail       -> PASS       (shard-hsw) fdo#104676
Test kms_vblank:
        Subgroup pipe-c-wait-idle:
                dmesg-warn -> PASS       (shard-hsw) fdo#102614

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-apl        total:3367 pass:1764 dwarn:1   dfail:0   fail:9   skip:1592 time:11962s
shard-hsw        total:3429 pass:1758 dwarn:1   dfail:0   fail:4   skip:1665 time:11557s
shard-snb        total:3411 pass:1346 dwarn:2   dfail:0   fail:2   skip:2060 time:6284s
Blacklisted hosts:
shard-kbl        total:3429 pass:1902 dwarn:23  dfail:1   fail:10  skip:1493 time:9639s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8095/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V4] drm/i915: Enable VBT based BL control for DP

[Ville Syrjälä]

On Wed, Feb 21, 2018 at 12:04:43AM +0000, Mustaffa, Mustamin B wrote:
> Hi Ville, 
> 
> Can you point out what makes you says the git diff is broken? 
> 
> Best regard 
> 
> Mustamin
> 
> 
> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
> Sent: Tuesday, February 20, 2018 10:26 PM
> To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP
> 
> On Tue, Feb 20, 2018 at 05:42:59PM +0800, Mustamin B Mustaffa wrote:
> > Currently, BXT_PP is hardcoded with value '0'.
> > It practically disabled eDP backlight on MRB (BXT) platform.
> > 
> > This patch will tell which BXT_PP registers (there are two set of 
> > PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> > Timing
> > table) and this will enabled eDP backlight controller on MRB (BXT) 
> > platform.
> > 
> > v2:
> >  - Remove unnecessary information in commit message.
> >  - Assign vbt.backlight.controller to a backlight_controller variable and
> >    return the variable value.
> > v3:
> >  - Rebased to latest code base.
> >  - updated commit title.
> > V4:
> >  - Use sanitized panel backlight controller instead of vbt backlight
> >    controller
> > 
> > Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
> >  1 file changed, 4 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c index 1868f73..f9b922d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct 
                                           ^^^^^^^^^^^^^^^^^

That is not the function you're patching here.

> > drm_i915_private *dev_priv)
> 
> Your git diff is clearly broken. This makes patch review harder than it has to be. Please consider updating to a non-broken version.
> 
> >  {
> >  	struct drm_i915_private *dev_priv = 
> > to_i915(intel_dp_to_dev(intel_dp));
> >  
> > +	int backlight_controller = 
> > +intel_dp->attached_connector->panel.backlight.controller;
> > +
> >  	lockdep_assert_held(&dev_priv->pps_mutex);
> >  
> >  	/* We should never land here with regular DP ports */
> >  	WARN_ON(!intel_dp_is_edp(intel_dp));
> >  
> > -	/*
> > -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> > -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> > -	 * use instance #0 always.
> > -	 */
> >  	if (!intel_dp->pps_reset)
> > -		return 0;
> > +		return backlight_controller;
> >  
> >  	intel_dp->pps_reset = false;
> >  
> > @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
> >  	 */
> >  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> >  
> > -	return 0;
> > +	return backlight_controller;
> >  }
> >  
> >  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> > --
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [V4] drm/i915: Enable VBT based BL control for DP

[Mustaffa, Mustamin B]

Hi Ville, 

I already resubmit the patch https://patchwork.freedesktop.org/patch/205823/ 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..b9068bd1943f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,16 @@  bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller =
+		intel_dp->attached_connector->panel.backlight.controller;
+

Best regard 

Mustamin


-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] 
Sent: Wednesday, February 21, 2018 9:19 PM
To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

On Wed, Feb 21, 2018 at 12:04:43AM +0000, Mustaffa, Mustamin B wrote:
> Hi Ville,
> 
> Can you point out what makes you says the git diff is broken? 
> 
> Best regard
> 
> Mustamin
> 
> 
> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Tuesday, February 20, 2018 10:26 PM
> To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control 
> for DP
> 
> On Tue, Feb 20, 2018 at 05:42:59PM +0800, Mustamin B Mustaffa wrote:
> > Currently, BXT_PP is hardcoded with value '0'.
> > It practically disabled eDP backlight on MRB (BXT) platform.
> > 
> > This patch will tell which BXT_PP registers (there are two set of 
> > PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> > Timing
> > table) and this will enabled eDP backlight controller on MRB (BXT) 
> > platform.
> > 
> > v2:
> >  - Remove unnecessary information in commit message.
> >  - Assign vbt.backlight.controller to a backlight_controller variable and
> >    return the variable value.
> > v3:
> >  - Rebased to latest code base.
> >  - updated commit title.
> > V4:
> >  - Use sanitized panel backlight controller instead of vbt backlight
> >    controller
> > 
> > Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
> >  1 file changed, 4 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c index 1868f73..f9b922d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -655,18 +655,15 @@ static enum pipe vlv_find_free_pps(struct
                                           ^^^^^^^^^^^^^^^^^

That is not the function you're patching here.

> > drm_i915_private *dev_priv)
> 
> Your git diff is clearly broken. This makes patch review harder than it has to be. Please consider updating to a non-broken version.
> 
> >  {
> >  	struct drm_i915_private *dev_priv = 
> > to_i915(intel_dp_to_dev(intel_dp));
> >  
> > +	int backlight_controller = 
> > +intel_dp->attached_connector->panel.backlight.controller;
> > +
> >  	lockdep_assert_held(&dev_priv->pps_mutex);
> >  
> >  	/* We should never land here with regular DP ports */
> >  	WARN_ON(!intel_dp_is_edp(intel_dp));
> >  
> > -	/*
> > -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> > -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> > -	 * use instance #0 always.
> > -	 */
> >  	if (!intel_dp->pps_reset)
> > -		return 0;
> > +		return backlight_controller;
> >  
> >  	intel_dp->pps_reset = false;
> >  
> > @@ -676,7 +673,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
> >  	 */
> >  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
> >  
> > -	return 0;
> > +	return backlight_controller;
> >  }
> >  
> >  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
> > --
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] [V3] drm/i915: Enable VBT based BL control for DP

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controller on MRB (BXT)
platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and
   return the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..b9068bd1943f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller = dev_priv->vbt.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +674,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
2.16.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for drm/i915: Enable VBT based BL control for DP (v3) (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev7)
URL   : https://patchwork.freedesktop.org/series/38559/
State : failure

== Summary ==

Applying: drm/i915: Enable VBT based BL control for DP
error: corrupt patch at line 40
error: could not build fake ancestor
Patch failed at 0001 drm/i915: Enable VBT based BL control for DP
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] [V3] drm/i915: Enable VBT based BL control for DP

[Mustamin B Mustaffa]

Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.

This patch will tell which BXT_PP registers (there are two set of
PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
table) and this will enabled eDP backlight controller on MRB (BXT)
platform.

v2:
 - Remove unnecessary information in commit message.
 - Assign vbt.backlight.controller to a backlight_controller variable and
   return the variable value.
v3:
 - Rebased to latest code base.
 - updated commit title.

Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475a19d76a49..20e3fcd2bf7e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +655,15 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 
+	int backlight_controller = dev_priv->vbt.backlight.controller;
+
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
 	/* We should never land here with regular DP ports */
 	WARN_ON(!intel_dp_is_edp(intel_dp));
 
-	/*
-	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-	 * mapping needs to be retrieved from VBT, for now just hard-code to
-	 * use instance #0 always.
-	 */
 	if (!intel_dp->pps_reset)
-		return 0;
+		return backlight_controller;
 
 	intel_dp->pps_reset = false;
 
@@ -676,7 +673,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 	 */
 	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-	return 0;
+	return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
-- 
2.16.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev8)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

Series 38559v8 drm/i915: Enable VBT based BL control for DP (v3)
https://patchwork.freedesktop.org/api/1.0/series/38559/revisions/8/mbox/

---- Possible new issues:

Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> INCOMPLETE (fi-hsw-4770)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> INCOMPLETE (fi-skl-6260u)

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:423s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:477s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:285s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:477s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:477s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:469s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:453s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:392s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:562s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:575s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:418s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:283s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:504s
fi-hsw-4770      total:108  pass:99   dwarn:0   dfail:0   fail:0   skip:8  
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:414s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:452s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:417s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:449s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:489s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:450s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:492s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:586s
fi-skl-6260u     total:244  pass:227  dwarn:0   dfail:0   fail:0   skip:16 
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:517s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:486s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:476s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:408s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:429s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:522s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:389s

7c50cf4f0dc70112cd82f4475308299df810f302 drm-tip: 2018y-02m-26d-22h-51m-08s UTC integration manifest
926e05a8a5cf drm/i915: Enable VBT based BL control for DP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8168/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Enable VBT based BL control for DP (v3) (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable VBT based BL control for DP (v3) (rev8)
URL   : https://patchwork.freedesktop.org/series/38559/
State : success

== Summary ==

---- Possible new issues:

Test kms_vblank:
        Subgroup pipe-a-query-forked-busy-hang:
                dmesg-warn -> PASS       (shard-hsw)

---- Known issues:

Test drv_suspend:
        Subgroup debugfs-reader:
                pass       -> SKIP       (shard-hsw) k.org#196691
Test kms_chv_cursor_fail:
        Subgroup pipe-b-64x64-bottom-edge:
                dmesg-warn -> PASS       (shard-snb) fdo#105185
Test kms_flip:
        Subgroup flip-vs-absolute-wf_vblank:
                fail       -> PASS       (shard-hsw) fdo#100368 +1
        Subgroup modeset-vs-vblank-race:
                fail       -> PASS       (shard-hsw) fdo#103060
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-pri-indfb-multidraw:
                fail       -> PASS       (shard-apl) fdo#103167
Test kms_sysfs_edid_timing:
                warn       -> PASS       (shard-apl) fdo#100047
Test perf:
        Subgroup oa-exponents:
                pass       -> INCOMPLETE (shard-apl) fdo#102254
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252

k.org#196691 https://bugzilla.kernel.org/show_bug.cgi?id=196691
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apl        total:3431 pass:1801 dwarn:1   dfail:0   fail:7   skip:1621 time:11855s
shard-hsw        total:3460 pass:1764 dwarn:1   dfail:0   fail:3   skip:1691 time:11641s
shard-snb        total:3460 pass:1359 dwarn:1   dfail:0   fail:1   skip:2099 time:6612s
Blacklisted hosts:
shard-kbl        total:3425 pass:1912 dwarn:1   dfail:0   fail:8   skip:1502 time:8930s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8168/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] [V3] drm/i915: Enable VBT based BL control for DP

[Jani Nikula]

On Tue, 27 Feb 2018, Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com> wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
>
> This patch will tell which BXT_PP registers (there are two set of
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios Timing
> table) and this will enabled eDP backlight controller on MRB (BXT)
> platform.
>
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
>
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>

Pushed to dinq, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 475a19d76a49..20e3fcd2bf7e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  
> +	int backlight_controller = dev_priv->vbt.backlight.controller;
> +
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
>  	/* We should never land here with regular DP ports */
>  	WARN_ON(!intel_dp_is_edp(intel_dp));
>  
> -	/*
> -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> -	 * use instance #0 always.
> -	 */
>  	if (!intel_dp->pps_reset)
> -		return 0;
> +		return backlight_controller;
>  
>  	intel_dp->pps_reset = false;
>  
> @@ -676,7 +673,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>  	 */
>  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
>  
> -	return 0;
> +	return backlight_controller;
>  }
>  
>  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] [V3] drm/i915: Enable VBT based BL control for DP

[Mustaffa, Mustamin B]

Thanks Jani. 

Best regard 

Mustamin


-----Original Message-----
From: Jani Nikula [mailto:jani.nikula@linux.intel.com] 
Sent: Wednesday, February 28, 2018 5:42 PM
To: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Mustaffa, Mustamin B <mustamin.b.mustaffa@intel.com>
Subject: Re: [Intel-gfx] [PATCH] [V3] drm/i915: Enable VBT based BL control for DP

On Tue, 27 Feb 2018, Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com> wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
>
> This patch will tell which BXT_PP registers (there are two set of 
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios 
> Timing
> table) and this will enabled eDP backlight controller on MRB (BXT) 
> platform.
>
> v2:
>  - Remove unnecessary information in commit message.
>  - Assign vbt.backlight.controller to a backlight_controller variable and
>    return the variable value.
> v3:
>  - Rebased to latest code base.
>  - updated commit title.
>
> Signed-off-by: Mustamin B Mustaffa <mustamin.b.mustaffa@intel.com>

Pushed to dinq, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> b/drivers/gpu/drm/i915/intel_dp.c index 475a19d76a49..20e3fcd2bf7e 
> 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -655,18 +655,15 @@ bxt_power_sequencer_idx(struct intel_dp 
> *intel_dp)  {
>  	struct drm_i915_private *dev_priv = 
> to_i915(intel_dp_to_dev(intel_dp));
>  
> +	int backlight_controller = dev_priv->vbt.backlight.controller;
> +
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
>  	/* We should never land here with regular DP ports */
>  	WARN_ON(!intel_dp_is_edp(intel_dp));
>  
> -	/*
> -	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
> -	 * mapping needs to be retrieved from VBT, for now just hard-code to
> -	 * use instance #0 always.
> -	 */
>  	if (!intel_dp->pps_reset)
> -		return 0;
> +		return backlight_controller;
>  
>  	intel_dp->pps_reset = false;
>  
> @@ -676,7 +673,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>  	 */
>  	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
>  
> -	return 0;
> +	return backlight_controller;
>  }
>  
>  typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,

--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx