From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zlmgW3JlGzF0QV for ; Tue, 20 Feb 2018 14:43:51 +1100 (AEDT) Received: by mail-pl0-x241.google.com with SMTP id u13so3178733plq.1 for ; Mon, 19 Feb 2018 19:43:51 -0800 (PST) Message-ID: <1519098225.6563.5.camel@gmail.com> Subject: Re: [RFC PATCH 06/12] [WIP] powerpc/tm: Remove dead code from __switch_to_tm() From: Cyril Bur To: Michael Neuling , benh@kernel.crashing.org, linuxppc-dev@lists.ozlabs.org Date: Tue, 20 Feb 2018 14:43:45 +1100 In-Reply-To: <1519095125.7360.54.camel@neuling.org> References: <20180220002241.29648-1-cyrilbur@gmail.com> <20180220002241.29648-7-cyrilbur@gmail.com> <1519095125.7360.54.camel@neuling.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 2018-02-20 at 13:52 +1100, Michael Neuling wrote: > Not sure I understand this.. should it be merged with the last patch? > Its all going to have to be one patch - I've left it split out to make it more obvious which bits have had to mess with, this series absolutely doesn't bisect. > Needs a comment here. > > > On Tue, 2018-02-20 at 11:22 +1100, Cyril Bur wrote: > > --- > > arch/powerpc/kernel/process.c | 24 +++++------------------- > > 1 file changed, 5 insertions(+), 19 deletions(-) > > > > diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c > > index ea75da0fd506..574b05fe7d66 100644 > > --- a/arch/powerpc/kernel/process.c > > +++ b/arch/powerpc/kernel/process.c > > @@ -1027,27 +1027,13 @@ static inline void __switch_to_tm(struct task_struct *prev, > > struct task_struct *new) > > { > > /* > > - * So, with the rework none of this code should not be needed. > > - * I've left in the reclaim for now. This *should* save us > > - * from any mistake in the new code. Also the > > - * enabling/disabling logic of MSR_TM really should be > > + * The enabling/disabling logic of MSR_TM really should be > > * refactored into a common way with MSR_{FP,VEC,VSX} > > */ > > - if (cpu_has_feature(CPU_FTR_TM)) { > > - if (tm_enabled(prev) || tm_enabled(new)) > > - tm_enable(); > > - > > - if (tm_enabled(prev)) { > > - prev->thread.load_tm++; > > - tm_reclaim_task(prev); > > - /* > > - * The disabling logic may be confused don't > > - * disable for now > > - * > > - * if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) > > - * prev->thread.regs->msr &= ~MSR_TM; > > - */ > > - } > > + if (cpu_has_feature(CPU_FTR_TM) && tm_enabled(prev)) { > > + prev->thread.load_tm++; > > + if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) > > + prev->thread.regs->msr &= ~MSR_TM; > > } > > } > >