From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ep10A-0000sP-4r for qemu-devel@nongnu.org; Thu, 22 Feb 2018 19:14:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ep0zc-0004yI-8v for qemu-devel@nongnu.org; Thu, 22 Feb 2018 19:14:14 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:42932) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ep0zb-0004wU-V4 for qemu-devel@nongnu.org; Thu, 22 Feb 2018 19:13:40 -0500 Received: by mail-pg0-x241.google.com with SMTP id y8so2663099pgr.9 for ; Thu, 22 Feb 2018 16:13:39 -0800 (PST) From: Michael Clark Date: Fri, 23 Feb 2018 13:11:48 +1300 Message-Id: <1519344729-73482-3-git-send-email-mjc@sifive.com> In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com> References: <1519344729-73482-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v6 02/23] RISC-V ELF Machine Definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann , RISC-V Patches Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 --- a/include/elf.h +++ b/include/elf.h @@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword; #define EM_UNICORE32 110 /* UniCore32 */ +#define EM_RISCV 243 /* RISC-V */ + /* * This is an interim value that we will use until the committee comes * up with a final number. -- 2.7.0