* [PATCH 0/7] meson build support for dpaaX
@ 2018-02-27 17:25 Hemant Agrawal
2018-02-27 17:25 ` [PATCH 1/7] event/dpaa: fix include header Hemant Agrawal
` (7 more replies)
0 siblings, 8 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain
This patch series enables the meson build support for dpaa
and dpaa2 platforms.
Earlier dpaaX was only compiled for armv8 target. This patch
series first prepares the dpaaX drivers to be compiled for
non-ARM platform as well.
Hemant Agrawal (7):
event/dpaa: fix include header
dpaa: prepare for 32 bit compilation
dpaa2: prepare for 32 bit compilation
bus/fslmc: add 32 bit functional support for ARM
bus/dpaa: enabling dpaa compilation for other platforms
bus/fslmc: enabling dpaa2 compilation for other platforms
build: add meson support for dpaaX platforms
app/test-pmd/meson.build | 3 ++
config/arm/arm64_dpaa2_linuxapp_gcc | 13 +++++++
config/arm/arm64_dpaa_linuxapp_gcc | 14 +++++++
config/arm/meson.build | 13 +++++++
drivers/bus/dpaa/base/fman/fman.c | 2 +-
drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +-
drivers/bus/dpaa/base/qbman/qman.c | 5 ++-
drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +--
drivers/bus/dpaa/dpaa_bus.c | 2 +-
drivers/bus/dpaa/include/compat.h | 30 ++++++++++++++-
drivers/bus/dpaa/meson.build | 29 ++++++++++++++
drivers/bus/fslmc/fslmc_vfio.c | 10 ++---
drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-
drivers/bus/fslmc/meson.build | 28 ++++++++++++++
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 4 +-
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++++++---------
drivers/bus/fslmc/qbman/qbman_portal.c | 14 +++----
drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++++++++-
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 23 +++++++++++
drivers/bus/meson.build | 4 +-
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 60 ++++++++++++++---------------
drivers/crypto/dpaa2_sec/meson.build | 16 ++++++++
drivers/crypto/dpaa_sec/dpaa_sec.c | 30 +++++++--------
drivers/crypto/dpaa_sec/meson.build | 16 ++++++++
drivers/crypto/meson.build | 3 ++
drivers/event/dpaa/dpaa_eventdev.c | 2 +-
drivers/event/dpaa/meson.build | 11 ++++++
drivers/event/dpaa2/dpaa2_eventdev.c | 6 +--
drivers/event/dpaa2/meson.build | 12 ++++++
drivers/event/meson.build | 2 +-
drivers/mempool/dpaa/dpaa_mempool.c | 10 ++---
drivers/mempool/dpaa/dpaa_mempool.h | 2 +-
drivers/mempool/dpaa/meson.build | 9 +++++
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 ++--
drivers/mempool/dpaa2/meson.build | 9 +++++
drivers/mempool/meson.build | 2 +-
drivers/net/dpaa/dpaa_rxtx.c | 17 ++++----
drivers/net/dpaa/meson.build | 15 ++++++++
drivers/net/dpaa2/Makefile | 1 -
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +-
drivers/net/dpaa2/dpaa2_ethdev.c | 6 +--
drivers/net/dpaa2/dpaa2_rxtx.c | 38 ++++++++----------
drivers/net/dpaa2/meson.build | 16 ++++++++
drivers/net/meson.build | 2 +-
44 files changed, 418 insertions(+), 147 deletions(-)
create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
create mode 100644 drivers/bus/dpaa/meson.build
create mode 100644 drivers/bus/fslmc/meson.build
create mode 100644 drivers/crypto/dpaa2_sec/meson.build
create mode 100644 drivers/crypto/dpaa_sec/meson.build
create mode 100644 drivers/event/dpaa/meson.build
create mode 100644 drivers/event/dpaa2/meson.build
create mode 100644 drivers/mempool/dpaa/meson.build
create mode 100644 drivers/mempool/dpaa2/meson.build
create mode 100644 drivers/net/dpaa/meson.build
create mode 100644 drivers/net/dpaa2/meson.build
--
2.7.4
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 1/7] event/dpaa: fix include header
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-27 17:25 ` [PATCH 2/7] dpaa: prepare for 32 bit compilation Hemant Agrawal
` (6 subsequent siblings)
7 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain, stable
rte_cycles.h shall be included instead of rte_cycles_64.h
dpaa_eventdev.c:32:27:
fatal error: rte_cycles_64.h: No such file or directory
Fixes: 9caac5dd1e7f ("event/dpaa: introduce PMD")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/event/dpaa/dpaa_eventdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
index 0006801..cd13d0c 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -29,7 +29,7 @@
#include <rte_event_eth_rx_adapter.h>
#include <rte_dpaa_bus.h>
#include <rte_dpaa_logs.h>
-#include <rte_cycles_64.h>
+#include <rte_cycles.h>
#include <dpaa_ethdev.h>
#include "dpaa_eventdev.h"
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 2/7] dpaa: prepare for 32 bit compilation
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
2018-02-27 17:25 ` [PATCH 1/7] event/dpaa: fix include header Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-27 17:25 ` [PATCH 3/7] dpaa2: " Hemant Agrawal
` (5 subsequent siblings)
7 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain
This patch prepares the dpaa drivers for compilation on 32 bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/base/fman/fman.c | 2 +-
drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +-
drivers/bus/dpaa/base/qbman/qman.c | 5 +++--
drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +----
drivers/bus/dpaa/dpaa_bus.c | 2 +-
drivers/crypto/dpaa_sec/dpaa_sec.c | 30 +++++++++++++++---------------
drivers/mempool/dpaa/dpaa_mempool.c | 10 +++++-----
drivers/mempool/dpaa/dpaa_mempool.h | 2 +-
drivers/net/dpaa/dpaa_rxtx.c | 17 ++++++++---------
9 files changed, 36 insertions(+), 39 deletions(-)
diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c
index bda62e0..e6fd5f3 100644
--- a/drivers/bus/dpaa/base/fman/fman.c
+++ b/drivers/bus/dpaa/base/fman/fman.c
@@ -300,7 +300,7 @@ fman_if_init(const struct device_node *dpa_node)
_errno = fman_get_mac_index(regs_addr_host, &__if->__if.mac_idx);
if (_errno) {
- FMAN_ERR(-EINVAL, "Invalid register address: %lu",
+ FMAN_ERR(-EINVAL, "Invalid register address: %" PRIx64,
regs_addr_host);
goto err;
}
diff --git a/drivers/bus/dpaa/base/qbman/bman_driver.c b/drivers/bus/dpaa/base/qbman/bman_driver.c
index a1ef392..1381da3 100644
--- a/drivers/bus/dpaa/base/qbman/bman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/bman_driver.c
@@ -161,7 +161,7 @@ int bman_init_ccsr(const struct device_node *node)
PROT_WRITE, MAP_SHARED, ccsr_map_fd, phys_addr);
if (bman_ccsr_map == MAP_FAILED) {
pr_err("Can not map BMan CCSR base Bman: "
- "0x%x Phys: 0x%lx size 0x%lx",
+ "0x%x Phys: 0x%" PRIx64 " size 0x%" PRIu64,
*bman_addr, phys_addr, regs_size);
return -EINVAL;
}
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 2b97671..2810fdd 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -1087,7 +1087,7 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
shadow[rx_number]->fd.opaque =
be32_to_cpu(dq[rx_number]->fd.opaque);
#else
- shadow = dq;
+ shadow[rx_number] = dq[rx_number];
#endif
/* SDQCR: context_b points to the FQ */
@@ -1095,7 +1095,8 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
fq[rx_number] = qman_fq_lookup_table[be32_to_cpu(
dq[rx_number]->contextB)];
#else
- fq[rx_number] = (void *)(uintptr_t)be32_to_cpu(dq->contextB);
+ fq[rx_number] = (void *)be32_to_cpu(
+ dq[rx_number]->contextB);
#endif
fq[rx_number]->cb.dqrr_prepare(shadow[rx_number],
&bufs[rx_number]);
diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c
index 7cfa8ee..66838d2 100644
--- a/drivers/bus/dpaa/base/qbman/qman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/qman_driver.c
@@ -246,7 +246,6 @@ int fsl_qman_portal_destroy(struct qman_portal *qp)
int qman_global_init(void)
{
const struct device_node *dt_node;
- int ret = 0;
size_t lenp;
const u32 *chanid;
static int ccsr_map_fd;
@@ -352,9 +351,7 @@ int qman_global_init(void)
qman_clk = be32_to_cpu(*clk);
#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
- ret = qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX);
- if (ret)
- return ret;
+ return qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX);
#endif
return 0;
}
diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index f2bb3b1..c643da5 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -235,7 +235,7 @@ int rte_dpaa_portal_init(void *arg)
BUS_INIT_FUNC_TRACE();
- if ((uint64_t)arg == 1 || cpu == LCORE_ID_ANY)
+ if ((size_t)arg == 1 || cpu == LCORE_ID_ANY)
cpu = rte_get_master_lcore();
/* if the core id is not supported */
else
diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 18681cf..c5191ce 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -84,7 +84,7 @@ dpaa_sec_alloc_ctx(dpaa_sec_session *ses)
dcbz_64(&ctx->job.sg[SG_CACHELINE_3]);
ctx->ctx_pool = ses->ctx_pool;
- ctx->vtop_offset = (uint64_t) ctx
+ ctx->vtop_offset = (size_t) ctx
- rte_mempool_virt2iova(ctx);
return ctx;
@@ -97,7 +97,7 @@ dpaa_mem_vtop(void *vaddr)
uint64_t vaddr_64, paddr;
int i;
- vaddr_64 = (uint64_t)vaddr;
+ vaddr_64 = (size_t)vaddr;
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (vaddr_64 >= memseg[i].addr_64 &&
vaddr_64 < memseg[i].addr_64 + memseg[i].len) {
@@ -107,14 +107,14 @@ dpaa_mem_vtop(void *vaddr)
return (rte_iova_t)paddr;
}
}
- return (rte_iova_t)(NULL);
+ return (size_t)NULL;
}
/* virtual address conversin when mempool support is available for ctx */
static inline phys_addr_t
dpaa_mem_vtop_ctx(struct dpaa_sec_op_ctx *ctx, void *vaddr)
{
- return (uint64_t)vaddr - ctx->vtop_offset;
+ return (size_t)vaddr - ctx->vtop_offset;
}
static inline void *
@@ -125,8 +125,8 @@ dpaa_mem_ptov(rte_iova_t paddr)
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (paddr >= memseg[i].iova &&
- (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
- return (void *)(memseg[i].addr_64 +
+ paddr < memseg[i].iova + memseg[i].len)
+ return (void *)(size_t)(memseg[i].addr_64 +
(paddr - memseg[i].iova));
}
return NULL;
@@ -406,7 +406,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_c.key = (uint64_t)ses->cipher_key.data;
+ alginfo_c.key = (size_t)ses->cipher_key.data;
alginfo_c.keylen = ses->cipher_key.length;
alginfo_c.key_enc_flags = 0;
alginfo_c.key_type = RTA_DATA_IMM;
@@ -424,7 +424,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_a.key = (uint64_t)ses->auth_key.data;
+ alginfo_a.key = (size_t)ses->auth_key.data;
alginfo_a.keylen = ses->auth_key.length;
alginfo_a.key_enc_flags = 0;
alginfo_a.key_type = RTA_DATA_IMM;
@@ -439,7 +439,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
PMD_TX_LOG(ERR, "not supported aead alg\n");
return -ENOTSUP;
}
- alginfo.key = (uint64_t)ses->aead_key.data;
+ alginfo.key = (size_t)ses->aead_key.data;
alginfo.keylen = ses->aead_key.length;
alginfo.key_enc_flags = 0;
alginfo.key_type = RTA_DATA_IMM;
@@ -463,7 +463,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_c.key = (uint64_t)ses->cipher_key.data;
+ alginfo_c.key = (size_t)ses->cipher_key.data;
alginfo_c.keylen = ses->cipher_key.length;
alginfo_c.key_enc_flags = 0;
alginfo_c.key_type = RTA_DATA_IMM;
@@ -474,7 +474,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_a.key = (uint64_t)ses->auth_key.data;
+ alginfo_a.key = (size_t)ses->auth_key.data;
alginfo_a.keylen = ses->auth_key.length;
alginfo_a.key_enc_flags = 0;
alginfo_a.key_type = RTA_DATA_IMM;
@@ -493,15 +493,15 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
if (cdb->sh_desc[2] & 1)
alginfo_c.key_type = RTA_DATA_IMM;
else {
- alginfo_c.key = (uint64_t)dpaa_mem_vtop(
- (void *)alginfo_c.key);
+ alginfo_c.key = (size_t)dpaa_mem_vtop(
+ (void *)(size_t)alginfo_c.key);
alginfo_c.key_type = RTA_DATA_PTR;
}
if (cdb->sh_desc[2] & (1<<1))
alginfo_a.key_type = RTA_DATA_IMM;
else {
- alginfo_a.key = (uint64_t)dpaa_mem_vtop(
- (void *)alginfo_a.key);
+ alginfo_a.key = (size_t)dpaa_mem_vtop(
+ (void *)(size_t)alginfo_a.key);
alginfo_a.key_type = RTA_DATA_PTR;
}
cdb->sh_desc[0] = 0;
diff --git a/drivers/mempool/dpaa/dpaa_mempool.c b/drivers/mempool/dpaa/dpaa_mempool.c
index fb3b6ba..7b82f4b 100644
--- a/drivers/mempool/dpaa/dpaa_mempool.c
+++ b/drivers/mempool/dpaa/dpaa_mempool.c
@@ -115,7 +115,8 @@ dpaa_buf_free(struct dpaa_bp_info *bp_info, uint64_t addr)
struct bm_buffer buf;
int ret;
- DPAA_MEMPOOL_DEBUG("Free 0x%lx to bpid: %d", addr, bp_info->bpid);
+ DPAA_MEMPOOL_DEBUG("Free 0x%" PRIx64 " to bpid: %d",
+ addr, bp_info->bpid);
bm_buffer_set64(&buf, addr);
retry:
@@ -154,8 +155,7 @@ dpaa_mbuf_free_bulk(struct rte_mempool *pool,
if (unlikely(!bp_info->ptov_off)) {
/* buffers are from single mem segment */
if (bp_info->flags & DPAA_MPOOL_SINGLE_SEGMENT) {
- bp_info->ptov_off
- = (uint64_t)obj_table[i] - phy;
+ bp_info->ptov_off = (size_t)obj_table[i] - phy;
rte_dpaa_bpid_info[bp_info->bpid].ptov_off
= bp_info->ptov_off;
}
@@ -282,8 +282,8 @@ dpaa_register_memory_area(const struct rte_mempool *mp,
bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;
- DPAA_MEMPOOL_DEBUG("Req size %lu vs Available %u\n",
- len, total_elt_sz * mp->size);
+ DPAA_MEMPOOL_DEBUG("Req size %" PRIx64 " vs Available %u\n",
+ (uint64_t)len, total_elt_sz * mp->size);
/* Detect pool area has sufficient space for elements in this memzone */
if (len >= total_elt_sz * mp->size)
diff --git a/drivers/mempool/dpaa/dpaa_mempool.h b/drivers/mempool/dpaa/dpaa_mempool.h
index 9435dd2..092f326 100644
--- a/drivers/mempool/dpaa/dpaa_mempool.h
+++ b/drivers/mempool/dpaa/dpaa_mempool.h
@@ -46,7 +46,7 @@ static inline void *
DPAA_MEMPOOL_PTOV(struct dpaa_bp_info *bp_info, uint64_t addr)
{
if (bp_info->ptov_off)
- return ((void *)(addr + bp_info->ptov_off));
+ return ((void *) (size_t)(addr + bp_info->ptov_off));
return rte_dpaa_mem_ptov(addr);
}
diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 0dea8e7..8d53137 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -90,11 +90,10 @@ static inline void dpaa_slow_parsing(struct rte_mbuf *m __rte_unused,
/*TBD:XXX: to be implemented*/
}
-static inline void dpaa_eth_packet_info(struct rte_mbuf *m,
- uint64_t fd_virt_addr)
+static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
{
struct annotations_t *annot = GET_ANNOTATIONS(fd_virt_addr);
- uint64_t prs = *((uint64_t *)(&annot->parse)) & DPAA_PARSE_MASK;
+ uint64_t prs = *((uintptr_t *)(&annot->parse)) & DPAA_PARSE_MASK;
DPAA_DP_LOG(DEBUG, " Parsing mbuf: %p with annotations: %p", m, annot);
@@ -351,7 +350,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
prev_seg = cur_seg;
}
- dpaa_eth_packet_info(first_seg, (uint64_t)vaddr);
+ dpaa_eth_packet_info(first_seg, vaddr);
rte_pktmbuf_free_seg(temp);
return first_seg;
@@ -394,7 +393,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
mbuf->ol_flags = 0;
mbuf->next = NULL;
rte_mbuf_refcnt_set(mbuf, 1);
- dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
return mbuf;
}
@@ -455,7 +454,7 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
mbuf->ol_flags = 0;
mbuf->next = NULL;
rte_mbuf_refcnt_set(mbuf, 1);
- dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
}
}
@@ -593,7 +592,7 @@ uint16_t dpaa_eth_queue_rx(void *q,
static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info)
{
int ret;
- uint64_t buf = 0;
+ size_t buf = 0;
struct bm_buffer bufs;
ret = bman_acquire(bp_info->bp, &bufs, 1, 0);
@@ -602,10 +601,10 @@ static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info)
return (void *)buf;
}
- DPAA_DP_LOG(DEBUG, "got buffer 0x%lx from pool %d",
+ DPAA_DP_LOG(DEBUG, "got buffer 0x%" PRIx64 " from pool %d",
(uint64_t)bufs.addr, bufs.bpid);
- buf = (uint64_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr)
+ buf = (size_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr)
- bp_info->meta_data_size;
if (!buf)
goto out;
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 3/7] dpaa2: prepare for 32 bit compilation
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
2018-02-27 17:25 ` [PATCH 1/7] event/dpaa: fix include header Hemant Agrawal
2018-02-27 17:25 ` [PATCH 2/7] dpaa: prepare for 32 bit compilation Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-27 17:25 ` [PATCH 4/7] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
` (4 subsequent siblings)
7 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain
This patch prepare the dpaa2 drivers for compilation on 32 bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/fslmc_vfio.c | 10 ++---
drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 4 +-
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++++++---------
drivers/bus/fslmc/qbman/qbman_portal.c | 14 +++----
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 60 ++++++++++++++---------------
drivers/event/dpaa2/dpaa2_eventdev.c | 6 +--
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 ++--
drivers/net/dpaa2/Makefile | 1 -
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +-
drivers/net/dpaa2/dpaa2_ethdev.c | 6 +--
drivers/net/dpaa2/dpaa2_rxtx.c | 38 ++++++++----------
12 files changed, 90 insertions(+), 98 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 1241295..e840ad6 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -76,7 +76,7 @@ fslmc_get_container_group(int *groupid)
if (!g_container) {
container = getenv("DPRC");
if (container == NULL) {
- RTE_LOG(WARNING, EAL, "DPAA2: DPRC not available\n");
+ RTE_LOG(DEBUG, EAL, "DPAA2: DPRC not available\n");
return -EINVAL;
}
@@ -270,7 +270,7 @@ int rte_fslmc_vfio_dmamap(void)
static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
{
- int64_t v_addr = (int64_t)MAP_FAILED;
+ intptr_t v_addr = (intptr_t)MAP_FAILED;
int32_t ret, mc_fd;
struct vfio_device_info d_info = { .argsz = sizeof(d_info) };
@@ -301,7 +301,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
FSLMC_VFIO_LOG(DEBUG, "region offset = %llx , region size = %llx",
reg_info.offset, reg_info.size);
- v_addr = (uint64_t)mmap(NULL, reg_info.size,
+ v_addr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
mc_fd, reg_info.offset);
@@ -469,7 +469,7 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev)
static int
fslmc_process_mcp(struct rte_dpaa2_device *dev)
{
- int64_t v_addr;
+ intptr_t v_addr;
char *dev_name;
struct fsl_mc_io dpmng = {0};
struct mc_version mc_ver_info = {0};
@@ -489,7 +489,7 @@ fslmc_process_mcp(struct rte_dpaa2_device *dev)
}
v_addr = vfio_map_mcp_obj(&vfio_group, dev_name);
- if (v_addr == (int64_t)MAP_FAILED) {
+ if (v_addr == (intptr_t)MAP_FAILED) {
FSLMC_VFIO_LOG(ERR, "Error mapping region (errno = %d)",
errno);
free(rte_mcp_ptr_list);
diff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h
index a3c3e79..ac91961 100644
--- a/drivers/bus/fslmc/mc/fsl_mc_cmd.h
+++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h
@@ -27,7 +27,7 @@
#define le32_to_cpu rte_le_to_cpu_32
#define le16_to_cpu rte_le_to_cpu_16
-#define BITS_PER_LONG 64
+#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
#define GENMASK(h, l) \
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index eefde15..9bbc219 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -427,7 +427,7 @@ dpaa2_create_dpio_device(int vdev_fd,
}
dpio_dev->ce_size = reg_info.size;
- dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
+ dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
vdev_fd, reg_info.offset);
@@ -439,7 +439,7 @@ dpaa2_create_dpio_device(int vdev_fd,
}
dpio_dev->ci_size = reg_info.size;
- dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
+ dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
vdev_fd, reg_info.offset);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index d421dbf..3191ead 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -174,7 +174,7 @@ enum qbman_fd_format {
};
/*Macros to define operations on FD*/
#define DPAA2_SET_FD_ADDR(fd, addr) do { \
- (fd)->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
+ (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
(fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
} while (0)
#define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
@@ -193,33 +193,32 @@ enum qbman_fd_format {
#define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
#define DPAA2_SET_FD_FLC(fd, addr) do { \
- (fd)->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
+ (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
(fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
} while (0)
#define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
#define DPAA2_GET_FLE_ADDR(fle) \
(uint64_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
#define DPAA2_SET_FLE_ADDR(fle, addr) do { \
- (fle)->addr_lo = lower_32_bits((uint64_t)addr); \
- (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
+ (fle)->addr_lo = lower_32_bits((size_t)addr); \
+ (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
} while (0)
#define DPAA2_GET_FLE_CTXT(fle) \
- (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \
- (fle)->reserved[0])
+ ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
#define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
- (fle)->reserved[0] = lower_32_bits((uint64_t)addr); \
- (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
+ (fle)->reserved[0] = lower_32_bits((size_t)addr); \
+ (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
} while (0)
#define DPAA2_SET_FLE_OFFSET(fle, offset) \
((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
-#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
+#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
#define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
-#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 31)
+#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
#define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
#define DPAA2_SET_FD_COMPOUND_FMT(fd) \
((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
#define DPAA2_GET_FD_ADDR(fd) \
-((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
+((size_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
#define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
#define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
@@ -231,7 +230,7 @@ enum qbman_fd_format {
(((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
#define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
- ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
+ ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
#define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
@@ -265,14 +264,14 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr)
int i;
if (dpaa2_virt_mode)
- return (void *)paddr;
+ return (void *)(size_t)paddr;
memseg = rte_eal_get_physmem_layout();
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (paddr >= memseg[i].iova &&
- (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
- return (void *)(memseg[i].addr_64
+ paddr < memseg[i].iova + memseg[i].len)
+ return (void *)(size_t)(memseg[i].addr_64
+ (paddr - memseg[i].iova));
}
return NULL;
@@ -295,7 +294,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
return memseg[i].iova
+ (vaddr - memseg[i].addr_64);
}
- return (phys_addr_t)(NULL);
+ return (size_t)(NULL);
}
/**
@@ -311,18 +310,18 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
/**
* macro to convert Virtual address to IOVA
*/
-#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
+#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
/**
* macro to convert IOVA to Virtual address
*/
-#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
+#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
/**
* macro to convert modify the memory containing IOVA to Virtual address
*/
#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
- {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
+ {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
#else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c
index e221733..713ec96 100644
--- a/drivers/bus/fslmc/qbman/qbman_portal.c
+++ b/drivers/bus/fslmc/qbman/qbman_portal.c
@@ -553,10 +553,9 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s,
/* Flush all the cacheline without load/store in between */
eqcr_pi = s->eqcr.pi;
- addr_cena = (uint64_t)s->sys.addr_cena;
+ addr_cena = (size_t)s->sys.addr_cena;
for (i = 0; i < num_enqueued; i++) {
- dcbf((uint64_t *)(addr_cena +
- QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
eqcr_pi++;
eqcr_pi &= 0xF;
}
@@ -620,10 +619,9 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
/* Flush all the cacheline without load/store in between */
eqcr_pi = s->eqcr.pi;
- addr_cena = (uint64_t)s->sys.addr_cena;
+ addr_cena = (size_t)s->sys.addr_cena;
for (i = 0; i < num_enqueued; i++) {
- dcbf((uint64_t *)(addr_cena +
- QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
eqcr_pi++;
eqcr_pi &= 0xF;
}
@@ -690,7 +688,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
dma_addr_t storage_phys,
int stash)
{
- d->pull.rsp_addr_virt = (uint64_t)storage;
+ d->pull.rsp_addr_virt = (size_t)storage;
if (!storage) {
d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
@@ -749,7 +747,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
}
d->pull.tok = s->sys.idx + 1;
- s->vdq.storage = (void *)d->pull.rsp_addr_virt;
+ s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt;
p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
memcpy(&p[1], &cl[1], 12);
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 9a790dd..a7f3b04 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -77,11 +77,11 @@ build_proto_fd(dpaa2_sec_session *sess,
DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
DPAA2_SET_FD_OFFSET(fd, sym_op->m_src->data_off);
DPAA2_SET_FD_LEN(fd, sym_op->m_src->pkt_len);
- DPAA2_SET_FD_FLC(fd, ((uint64_t)flc));
+ DPAA2_SET_FD_FLC(fd, (ptrdiff_t)flc);
/* save physical address of mbuf */
op->sym->aead.digest.phys_addr = mbuf->buf_iova;
- mbuf->buf_iova = (uint64_t)op;
+ mbuf->buf_iova = (size_t)op;
return 0;
}
@@ -118,7 +118,7 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_SG_MEM_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -269,7 +269,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_POOL_BUF_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
if (likely(bpid < MAX_BPID)) {
@@ -414,7 +414,7 @@ build_authenc_sg_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_SG_MEM_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -563,7 +563,7 @@ build_authenc_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_POOL_BUF_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
if (likely(bpid < MAX_BPID)) {
@@ -692,7 +692,7 @@ static inline int build_auth_sg_fd(
memset(fle, 0, FLE_SG_MEM_SIZE);
/* first FLE entry used to store mbuf and session ctxt */
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
sge = fle + 3;
@@ -773,7 +773,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
* We can have a better approach to use the inline Mbuf
*/
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
if (likely(bpid < MAX_BPID)) {
@@ -865,7 +865,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
memset(fle, 0, FLE_SG_MEM_SIZE);
/* first FLE entry used to store mbuf and session ctxt */
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -987,7 +987,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
* We can have a better approach to use the inline Mbuf
*/
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
@@ -1206,7 +1206,7 @@ sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id)
DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
- op = (struct rte_crypto_op *)mbuf->buf_iova;
+ op = (struct rte_crypto_op *)(size_t)mbuf->buf_iova;
mbuf->buf_iova = op->sym->aead.digest.phys_addr;
op->sym->aead.digest.phys_addr = 0L;
@@ -1276,7 +1276,7 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id)
/* free the fle memory */
if (likely(rte_pktmbuf_is_contiguous(src))) {
- priv = (struct ctxt_priv *)DPAA2_GET_FLE_CTXT(fle - 1);
+ priv = (struct ctxt_priv *)(size_t)DPAA2_GET_FLE_CTXT(fle - 1);
rte_mempool_put(priv->fle_pool, (void *)(fle-1));
} else
rte_free((void *)(fle-1));
@@ -1455,7 +1455,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
dev->data->queue_pairs[qp_id] = qp;
cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;
- cfg.user_ctx = (uint64_t)(&qp->rx_vq);
+ cfg.user_ctx = (size_t)(&qp->rx_vq);
retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,
qp_id, &cfg);
return retcode;
@@ -1536,7 +1536,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
memcpy(session->cipher_key.data, xform->cipher.key.data,
xform->cipher.key.length);
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -1595,10 +1595,10 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
@@ -1651,7 +1651,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, xform->auth.key.data,
xform->auth.key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -1720,10 +1720,10 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -1786,7 +1786,7 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev,
session->aead_key.length = aead_xform->key.length;
ctxt->auth_only_len = aead_xform->aad_length;
- aeaddata.key = (uint64_t)session->aead_key.data;
+ aeaddata.key = (size_t)session->aead_key.data;
aeaddata.keylen = session->aead_key.length;
aeaddata.key_enc_flags = 0;
aeaddata.key_type = RTA_DATA_IMM;
@@ -1840,10 +1840,10 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev,
session->digest_length);
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -1928,7 +1928,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, auth_xform->key.data,
auth_xform->key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -1988,7 +1988,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
auth_xform->algo);
goto error_out;
}
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -2066,10 +2066,10 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -2202,7 +2202,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, auth_xform->key.data,
auth_xform->key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -2261,7 +2261,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
auth_xform->algo);
goto out;
}
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -2345,10 +2345,10 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
/* Enable the stashing control bit */
DPAA2_SET_FLC_RSC(flc);
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq) | 0x14);
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
/* Set EWS bit i.e. enable write-safe */
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index c3e6fbf..9bdc014 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -126,7 +126,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
goto send_partial;
}
rte_memcpy(ev_temp, event, sizeof(struct rte_event));
- DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
+ DPAA2_SET_FD_ADDR((&fd_arr[loop]), (size_t)ev_temp);
DPAA2_SET_FD_LEN((&fd_arr[loop]),
sizeof(struct rte_event));
}
@@ -258,7 +258,7 @@ dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
qbman_swp_prefetch_dqrr_next(swp);
fd = qbman_result_DQ_fd(dq);
- rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
+ rxq = (struct dpaa2_queue *)(size_t)qbman_result_DQ_fqd_ctx(dq);
if (rxq) {
rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
} else {
@@ -736,7 +736,7 @@ dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
dpaa2_eventdev_process_atomic;
for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
- rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
+ rx_queue_cfg.user_ctx = (size_t)(&dpci_dev->queue[i]);
ret = dpci_set_rx_queue(&dpci_dev->dpci,
CMD_PRI_LOW,
dpci_dev->token, i,
diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
index 2bd62e8..1a618ae 100644
--- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
+++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
@@ -242,7 +242,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
#endif
struct qbman_swp *swp;
uint16_t bpid;
- uint64_t bufs[DPAA2_MBUF_MAX_ACQ_REL];
+ size_t bufs[DPAA2_MBUF_MAX_ACQ_REL];
int i, ret;
unsigned int n = 0;
struct dpaa2_bp_info *bp_info;
@@ -270,10 +270,10 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
* then the remainder.
*/
if ((count - n) > DPAA2_MBUF_MAX_ACQ_REL) {
- ret = qbman_swp_acquire(swp, bpid, bufs,
+ ret = qbman_swp_acquire(swp, bpid, (void *)bufs,
DPAA2_MBUF_MAX_ACQ_REL);
} else {
- ret = qbman_swp_acquire(swp, bpid, bufs,
+ ret = qbman_swp_acquire(swp, bpid, (void *)bufs,
count - n);
}
/* In case of less than requested number of buffers available
@@ -290,7 +290,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
}
/* assigning mbuf from the acquired objects */
for (i = 0; (i < ret) && bufs[i]; i++) {
- DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], uint64_t);
+ DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], size_t);
obj_table[n] = (struct rte_mbuf *)
(bufs[i] - bp_info->meta_data_size);
PMD_TX_LOG(DEBUG, "Acquired %p address %p from BMAN",
diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile
index 5a93a0b..068e9d3 100644
--- a/drivers/net/dpaa2/Makefile
+++ b/drivers/net/dpaa2/Makefile
@@ -25,7 +25,6 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include
CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc
CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal
CFLAGS += -I$(RTE_SDK)/drivers/mempool/dpaa2
-CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2
CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
# versioning export map
diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
index b93376d..4b60f56 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
@@ -50,7 +50,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg);
if (ret) {
- PMD_INIT_LOG(ERR, "given rss_hf (%lx) not supported",
+ PMD_INIT_LOG(ERR, "given rss_hf (%" PRIx64 ") not supported",
req_dist_set);
rte_free(p_params);
return ret;
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 09a11d6..fd5897e 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -445,7 +445,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
memset(&cfg, 0, sizeof(struct dpni_queue));
options = options | DPNI_QUEUE_OPT_USER_CTX;
- cfg.user_context = (uint64_t)(dpaa2_q);
+ cfg.user_context = (size_t)(dpaa2_q);
/*if ls2088 or rev2 device, enable the stashing */
@@ -560,7 +560,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
*/
cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
cong_notif_cfg.message_ctx = 0;
- cong_notif_cfg.message_iova = (uint64_t)dpaa2_q->cscn;
+ cong_notif_cfg.message_iova = (size_t)dpaa2_q->cscn;
cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
cong_notif_cfg.notification_mode =
DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
@@ -1702,7 +1702,7 @@ int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
}
options |= DPNI_QUEUE_OPT_USER_CTX;
- cfg.user_context = (uint64_t)(dpaa2_ethq);
+ cfg.user_context = (size_t)(dpaa2_ethq);
ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
dpaa2_ethq->tc_index, flow_id, options, &cfg);
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 183293c..f33b1fd 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -21,7 +21,6 @@
#include <dpaa2_hw_pvt.h>
#include <dpaa2_hw_dpio.h>
#include <dpaa2_hw_mempool.h>
-#include <dpaa2_eventdev.h>
#include "dpaa2_ethdev.h"
#include "base/dpaa2_hw_dpni_annot.h"
@@ -104,11 +103,9 @@ dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc)
}
static inline uint32_t __attribute__((hot))
-dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
+dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation)
{
uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
- struct dpaa2_annot_hdr *annotation =
- (struct dpaa2_annot_hdr *)hw_annot_addr;
PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4);
if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
@@ -167,7 +164,7 @@ dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
}
static inline uint32_t __attribute__((hot))
-dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
+dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
{
struct dpaa2_annot_hdr *annotation =
(struct dpaa2_annot_hdr *)hw_annot_addr;
@@ -207,25 +204,24 @@ dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
break;
}
- return dpaa2_dev_rx_parse_slow(hw_annot_addr);
+ return dpaa2_dev_rx_parse_slow(annotation);
}
static inline struct rte_mbuf *__attribute__((hot))
eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
{
struct qbman_sge *sgt, *sge;
- dma_addr_t sg_addr;
+ size_t sg_addr, fd_addr;
int i = 0;
- uint64_t fd_addr;
struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
- fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
+ fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
/* Get Scatter gather table address */
sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
sge = &sgt[i++];
- sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
+ sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
/* First Scatter gather entry */
first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
@@ -243,14 +239,14 @@ eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
DPAA2_GET_FD_FRC_PARSE_SUM(fd));
else
first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
- + DPAA2_FD_PTA_SIZE);
+ (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ + DPAA2_FD_PTA_SIZE));
rte_mbuf_refcnt_set(first_seg, 1);
cur_seg = first_seg;
while (!DPAA2_SG_IS_FINAL(sge)) {
sge = &sgt[i++];
- sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(
+ sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
DPAA2_GET_FLE_ADDR(sge));
next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
@@ -299,8 +295,8 @@ eth_fd_to_mbuf(const struct qbman_fd *fd)
dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd));
else
mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
- + DPAA2_FD_PTA_SIZE);
+ (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ + DPAA2_FD_PTA_SIZE));
PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
"fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n",
@@ -340,7 +336,7 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
/*Set Scatter gather table and Scatter gather entries*/
sgt = (struct qbman_sge *)(
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ DPAA2_GET_FD_OFFSET(fd));
for (i = 0; i < mbuf->nb_segs; i++) {
@@ -523,8 +519,8 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
}
dq_storage = q_storage->active_dqs;
- rte_prefetch0((void *)((uint64_t)(dq_storage)));
- rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
+ rte_prefetch0((void *)(size_t)(dq_storage));
+ rte_prefetch0((void *)(size_t)(dq_storage + 1));
/* Prepare next pull descriptor. This will give space for the
* prefething done on DQRR entries
@@ -554,7 +550,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
*/
while (!qbman_check_new_result(dq_storage))
;
- rte_prefetch0((void *)((uint64_t)(dq_storage + 2)));
+ rte_prefetch0((void *)((size_t)(dq_storage + 2)));
/* Check whether Last Pull command is Expired and
* setting Condition for Loop termination
*/
@@ -569,7 +565,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
next_fd = qbman_result_DQ_fd(dq_storage + 1);
/* Prefetch Annotation address for the parse results */
- rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(next_fd)
+ rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd)
+ DPAA2_FD_PTA_SIZE + 16));
if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
@@ -726,7 +722,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
fd_arr[loop].simple.frc = 0;
DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
- DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
+ DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL);
if (likely(RTE_MBUF_DIRECT(*bufs))) {
mp = (*bufs)->pool;
/* Check the basic scenario and set
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 4/7] bus/fslmc: add 32 bit functional support for ARM
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
` (2 preceding siblings ...)
2018-02-27 17:25 ` [PATCH 3/7] dpaa2: " Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-27 17:25 ` [PATCH 5/7] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
` (3 subsequent siblings)
7 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain
This patch adds the functional logic to make the dpaa2 drivers
work on 32bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++++++++++++++++++++++--
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 9 +++++++++
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h
index 846788e..0b460c4 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys.h
@@ -20,6 +20,9 @@
#include "qbman_sys_decl.h"
+#define CENA_WRITE_ENABLE 0
+#define CINH_WRITE_ENABLE 1
+
/* Debugging assists */
static inline void __hexdump(unsigned long start, unsigned long end,
unsigned long p, size_t sz, const unsigned char *c)
@@ -178,7 +181,11 @@ static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
s->addr_cena, s->idx, offset);
#endif
QBMAN_BUG_ON(offset & 63);
+#ifdef RTE_ARCH_64
return (s->addr_cena + offset);
+#else
+ return (s->addr_cinh + offset);
+#endif
}
static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
@@ -191,11 +198,19 @@ static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
s->addr_cena, s->idx, offset, shadow);
hexdump(cmd, 64);
#endif
+#ifdef RTE_ARCH_64
for (loop = 15; loop >= 1; loop--)
__raw_writel(shadow[loop], s->addr_cena +
offset + loop * 4);
lwsync();
__raw_writel(shadow[0], s->addr_cena + offset);
+#else
+ for (loop = 15; loop >= 1; loop--)
+ __raw_writel(shadow[loop], s->addr_cinh +
+ offset + loop * 4);
+ lwsync();
+ __raw_writel(shadow[0], s->addr_cinh + offset);
+#endif
dcbf(s->addr_cena + offset);
}
@@ -224,9 +239,15 @@ static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
s->addr_cena, s->idx, offset, shadow);
#endif
+#ifdef RTE_ARCH_64
for (loop = 0; loop < 16; loop++)
shadow[loop] = __raw_readl(s->addr_cena + offset
+ loop * 4);
+#else
+ for (loop = 0; loop < 16; loop++)
+ shadow[loop] = __raw_readl(s->addr_cinh + offset
+ + loop * 4);
+#endif
#ifdef QBMAN_CENA_TRACE
hexdump(shadow, 64);
#endif
@@ -313,6 +334,11 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
uint8_t dqrr_size)
{
uint32_t reg;
+#ifndef RTE_ARCH_64
+ uint8_t wn = CENA_WRITE_ENABLE;
+#else
+ uint8_t wn = CINH_WRITE_ENABLE;
+#endif
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
@@ -333,10 +359,10 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
QBMAN_BUG_ON(reg);
#endif
if (s->eqcr_mode == qman_eqcr_vb_array)
- reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1,
+ reg = qbman_set_swp_cfg(dqrr_size, wn, 0, 3, 2, 3, 1, 1, 1, 1,
1, 1);
else
- reg = qbman_set_swp_cfg(dqrr_size, 0, 1, 3, 2, 2, 1, 1, 1, 1,
+ reg = qbman_set_swp_cfg(dqrr_size, wn, 2, 3, 2, 2, 1, 1, 1, 1,
1, 1);
qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
index f82bb18..5640b04 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
@@ -15,6 +15,7 @@
/****************/
/* arch assists */
/****************/
+#if defined(RTE_ARCH_ARM64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define lwsync() { asm volatile("dmb st" : : : "memory"); }
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
@@ -28,3 +29,11 @@ static inline void prefetch_for_store(void *p)
{
asm volatile("prfm pstl1keep, [%0, #0]" : : "r" (p));
}
+#elif defined(RTE_ARCH_ARM)
+#define dcbz(p) memset(p, 0, 64)
+#define lwsync() { asm volatile("dmb st" : : : "memory"); }
+#define dcbf(p) RTE_SET_USED(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 5/7] bus/dpaa: enabling dpaa compilation for other platforms
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
` (3 preceding siblings ...)
2018-02-27 17:25 ` [PATCH 4/7] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-27 17:25 ` [PATCH 6/7] bus/fslmc: enabling dpaa2 " Hemant Agrawal
` (2 subsequent siblings)
7 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/include/compat.h | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/dpaa/include/compat.h b/drivers/bus/dpaa/include/compat.h
index 53707bb..e4b5702 100644
--- a/drivers/bus/dpaa/include/compat.h
+++ b/drivers/bus/dpaa/include/compat.h
@@ -39,6 +39,7 @@
#include <rte_spinlock.h>
#include <rte_common.h>
#include <rte_debug.h>
+#include <rte_cycles.h>
/* The following definitions are primarily to allow the single-source driver
* interfaces to be included by arbitrary program code. Ie. for interfaces that
@@ -127,13 +128,15 @@ static inline void out_be32(volatile void *__p, u32 val)
*p = rte_cpu_to_be_32(val);
}
+#define hwsync() rte_rmb()
+#define lwsync() rte_wmb()
+
#define dcbt_ro(p) __builtin_prefetch(p, 0)
#define dcbt_rw(p) __builtin_prefetch(p, 1)
+#if defined(RTE_ARCH_ARM64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define dcbz_64(p) dcbz(p)
-#define hwsync() rte_rmb()
-#define lwsync() rte_wmb()
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
#define dcbf_64(p) dcbf(p)
#define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); }
@@ -144,9 +147,27 @@ static inline void out_be32(volatile void *__p, u32 val)
asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); \
} while (0)
+#elif defined(RTE_ARCH_ARM)
+#define dcbz(p) memset((p), 0, 32)
+#define dcbz_64(p) memset((p), 0, 64)
+#define dcbf(p) RTE_SET_USED(p)
+#define dcbf_64(p) dcbf(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define dcbit_ro(p) RTE_SET_USED(p)
+
+#else
+#define dcbz(p) RTE_SET_USED(p)
+#define dcbz_64(p) dcbz(p)
+#define dcbf(p) RTE_SET_USED(p)
+#define dcbf_64(p) dcbf(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define dcbit_ro(p) RTE_SET_USED(p)
+#endif
+
#define barrier() { asm volatile ("" : : : "memory"); }
#define cpu_relax barrier
+#if defined(RTE_ARCH_ARM64)
static inline uint64_t mfatb(void)
{
uint64_t ret, ret_new, timeout = 200;
@@ -160,6 +181,11 @@ static inline uint64_t mfatb(void)
DPAA_BUG_ON(!timeout && (ret != ret_new));
return ret * 64;
}
+#else
+
+#define mfatb rte_rdtsc
+
+#endif
/* Spin for a few cycles without bothering the bus */
static inline void cpu_spin(int cycles)
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 6/7] bus/fslmc: enabling dpaa2 compilation for other platforms
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
` (4 preceding siblings ...)
2018-02-27 17:25 ` [PATCH 5/7] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-28 14:45 ` Bruce Richardson
2018-02-27 17:25 ` [PATCH 7/7] build: add meson support for dpaaX platforms Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
7 siblings, 1 reply; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
index 5640b04..fa6977f 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
@@ -36,4 +36,18 @@ static inline void prefetch_for_store(void *p)
#define dccivac(p) RTE_SET_USED(p)
#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+
+#else
+#define dcbz(p) RTE_SET_USED(p)
+#define lwsync()
+#define dcbf(p) RTE_SET_USED(p)
+#define dccivac(p) RTE_SET_USED(p)
+static inline void prefetch_for_load(void *p)
+{
+ RTE_SET_USED(p);
+}
+static inline void prefetch_for_store(void *p)
+{
+ RTE_SET_USED(p);
+}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 7/7] build: add meson support for dpaaX platforms
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
` (5 preceding siblings ...)
2018-02-27 17:25 ` [PATCH 6/7] bus/fslmc: enabling dpaa2 " Hemant Agrawal
@ 2018-02-27 17:25 ` Hemant Agrawal
2018-02-28 14:44 ` Bruce Richardson
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
7 siblings, 1 reply; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-27 17:25 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, shreyansh.jain, Akhil Goyal
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
app/test-pmd/meson.build | 3 +++
config/arm/arm64_dpaa2_linuxapp_gcc | 13 +++++++++++++
config/arm/arm64_dpaa_linuxapp_gcc | 14 ++++++++++++++
config/arm/meson.build | 13 +++++++++++++
drivers/bus/dpaa/meson.build | 29 +++++++++++++++++++++++++++++
drivers/bus/fslmc/meson.build | 28 ++++++++++++++++++++++++++++
drivers/bus/meson.build | 4 ++--
drivers/crypto/dpaa2_sec/meson.build | 16 ++++++++++++++++
drivers/crypto/dpaa_sec/meson.build | 16 ++++++++++++++++
drivers/crypto/meson.build | 3 +++
drivers/event/dpaa/meson.build | 11 +++++++++++
drivers/event/dpaa2/meson.build | 12 ++++++++++++
drivers/event/meson.build | 2 +-
drivers/mempool/dpaa/meson.build | 9 +++++++++
drivers/mempool/dpaa2/meson.build | 9 +++++++++
drivers/mempool/meson.build | 2 +-
drivers/net/dpaa/meson.build | 15 +++++++++++++++
drivers/net/dpaa2/meson.build | 16 ++++++++++++++++
drivers/net/meson.build | 2 +-
19 files changed, 212 insertions(+), 5 deletions(-)
create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
create mode 100644 drivers/bus/dpaa/meson.build
create mode 100644 drivers/bus/fslmc/meson.build
create mode 100644 drivers/crypto/dpaa2_sec/meson.build
create mode 100644 drivers/crypto/dpaa_sec/meson.build
create mode 100644 drivers/event/dpaa/meson.build
create mode 100644 drivers/event/dpaa2/meson.build
create mode 100644 drivers/mempool/dpaa/meson.build
create mode 100644 drivers/mempool/dpaa2/meson.build
create mode 100644 drivers/net/dpaa/meson.build
create mode 100644 drivers/net/dpaa2/meson.build
diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build
index 7ed74db..83f8bb1 100644
--- a/app/test-pmd/meson.build
+++ b/app/test-pmd/meson.build
@@ -32,6 +32,9 @@ if dpdk_conf.has('RTE_LIBRTE_SOFTNIC_PMD')
sources += files('tm.c')
deps += 'pmd_softnic'
endif
+if dpdk_conf.has('RTE_LIBRTE_DPAA_PMD')
+ deps += ['bus_dpaa', 'mempool_dpaa', 'pmd_dpaa']
+endif
dep_objs = []
foreach d:deps
diff --git a/config/arm/arm64_dpaa2_linuxapp_gcc b/config/arm/arm64_dpaa2_linuxapp_gcc
new file mode 100644
index 0000000..87337fb
--- /dev/null
+++ b/config/arm/arm64_dpaa2_linuxapp_gcc
@@ -0,0 +1,13 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = 'dpaa2'
diff --git a/config/arm/arm64_dpaa_linuxapp_gcc b/config/arm/arm64_dpaa_linuxapp_gcc
new file mode 100644
index 0000000..f769435
--- /dev/null
+++ b/config/arm/arm64_dpaa_linuxapp_gcc
@@ -0,0 +1,14 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = 'dpaa'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 4e788a4..c1ab6ed 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,17 @@ flags_cavium = [
['RTE_MAX_LCORE', 96],
['RTE_MAX_VFIO_GROUPS', 128],
['RTE_RING_USE_C11_MEM_MODEL', false]]
+flags_dpaa = [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16]]
+flags_dpaa2 = [
+ ['RTE_MACHINE', '"dpaa2"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', 'n']]
## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -69,6 +80,8 @@ impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
impl_0x69 = ['Intel', flags_generic, machine_args_generic]
+impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
+impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
if cc.get_define('__clang__') != ''
diff --git a/drivers/bus/dpaa/meson.build b/drivers/bus/dpaa/meson.build
new file mode 100644
index 0000000..c4257a5
--- /dev/null
+++ b/drivers/bus/dpaa/meson.build
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['pci', 'ethdev', 'eventdev']
+sources = files('dpaa_bus.c',
+ 'base/fman/fman.c',
+ 'base/fman/fman_hw.c',
+ 'base/fman/of.c',
+ 'base/fman/netcfg_layer.c',
+ 'base/qbman/process.c',
+ 'base/qbman/bman.c',
+ 'base/qbman/bman_driver.c',
+ 'base/qbman/qman.c',
+ 'base/qbman/qman_driver.c',
+ 'base/qbman/dpaa_alloc.c',
+ 'base/qbman/dpaa_sys.c')
+
+allow_experimental_apis = true
+
+if cc.has_argument('-Wno-cast-qual')
+ cflags += '-Wno-cast-qual'
+endif
+
+includes += include_directories('include', 'base/qbman')
+cflags += ['-D_GNU_SOURCE']
diff --git a/drivers/bus/fslmc/meson.build b/drivers/bus/fslmc/meson.build
new file mode 100644
index 0000000..87475ee
--- /dev/null
+++ b/drivers/bus/fslmc/meson.build
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['eal', 'ethdev', 'eventdev']
+sources = files('qbman/qbman_portal.c',
+ 'qbman/qbman_debug.c',
+ 'mc/dpmng.c',
+ 'mc/dpbp.c',
+ 'mc/dpio.c',
+ 'mc/mc_sys.c',
+ 'mc/dpcon.c',
+ 'mc/dpci.c',
+ 'portal/dpaa2_hw_dpio.c',
+ 'portal/dpaa2_hw_dpbp.c',
+ 'portal/dpaa2_hw_dpci.c',
+ 'fslmc_vfio.c',
+ 'fslmc_bus.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
+includes += include_directories('mc', 'qbman/include', 'portal')
+dpdk_conf.set('CONFIG_RTE_ARCH_ARM_TUNE', 'cortex-a72')
+cflags += ['-D_GNU_SOURCE']
diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build
index c6af500..2187f6b 100644
--- a/drivers/bus/meson.build
+++ b/drivers/bus/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['pci', 'vdev']
-std_deps = ['eal']
+drivers = ['pci', 'vdev', 'fslmc', 'dpaa']
+std_deps = ['eal', 'kvargs']
config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
driver_name_fmt = 'rte_bus_@0@'
diff --git a/drivers/crypto/dpaa2_sec/meson.build b/drivers/crypto/dpaa2_sec/meson.build
new file mode 100644
index 0000000..e80f15d
--- /dev/null
+++ b/drivers/crypto/dpaa2_sec/meson.build
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_fslmc', 'security', 'mempool_dpaa2']
+sources = files('dpaa2_sec_dpseci.c',
+ 'mc/dpseci.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('mc', 'hw')
+dpdk_conf.set('RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS', 2048)
+ext_deps += dep
diff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build
new file mode 100644
index 0000000..10a7dd3
--- /dev/null
+++ b/drivers/crypto/dpaa_sec/meson.build
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_dpaa', 'security']
+sources = files('dpaa_sec.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('../dpaa2_sec/')
+dpdk_conf.set('RTE_LIBRTE_DPAA_MAX_CRYPTODEV', 4)
+dpdk_conf.set('RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS', 2048)
+ext_deps += dep
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 17041ad..a08bce5 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -2,6 +2,9 @@
# Copyright(c) 2017 Intel Corporation
drivers = ['qat', 'null', 'openssl']
+
+ drivers += ['dpaa_sec', 'dpaa2_sec']
+
std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
driver_name_fmt = 'rte_pmd_@0@'
diff --git a/drivers/event/dpaa/meson.build b/drivers/event/dpaa/meson.build
new file mode 100644
index 0000000..0a26d5d
--- /dev/null
+++ b/drivers/event/dpaa/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['mempool_dpaa', 'bus_dpaa', 'pmd_dpaa']
+sources = files('dpaa_eventdev.c',
+)
+
+allow_experimental_apis = true
diff --git a/drivers/event/dpaa2/meson.build b/drivers/event/dpaa2/meson.build
new file mode 100644
index 0000000..686b622
--- /dev/null
+++ b/drivers/event/dpaa2/meson.build
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['mempool_dpaa2', 'bus_fslmc', 'bus_vdev', 'pmd_dpaa2']
+sources = files('dpaa2_hw_dpcon.c',
+ 'dpaa2_eventdev.c'
+)
+
+allow_experimental_apis = true
diff --git a/drivers/event/meson.build b/drivers/event/meson.build
index d7bc485..f1c3678 100644
--- a/drivers/event/meson.build
+++ b/drivers/event/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['skeleton', 'sw', 'octeontx']
+drivers = ['skeleton', 'sw', 'octeontx', 'dpaa', 'dpaa2']
std_deps = ['eventdev', 'kvargs']
config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD'
driver_name_fmt = 'rte_pmd_@0@_event'
diff --git a/drivers/mempool/dpaa/meson.build b/drivers/mempool/dpaa/meson.build
new file mode 100644
index 0000000..08423c2
--- /dev/null
+++ b/drivers/mempool/dpaa/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_dpaa']
+sources = files('dpaa_mempool.c')
diff --git a/drivers/mempool/dpaa2/meson.build b/drivers/mempool/dpaa2/meson.build
new file mode 100644
index 0000000..402d087
--- /dev/null
+++ b/drivers/mempool/dpaa2/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['mbuf', 'ethdev', 'kvargs', 'bus_fslmc']
+sources = files('dpaa2_hw_mempool.c')
diff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build
index 5991856..47431cd 100644
--- a/drivers/mempool/meson.build
+++ b/drivers/mempool/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['ring', 'stack', 'octeontx']
+drivers = ['ring', 'stack', 'octeontx', 'dpaa', 'dpaa2']
std_deps = ['mempool']
config_flag_fmt = 'RTE_LIBRTE_@0@_MEMPOOL'
driver_name_fmt = 'rte_mempool_@0@'
diff --git a/drivers/net/dpaa/meson.build b/drivers/net/dpaa/meson.build
new file mode 100644
index 0000000..e5a2d17
--- /dev/null
+++ b/drivers/net/dpaa/meson.build
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['bus_dpaa']
+deps += ['mempool_dpaa']
+
+sources = files('dpaa_ethdev.c',
+ 'dpaa_rxtx.c')
+
+allow_experimental_apis = true
+
+install_headers('rte_pmd_dpaa.h')
diff --git a/drivers/net/dpaa2/meson.build b/drivers/net/dpaa2/meson.build
new file mode 100644
index 0000000..025c587
--- /dev/null
+++ b/drivers/net/dpaa2/meson.build
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_fslmc'] # same with vdev bus
+deps += ['mempool_dpaa2'] # same with vdev bus
+sources = files('dpaa2_ethdev.c',
+ 'dpaa2_rxtx.c',
+ 'base/dpaa2_hw_dpni.c',
+ 'mc/dpni.c',
+ 'mc/dpkg.c')
+
+includes += include_directories('base', 'mc')
diff --git a/drivers/net/meson.build b/drivers/net/meson.build
index 704cbe3..6d7a772 100644
--- a/drivers/net/meson.build
+++ b/drivers/net/meson.build
@@ -4,7 +4,7 @@
drivers = ['af_packet', 'bonding',
'e1000', 'fm10k', 'i40e', 'ixgbe',
'null', 'octeontx', 'pcap', 'ring',
- 'sfc', 'thunderx']
+ 'sfc', 'thunderx', 'dpaa', 'dpaa2']
std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
std_deps += ['bus_pci'] # very many PMDs depend on PCI, so make std
std_deps += ['bus_vdev'] # same with vdev bus
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH 7/7] build: add meson support for dpaaX platforms
2018-02-27 17:25 ` [PATCH 7/7] build: add meson support for dpaaX platforms Hemant Agrawal
@ 2018-02-28 14:44 ` Bruce Richardson
2018-03-01 6:10 ` Hemant Agrawal
0 siblings, 1 reply; 44+ messages in thread
From: Bruce Richardson @ 2018-02-28 14:44 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, thomas, shreyansh.jain, Akhil Goyal
On Tue, Feb 27, 2018 at 10:55:52PM +0530, Hemant Agrawal wrote:
> Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
Thanks for this. Some comments inline below.
/Bruce
> app/test-pmd/meson.build | 3 +++
> config/arm/arm64_dpaa2_linuxapp_gcc | 13 +++++++++++++
> config/arm/arm64_dpaa_linuxapp_gcc | 14 ++++++++++++++
> config/arm/meson.build | 13 +++++++++++++
> drivers/bus/dpaa/meson.build | 29 +++++++++++++++++++++++++++++
> drivers/bus/fslmc/meson.build | 28 ++++++++++++++++++++++++++++
> drivers/bus/meson.build | 4 ++--
> drivers/crypto/dpaa2_sec/meson.build | 16 ++++++++++++++++
> drivers/crypto/dpaa_sec/meson.build | 16 ++++++++++++++++
> drivers/crypto/meson.build | 3 +++
> drivers/event/dpaa/meson.build | 11 +++++++++++
> drivers/event/dpaa2/meson.build | 12 ++++++++++++
> drivers/event/meson.build | 2 +-
> drivers/mempool/dpaa/meson.build | 9 +++++++++
> drivers/mempool/dpaa2/meson.build | 9 +++++++++
> drivers/mempool/meson.build | 2 +-
> drivers/net/dpaa/meson.build | 15 +++++++++++++++
> drivers/net/dpaa2/meson.build | 16 ++++++++++++++++
> drivers/net/meson.build | 2 +-
> 19 files changed, 212 insertions(+), 5 deletions(-)
> create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
> create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
> create mode 100644 drivers/bus/dpaa/meson.build
> create mode 100644 drivers/bus/fslmc/meson.build
> create mode 100644 drivers/crypto/dpaa2_sec/meson.build
> create mode 100644 drivers/crypto/dpaa_sec/meson.build
> create mode 100644 drivers/event/dpaa/meson.build
> create mode 100644 drivers/event/dpaa2/meson.build
> create mode 100644 drivers/mempool/dpaa/meson.build
> create mode 100644 drivers/mempool/dpaa2/meson.build
> create mode 100644 drivers/net/dpaa/meson.build
> create mode 100644 drivers/net/dpaa2/meson.build
>
> diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build
> index 7ed74db..83f8bb1 100644
> --- a/app/test-pmd/meson.build
> +++ b/app/test-pmd/meson.build
> @@ -32,6 +32,9 @@ if dpdk_conf.has('RTE_LIBRTE_SOFTNIC_PMD')
> sources += files('tm.c')
> deps += 'pmd_softnic'
> endif
> +if dpdk_conf.has('RTE_LIBRTE_DPAA_PMD')
> + deps += ['bus_dpaa', 'mempool_dpaa', 'pmd_dpaa']
> +endif
>
> dep_objs = []
> foreach d:deps
> diff --git a/config/arm/arm64_dpaa2_linuxapp_gcc b/config/arm/arm64_dpaa2_linuxapp_gcc
> new file mode 100644
> index 0000000..87337fb
> --- /dev/null
> +++ b/config/arm/arm64_dpaa2_linuxapp_gcc
> @@ -0,0 +1,13 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = 'dpaa2'
> diff --git a/config/arm/arm64_dpaa_linuxapp_gcc b/config/arm/arm64_dpaa_linuxapp_gcc
> new file mode 100644
> index 0000000..f769435
> --- /dev/null
> +++ b/config/arm/arm64_dpaa_linuxapp_gcc
> @@ -0,0 +1,14 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = 'dpaa'
Maybe separate the cross-build files out into a separate patch, since
they are pretty independent of the rest of the changes.
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 4e788a4..c1ab6ed 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -54,6 +54,17 @@ flags_cavium = [
> ['RTE_MAX_LCORE', 96],
> ['RTE_MAX_VFIO_GROUPS', 128],
> ['RTE_RING_USE_C11_MEM_MODEL', false]]
> +flags_dpaa = [
> + ['RTE_MACHINE', '"dpaa"'],
> + ['RTE_CACHE_LINE_SIZE', 64],
> + ['RTE_MAX_NUMA_NODES', 1],
> + ['RTE_MAX_LCORE', 16]]
> +flags_dpaa2 = [
> + ['RTE_MACHINE', '"dpaa2"'],
> + ['RTE_CACHE_LINE_SIZE', 64],
> + ['RTE_MAX_NUMA_NODES', 1],
> + ['RTE_MAX_LCORE', 16],
> + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', 'n']]
>
> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> @@ -69,6 +80,8 @@ impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
> impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
> impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
> impl_0x69 = ['Intel', flags_generic, machine_args_generic]
> +impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
> +impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
>
>
> if cc.get_define('__clang__') != ''
> diff --git a/drivers/bus/dpaa/meson.build b/drivers/bus/dpaa/meson.build
> new file mode 100644
> index 0000000..c4257a5
> --- /dev/null
> +++ b/drivers/bus/dpaa/meson.build
> @@ -0,0 +1,29 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['pci', 'ethdev', 'eventdev']
> +sources = files('dpaa_bus.c',
> + 'base/fman/fman.c',
> + 'base/fman/fman_hw.c',
> + 'base/fman/of.c',
> + 'base/fman/netcfg_layer.c',
> + 'base/qbman/process.c',
> + 'base/qbman/bman.c',
> + 'base/qbman/bman_driver.c',
> + 'base/qbman/qman.c',
> + 'base/qbman/qman_driver.c',
> + 'base/qbman/dpaa_alloc.c',
> + 'base/qbman/dpaa_sys.c')
Minor nit - try to keep all files and list entries in alphabetical
order.
> +
> +allow_experimental_apis = true
> +
> +if cc.has_argument('-Wno-cast-qual')
> + cflags += '-Wno-cast-qual'
> +endif
> +
> +includes += include_directories('include', 'base/qbman')
> +cflags += ['-D_GNU_SOURCE']
> diff --git a/drivers/bus/fslmc/meson.build b/drivers/bus/fslmc/meson.build
> new file mode 100644
> index 0000000..87475ee
> --- /dev/null
> +++ b/drivers/bus/fslmc/meson.build
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['eal', 'ethdev', 'eventdev']
Another minor nit - eal isn't strictly necessary here as both ethdev and
eventdev already depend on it, and dependencies are recursive.
Explicitly calling out all dependencies is not wrong, but in previous
prototyping I found that meson takes a lot longer to run when it has to
sort through all the dependency chains. That's why in other libs and
drivers I tried to keep the dependency lists to a minimum.
As well as this, EAL is a standard dependency, so it's already in the
deps array at this point.
> +sources = files('qbman/qbman_portal.c',
> + 'qbman/qbman_debug.c',
> + 'mc/dpmng.c',
> + 'mc/dpbp.c',
> + 'mc/dpio.c',
> + 'mc/mc_sys.c',
> + 'mc/dpcon.c',
> + 'mc/dpci.c',
> + 'portal/dpaa2_hw_dpio.c',
> + 'portal/dpaa2_hw_dpbp.c',
> + 'portal/dpaa2_hw_dpci.c',
> + 'fslmc_vfio.c',
> + 'fslmc_bus.c')
> +
> +allow_experimental_apis = true
> +
> +includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
Is this not covered by the dependency on eal? Is it accessing things
directly in the EAL internals?
> +includes += include_directories('mc', 'qbman/include', 'portal')
> +dpdk_conf.set('CONFIG_RTE_ARCH_ARM_TUNE', 'cortex-a72')
This setting seems strange here? How is it used, and why set only inside
this particular driver?
> +cflags += ['-D_GNU_SOURCE']
> diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build
> index c6af500..2187f6b 100644
> --- a/drivers/bus/meson.build
> +++ b/drivers/bus/meson.build
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: BSD-3-Clause
> # Copyright(c) 2017 Intel Corporation
>
> -drivers = ['pci', 'vdev']
> -std_deps = ['eal']
> +drivers = ['pci', 'vdev', 'fslmc', 'dpaa']
Please keep alphabetical order.
> +std_deps = ['eal', 'kvargs']
No big issue with this line change, but did you consider just making
kvargs a dependency of the fslmc and dpaa buses directly, rather than
making pci and vdev also depend on them?
> config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
> driver_name_fmt = 'rte_bus_@0@'
> diff --git a/drivers/crypto/dpaa2_sec/meson.build b/drivers/crypto/dpaa2_sec/meson.build
> new file mode 100644
> index 0000000..e80f15d
> --- /dev/null
> +++ b/drivers/crypto/dpaa2_sec/meson.build
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['bus_fslmc', 'security', 'mempool_dpaa2']
> +sources = files('dpaa2_sec_dpseci.c',
> + 'mc/dpseci.c')
> +
> +allow_experimental_apis = true
> +
> +includes += include_directories('mc', 'hw')
> +dpdk_conf.set('RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS', 2048)
I don't think this should be set here. For other libs and drivers, the
constants are placed directly in config/rte_config.h (or put into a
header file inside the driver itself).
> +ext_deps += dep
This line should be removed. You haven't assigned a dependency object to
a variable called "dep" anywhere in this file.
> diff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build
> new file mode 100644
> index 0000000..10a7dd3
> --- /dev/null
> +++ b/drivers/crypto/dpaa_sec/meson.build
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['bus_dpaa', 'security']
> +sources = files('dpaa_sec.c')
> +
> +allow_experimental_apis = true
> +
> +includes += include_directories('../dpaa2_sec/')
> +dpdk_conf.set('RTE_LIBRTE_DPAA_MAX_CRYPTODEV', 4)
> +dpdk_conf.set('RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS', 2048)
As with other constants, I think this should go directly into
rte_config.h, or in a header file in the driver directly.
> +ext_deps += dep
Drop this line.
> diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
> index 17041ad..a08bce5 100644
> --- a/drivers/crypto/meson.build
> +++ b/drivers/crypto/meson.build
> @@ -2,6 +2,9 @@
> # Copyright(c) 2017 Intel Corporation
>
> drivers = ['qat', 'null', 'openssl']
> +
> + drivers += ['dpaa_sec', 'dpaa2_sec']
> +
Don't indent.
In other lists, we just allow list to flow onto multiple lines, rather
than using +=. Using += is not wrong, it's just inconsistent, and again
will break alphabetical ordering in this case.
> std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
> config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
> driver_name_fmt = 'rte_pmd_@0@'
> diff --git a/drivers/event/dpaa/meson.build b/drivers/event/dpaa/meson.build
> new file mode 100644
> index 0000000..0a26d5d
> --- /dev/null
> +++ b/drivers/event/dpaa/meson.build
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +deps += ['mempool_dpaa', 'bus_dpaa', 'pmd_dpaa']
> +sources = files('dpaa_eventdev.c',
> +)
No need to move to a second line here.
> +
> +allow_experimental_apis = true
> diff --git a/drivers/event/dpaa2/meson.build b/drivers/event/dpaa2/meson.build
> new file mode 100644
> index 0000000..686b622
> --- /dev/null
> +++ b/drivers/event/dpaa2/meson.build
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +deps += ['mempool_dpaa2', 'bus_fslmc', 'bus_vdev', 'pmd_dpaa2']
> +sources = files('dpaa2_hw_dpcon.c',
> + 'dpaa2_eventdev.c'
> +)
> +
> +allow_experimental_apis = true
> diff --git a/drivers/event/meson.build b/drivers/event/meson.build
> index d7bc485..f1c3678 100644
> --- a/drivers/event/meson.build
> +++ b/drivers/event/meson.build
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: BSD-3-Clause
> # Copyright(c) 2017 Intel Corporation
>
> -drivers = ['skeleton', 'sw', 'octeontx']
> +drivers = ['skeleton', 'sw', 'octeontx', 'dpaa', 'dpaa2']
alphabetically ordering, please.
> std_deps = ['eventdev', 'kvargs']
> config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD'
> driver_name_fmt = 'rte_pmd_@0@_event'
> diff --git a/drivers/mempool/dpaa/meson.build b/drivers/mempool/dpaa/meson.build
> new file mode 100644
> index 0000000..08423c2
> --- /dev/null
> +++ b/drivers/mempool/dpaa/meson.build
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['bus_dpaa']
> +sources = files('dpaa_mempool.c')
> diff --git a/drivers/mempool/dpaa2/meson.build b/drivers/mempool/dpaa2/meson.build
> new file mode 100644
> index 0000000..402d087
> --- /dev/null
> +++ b/drivers/mempool/dpaa2/meson.build
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['mbuf', 'ethdev', 'kvargs', 'bus_fslmc']
> +sources = files('dpaa2_hw_mempool.c')
> diff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build
> index 5991856..47431cd 100644
> --- a/drivers/mempool/meson.build
> +++ b/drivers/mempool/meson.build
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: BSD-3-Clause
> # Copyright(c) 2017 Intel Corporation
>
> -drivers = ['ring', 'stack', 'octeontx']
> +drivers = ['ring', 'stack', 'octeontx', 'dpaa', 'dpaa2']
ordering.
> std_deps = ['mempool']
> config_flag_fmt = 'RTE_LIBRTE_@0@_MEMPOOL'
> driver_name_fmt = 'rte_mempool_@0@'
> diff --git a/drivers/net/dpaa/meson.build b/drivers/net/dpaa/meson.build
> new file mode 100644
> index 0000000..e5a2d17
> --- /dev/null
> +++ b/drivers/net/dpaa/meson.build
> @@ -0,0 +1,15 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +deps += ['bus_dpaa']
> +deps += ['mempool_dpaa']
> +
> +sources = files('dpaa_ethdev.c',
> + 'dpaa_rxtx.c')
> +
> +allow_experimental_apis = true
> +
> +install_headers('rte_pmd_dpaa.h')
> diff --git a/drivers/net/dpaa2/meson.build b/drivers/net/dpaa2/meson.build
> new file mode 100644
> index 0000000..025c587
> --- /dev/null
> +++ b/drivers/net/dpaa2/meson.build
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright 2018 NXP
> +
> +if host_machine.system() != 'linux'
> + build = false
> +endif
> +
> +deps += ['bus_fslmc'] # same with vdev bus
> +deps += ['mempool_dpaa2'] # same with vdev bus
> +sources = files('dpaa2_ethdev.c',
> + 'dpaa2_rxtx.c',
> + 'base/dpaa2_hw_dpni.c',
> + 'mc/dpni.c',
> + 'mc/dpkg.c')
> +
> +includes += include_directories('base', 'mc')
> diff --git a/drivers/net/meson.build b/drivers/net/meson.build
> index 704cbe3..6d7a772 100644
> --- a/drivers/net/meson.build
> +++ b/drivers/net/meson.build
> @@ -4,7 +4,7 @@
> drivers = ['af_packet', 'bonding',
> 'e1000', 'fm10k', 'i40e', 'ixgbe',
> 'null', 'octeontx', 'pcap', 'ring',
> - 'sfc', 'thunderx']
> + 'sfc', 'thunderx', 'dpaa', 'dpaa2']
ordering.
> std_deps = ['ethdev', 'kvargs'] # 'ethdev' also pulls in mbuf, net, eal etc
> std_deps += ['bus_pci'] # very many PMDs depend on PCI, so make std
> std_deps += ['bus_vdev'] # same with vdev bus
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/7] bus/fslmc: enabling dpaa2 compilation for other platforms
2018-02-27 17:25 ` [PATCH 6/7] bus/fslmc: enabling dpaa2 " Hemant Agrawal
@ 2018-02-28 14:45 ` Bruce Richardson
2018-02-28 16:02 ` Hemant Agrawal
0 siblings, 1 reply; 44+ messages in thread
From: Bruce Richardson @ 2018-02-28 14:45 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, thomas, shreyansh.jain
On Tue, Feb 27, 2018 at 10:55:51PM +0530, Hemant Agrawal wrote:
> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
> drivers/bus/fslmc/qbman/qbman_sys_decl.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
With these patches should config/common_base be changed to enable all
these drivers globally for compilation testing?
/Bruce
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/7] bus/fslmc: enabling dpaa2 compilation for other platforms
2018-02-28 14:45 ` Bruce Richardson
@ 2018-02-28 16:02 ` Hemant Agrawal
2018-02-28 16:33 ` Richardson, Bruce
0 siblings, 1 reply; 44+ messages in thread
From: Hemant Agrawal @ 2018-02-28 16:02 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev, thomas, shreyansh.jain
On 2/28/2018 8:15 PM, Bruce Richardson wrote:
> On Tue, Feb 27, 2018 at 10:55:51PM +0530, Hemant Agrawal wrote:
>> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
>> ---
>> drivers/bus/fslmc/qbman/qbman_sys_decl.h | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>
> With these patches should config/common_base be changed to enable all
> these drivers globally for compilation testing?
>
currently we are planning to enable them in config/common_linuxapp only.
We still have issue with BSD compilations. some of the compat files are
linux dependent.
> /Bruce
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/7] bus/fslmc: enabling dpaa2 compilation for other platforms
2018-02-28 16:02 ` Hemant Agrawal
@ 2018-02-28 16:33 ` Richardson, Bruce
0 siblings, 0 replies; 44+ messages in thread
From: Richardson, Bruce @ 2018-02-28 16:33 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, thomas, shreyansh.jain
> -----Original Message-----
> From: Hemant Agrawal [mailto:hemant.agrawal@nxp.com]
> Sent: Wednesday, February 28, 2018 4:02 PM
> To: Richardson, Bruce <bruce.richardson@intel.com>
> Cc: dev@dpdk.org; thomas@monjalon.net; shreyansh.jain@nxp.com
> Subject: Re: [PATCH 6/7] bus/fslmc: enabling dpaa2 compilation for other
> platforms
>
> On 2/28/2018 8:15 PM, Bruce Richardson wrote:
> > On Tue, Feb 27, 2018 at 10:55:51PM +0530, Hemant Agrawal wrote:
> >> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> >> ---
> >> drivers/bus/fslmc/qbman/qbman_sys_decl.h | 14 ++++++++++++++
> >> 1 file changed, 14 insertions(+)
> >>
> >
> > With these patches should config/common_base be changed to enable all
> > these drivers globally for compilation testing?
> >
>
> currently we are planning to enable them in config/common_linuxapp only.
>
> We still have issue with BSD compilations. some of the compat files are
> linux dependent.
>
Yes, of course. I should have spotted that from the checks in the meson files. :-)
/Bruce
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/7] build: add meson support for dpaaX platforms
2018-02-28 14:44 ` Bruce Richardson
@ 2018-03-01 6:10 ` Hemant Agrawal
2018-03-01 14:15 ` Thomas Monjalon
0 siblings, 1 reply; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 6:10 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev, thomas, shreyansh.jain, Akhil Goyal
On 2/28/2018 8:14 PM, Bruce Richardson wrote:
> On Tue, Feb 27, 2018 at 10:55:52PM +0530, Hemant Agrawal wrote:
>> Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
>> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
>> ---
>
> Thanks for this. Some comments inline below.
>
> /Bruce
<snip>..
>> diff --git a/drivers/bus/fslmc/meson.build b/drivers/bus/fslmc/meson.build
>> new file mode 100644
>> index 0000000..87475ee
>> --- /dev/null
>> +++ b/drivers/bus/fslmc/meson.build
>> @@ -0,0 +1,28 @@
>> +# SPDX-License-Identifier: BSD-3-Clause
>> +# Copyright 2018 NXP
>> +
>> +if host_machine.system() != 'linux'
>> + build = false
>> +endif
>> +
>> +deps += ['eal', 'ethdev', 'eventdev']
>
> Another minor nit - eal isn't strictly necessary here as both ethdev and
> eventdev already depend on it, and dependencies are recursive.
> Explicitly calling out all dependencies is not wrong, but in previous
> prototyping I found that meson takes a lot longer to run when it has to
> sort through all the dependency chains. That's why in other libs and
> drivers I tried to keep the dependency lists to a minimum.
> As well as this, EAL is a standard dependency, so it's already in the
> deps array at this point.
>
yes, it worked.
>> +sources = files('qbman/qbman_portal.c',
>> + 'qbman/qbman_debug.c',
>> + 'mc/dpmng.c',
>> + 'mc/dpbp.c',
>> + 'mc/dpio.c',
>> + 'mc/mc_sys.c',
>> + 'mc/dpcon.c',
>> + 'mc/dpci.c',
>> + 'portal/dpaa2_hw_dpio.c',
>> + 'portal/dpaa2_hw_dpbp.c',
>> + 'portal/dpaa2_hw_dpci.c',
>> + 'fslmc_vfio.c',
>> + 'fslmc_bus.c')
>> +
>> +allow_experimental_apis = true
>> +
>> +includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
>
> Is this not covered by the dependency on eal? Is it accessing things
> directly in the EAL internals?
We are accessing eal_vfio.h. so it is needed.
../drivers/bus/fslmc/fslmc_vfio.h:12:10: fatal error: eal_vfio.h: No
such file or directory
#include <eal_vfio.h>
>
>> +includes += include_directories('mc', 'qbman/include', 'portal')
>> +dpdk_conf.set('CONFIG_RTE_ARCH_ARM_TUNE', 'cortex-a72')
>
> This setting seems strange here? How is it used, and why set only inside
> this particular driver?
>
We can remove it
>> +cflags += ['-D_GNU_SOURCE']
>> diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build
>> index c6af500..2187f6b 100644
>> --- a/drivers/bus/meson.build
>> +++ b/drivers/bus/meson.build
>> @@ -1,7 +1,7 @@
>> # SPDX-License-Identifier: BSD-3-Clause
>> # Copyright(c) 2017 Intel Corporation
>>
>> -drivers = ['pci', 'vdev']
>> -std_deps = ['eal']
>> +drivers = ['pci', 'vdev', 'fslmc', 'dpaa']
>
> Please keep alphabetical order.
>
>> +std_deps = ['eal', 'kvargs']
>
> No big issue with this line change, but did you consider just making
> kvargs a dependency of the fslmc and dpaa buses directly, rather than
> making pci and vdev also depend on them?
>
Yes. it will work
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2 00/10] meson build support for dpaaX
2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
` (6 preceding siblings ...)
2018-02-27 17:25 ` [PATCH 7/7] build: add meson support for dpaaX platforms Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 01/10] event/dpaa: fix include header Hemant Agrawal
` (10 more replies)
7 siblings, 11 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch series enables the meson build support for dpaa and dpaa2 platforms.
Earlier dpaaX was only compiled for armv8 target. This patch series first
prepares the dpaaX drivers to be compiled for non-ARM platform as well.
v2:
- handle review comments from Bruce
- move the dpaaX compilation to linuxapp
Hemant Agrawal (10):
event/dpaa: fix include header
bus/dpaa: fix the BE compilation issue
dpaa: prepare for 32 bit compilation
dpaa2: prepare for 32 bit compilation
bus/fslmc: add 32 bit functional support for ARM
bus/dpaa: enabling dpaa compilation for other platforms
bus/fslmc: enabling dpaa2 compilation for other platforms
config: add dpaaX build support in common linuxapp
build: add meson support for dpaaX platforms
build: adding meson cross compile config for dpaaX
app/test-pmd/meson.build | 3 ++
config/arm/arm64_dpaa2_linuxapp_gcc | 13 +++++++
config/arm/arm64_dpaa_linuxapp_gcc | 14 +++++++
config/arm/meson.build | 13 +++++++
config/common_armv8a_linuxapp | 58 ----------------------------
config/common_linuxapp | 37 ++++++++++++++++++
config/rte_config.h | 12 +++++-
drivers/bus/dpaa/base/fman/fman.c | 2 +-
drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +-
drivers/bus/dpaa/base/qbman/qman.c | 5 ++-
drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +--
drivers/bus/dpaa/dpaa_bus.c | 3 +-
drivers/bus/dpaa/include/compat.h | 30 ++++++++++++++-
drivers/bus/dpaa/meson.build | 29 ++++++++++++++
drivers/bus/fslmc/fslmc_vfio.c | 10 ++---
drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-
drivers/bus/fslmc/meson.build | 27 +++++++++++++
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 4 +-
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++++++---------
drivers/bus/fslmc/qbman/qbman_portal.c | 14 +++----
drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++++++++-
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 23 +++++++++++
drivers/bus/meson.build | 2 +-
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 60 ++++++++++++++---------------
drivers/crypto/dpaa2_sec/meson.build | 14 +++++++
drivers/crypto/dpaa_sec/dpaa_sec.c | 30 +++++++--------
drivers/crypto/dpaa_sec/meson.build | 13 +++++++
drivers/crypto/meson.build | 4 +-
drivers/event/dpaa/dpaa_eventdev.c | 2 +-
drivers/event/dpaa/meson.build | 10 +++++
drivers/event/dpaa2/dpaa2_eventdev.c | 6 +--
drivers/event/dpaa2/meson.build | 11 ++++++
drivers/event/meson.build | 2 +-
drivers/mempool/dpaa/dpaa_mempool.c | 10 ++---
drivers/mempool/dpaa/dpaa_mempool.h | 2 +-
drivers/mempool/dpaa/meson.build | 9 +++++
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 ++--
drivers/mempool/dpaa2/meson.build | 9 +++++
drivers/mempool/meson.build | 2 +-
drivers/net/dpaa/dpaa_rxtx.c | 17 ++++----
drivers/net/dpaa/meson.build | 14 +++++++
drivers/net/dpaa2/Makefile | 1 -
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +-
drivers/net/dpaa2/dpaa2_ethdev.c | 6 +--
drivers/net/dpaa2/dpaa2_rxtx.c | 38 ++++++++----------
drivers/net/dpaa2/meson.build | 15 ++++++++
drivers/net/meson.build | 2 +-
47 files changed, 455 insertions(+), 207 deletions(-)
create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
create mode 100644 drivers/bus/dpaa/meson.build
create mode 100644 drivers/bus/fslmc/meson.build
create mode 100644 drivers/crypto/dpaa2_sec/meson.build
create mode 100644 drivers/crypto/dpaa_sec/meson.build
create mode 100644 drivers/event/dpaa/meson.build
create mode 100644 drivers/event/dpaa2/meson.build
create mode 100644 drivers/mempool/dpaa/meson.build
create mode 100644 drivers/mempool/dpaa2/meson.build
create mode 100644 drivers/net/dpaa/meson.build
create mode 100644 drivers/net/dpaa2/meson.build
--
2.7.4
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v2 01/10] event/dpaa: fix include header
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
` (9 subsequent siblings)
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, stable
rte_cycles.h shall be included instead of rte_cycles_64.h
dpaa_eventdev.c:32:27:
fatal error: rte_cycles_64.h: No such file or directory
Fixes: 9caac5dd1e7f ("event/dpaa: introduce PMD")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/event/dpaa/dpaa_eventdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
index 0006801..cd13d0c 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -29,7 +29,7 @@
#include <rte_event_eth_rx_adapter.h>
#include <rte_dpaa_bus.h>
#include <rte_dpaa_logs.h>
-#include <rte_cycles_64.h>
+#include <rte_cycles.h>
#include <dpaa_ethdev.h>
#include "dpaa_eventdev.h"
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 02/10] bus/dpaa: fix the BE compilation issue
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 01/10] event/dpaa: fix include header Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 12:22 ` Shreyansh Jain
2018-03-01 7:33 ` [PATCH v2 03/10] dpaa: prepare for 32 bit compilation Hemant Agrawal
` (8 subsequent siblings)
10 siblings, 1 reply; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, stable
The array pointers were used without index.
Fixes: b9083ea5e084 ("net/dpaa: further push mode optimizations")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman.c | 5 +++--
drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 2b97671..2810fdd 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -1087,7 +1087,7 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
shadow[rx_number]->fd.opaque =
be32_to_cpu(dq[rx_number]->fd.opaque);
#else
- shadow = dq;
+ shadow[rx_number] = dq[rx_number];
#endif
/* SDQCR: context_b points to the FQ */
@@ -1095,7 +1095,8 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
fq[rx_number] = qman_fq_lookup_table[be32_to_cpu(
dq[rx_number]->contextB)];
#else
- fq[rx_number] = (void *)(uintptr_t)be32_to_cpu(dq->contextB);
+ fq[rx_number] = (void *)be32_to_cpu(
+ dq[rx_number]->contextB);
#endif
fq[rx_number]->cb.dqrr_prepare(shadow[rx_number],
&bufs[rx_number]);
diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c
index 7cfa8ee..66838d2 100644
--- a/drivers/bus/dpaa/base/qbman/qman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/qman_driver.c
@@ -246,7 +246,6 @@ int fsl_qman_portal_destroy(struct qman_portal *qp)
int qman_global_init(void)
{
const struct device_node *dt_node;
- int ret = 0;
size_t lenp;
const u32 *chanid;
static int ccsr_map_fd;
@@ -352,9 +351,7 @@ int qman_global_init(void)
qman_clk = be32_to_cpu(*clk);
#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
- ret = qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX);
- if (ret)
- return ret;
+ return qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX);
#endif
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 03/10] dpaa: prepare for 32 bit compilation
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 01/10] event/dpaa: fix include header Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 04/10] dpaa2: " Hemant Agrawal
` (7 subsequent siblings)
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch prepares the dpaa drivers for compilation on 32 bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/base/fman/fman.c | 2 +-
drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +-
drivers/bus/dpaa/dpaa_bus.c | 3 +--
drivers/crypto/dpaa_sec/dpaa_sec.c | 30 +++++++++++++++---------------
drivers/mempool/dpaa/dpaa_mempool.c | 10 +++++-----
drivers/mempool/dpaa/dpaa_mempool.h | 2 +-
drivers/net/dpaa/dpaa_rxtx.c | 17 ++++++++---------
7 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c
index bda62e0..e6fd5f3 100644
--- a/drivers/bus/dpaa/base/fman/fman.c
+++ b/drivers/bus/dpaa/base/fman/fman.c
@@ -300,7 +300,7 @@ fman_if_init(const struct device_node *dpa_node)
_errno = fman_get_mac_index(regs_addr_host, &__if->__if.mac_idx);
if (_errno) {
- FMAN_ERR(-EINVAL, "Invalid register address: %lu",
+ FMAN_ERR(-EINVAL, "Invalid register address: %" PRIx64,
regs_addr_host);
goto err;
}
diff --git a/drivers/bus/dpaa/base/qbman/bman_driver.c b/drivers/bus/dpaa/base/qbman/bman_driver.c
index a1ef392..1381da3 100644
--- a/drivers/bus/dpaa/base/qbman/bman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/bman_driver.c
@@ -161,7 +161,7 @@ int bman_init_ccsr(const struct device_node *node)
PROT_WRITE, MAP_SHARED, ccsr_map_fd, phys_addr);
if (bman_ccsr_map == MAP_FAILED) {
pr_err("Can not map BMan CCSR base Bman: "
- "0x%x Phys: 0x%lx size 0x%lx",
+ "0x%x Phys: 0x%" PRIx64 " size 0x%" PRIu64,
*bman_addr, phys_addr, regs_size);
return -EINVAL;
}
diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index f2bb3b1..3535da5 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -19,7 +19,6 @@
#include <rte_interrupts.h>
#include <rte_log.h>
#include <rte_debug.h>
-#include <rte_pci.h>
#include <rte_atomic.h>
#include <rte_branch_prediction.h>
#include <rte_memory.h>
@@ -235,7 +234,7 @@ int rte_dpaa_portal_init(void *arg)
BUS_INIT_FUNC_TRACE();
- if ((uint64_t)arg == 1 || cpu == LCORE_ID_ANY)
+ if ((size_t)arg == 1 || cpu == LCORE_ID_ANY)
cpu = rte_get_master_lcore();
/* if the core id is not supported */
else
diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 18681cf..c5191ce 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -84,7 +84,7 @@ dpaa_sec_alloc_ctx(dpaa_sec_session *ses)
dcbz_64(&ctx->job.sg[SG_CACHELINE_3]);
ctx->ctx_pool = ses->ctx_pool;
- ctx->vtop_offset = (uint64_t) ctx
+ ctx->vtop_offset = (size_t) ctx
- rte_mempool_virt2iova(ctx);
return ctx;
@@ -97,7 +97,7 @@ dpaa_mem_vtop(void *vaddr)
uint64_t vaddr_64, paddr;
int i;
- vaddr_64 = (uint64_t)vaddr;
+ vaddr_64 = (size_t)vaddr;
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (vaddr_64 >= memseg[i].addr_64 &&
vaddr_64 < memseg[i].addr_64 + memseg[i].len) {
@@ -107,14 +107,14 @@ dpaa_mem_vtop(void *vaddr)
return (rte_iova_t)paddr;
}
}
- return (rte_iova_t)(NULL);
+ return (size_t)NULL;
}
/* virtual address conversin when mempool support is available for ctx */
static inline phys_addr_t
dpaa_mem_vtop_ctx(struct dpaa_sec_op_ctx *ctx, void *vaddr)
{
- return (uint64_t)vaddr - ctx->vtop_offset;
+ return (size_t)vaddr - ctx->vtop_offset;
}
static inline void *
@@ -125,8 +125,8 @@ dpaa_mem_ptov(rte_iova_t paddr)
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (paddr >= memseg[i].iova &&
- (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
- return (void *)(memseg[i].addr_64 +
+ paddr < memseg[i].iova + memseg[i].len)
+ return (void *)(size_t)(memseg[i].addr_64 +
(paddr - memseg[i].iova));
}
return NULL;
@@ -406,7 +406,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_c.key = (uint64_t)ses->cipher_key.data;
+ alginfo_c.key = (size_t)ses->cipher_key.data;
alginfo_c.keylen = ses->cipher_key.length;
alginfo_c.key_enc_flags = 0;
alginfo_c.key_type = RTA_DATA_IMM;
@@ -424,7 +424,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_a.key = (uint64_t)ses->auth_key.data;
+ alginfo_a.key = (size_t)ses->auth_key.data;
alginfo_a.keylen = ses->auth_key.length;
alginfo_a.key_enc_flags = 0;
alginfo_a.key_type = RTA_DATA_IMM;
@@ -439,7 +439,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
PMD_TX_LOG(ERR, "not supported aead alg\n");
return -ENOTSUP;
}
- alginfo.key = (uint64_t)ses->aead_key.data;
+ alginfo.key = (size_t)ses->aead_key.data;
alginfo.keylen = ses->aead_key.length;
alginfo.key_enc_flags = 0;
alginfo.key_type = RTA_DATA_IMM;
@@ -463,7 +463,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_c.key = (uint64_t)ses->cipher_key.data;
+ alginfo_c.key = (size_t)ses->cipher_key.data;
alginfo_c.keylen = ses->cipher_key.length;
alginfo_c.key_enc_flags = 0;
alginfo_c.key_type = RTA_DATA_IMM;
@@ -474,7 +474,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_a.key = (uint64_t)ses->auth_key.data;
+ alginfo_a.key = (size_t)ses->auth_key.data;
alginfo_a.keylen = ses->auth_key.length;
alginfo_a.key_enc_flags = 0;
alginfo_a.key_type = RTA_DATA_IMM;
@@ -493,15 +493,15 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
if (cdb->sh_desc[2] & 1)
alginfo_c.key_type = RTA_DATA_IMM;
else {
- alginfo_c.key = (uint64_t)dpaa_mem_vtop(
- (void *)alginfo_c.key);
+ alginfo_c.key = (size_t)dpaa_mem_vtop(
+ (void *)(size_t)alginfo_c.key);
alginfo_c.key_type = RTA_DATA_PTR;
}
if (cdb->sh_desc[2] & (1<<1))
alginfo_a.key_type = RTA_DATA_IMM;
else {
- alginfo_a.key = (uint64_t)dpaa_mem_vtop(
- (void *)alginfo_a.key);
+ alginfo_a.key = (size_t)dpaa_mem_vtop(
+ (void *)(size_t)alginfo_a.key);
alginfo_a.key_type = RTA_DATA_PTR;
}
cdb->sh_desc[0] = 0;
diff --git a/drivers/mempool/dpaa/dpaa_mempool.c b/drivers/mempool/dpaa/dpaa_mempool.c
index fb3b6ba..7b82f4b 100644
--- a/drivers/mempool/dpaa/dpaa_mempool.c
+++ b/drivers/mempool/dpaa/dpaa_mempool.c
@@ -115,7 +115,8 @@ dpaa_buf_free(struct dpaa_bp_info *bp_info, uint64_t addr)
struct bm_buffer buf;
int ret;
- DPAA_MEMPOOL_DEBUG("Free 0x%lx to bpid: %d", addr, bp_info->bpid);
+ DPAA_MEMPOOL_DEBUG("Free 0x%" PRIx64 " to bpid: %d",
+ addr, bp_info->bpid);
bm_buffer_set64(&buf, addr);
retry:
@@ -154,8 +155,7 @@ dpaa_mbuf_free_bulk(struct rte_mempool *pool,
if (unlikely(!bp_info->ptov_off)) {
/* buffers are from single mem segment */
if (bp_info->flags & DPAA_MPOOL_SINGLE_SEGMENT) {
- bp_info->ptov_off
- = (uint64_t)obj_table[i] - phy;
+ bp_info->ptov_off = (size_t)obj_table[i] - phy;
rte_dpaa_bpid_info[bp_info->bpid].ptov_off
= bp_info->ptov_off;
}
@@ -282,8 +282,8 @@ dpaa_register_memory_area(const struct rte_mempool *mp,
bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;
- DPAA_MEMPOOL_DEBUG("Req size %lu vs Available %u\n",
- len, total_elt_sz * mp->size);
+ DPAA_MEMPOOL_DEBUG("Req size %" PRIx64 " vs Available %u\n",
+ (uint64_t)len, total_elt_sz * mp->size);
/* Detect pool area has sufficient space for elements in this memzone */
if (len >= total_elt_sz * mp->size)
diff --git a/drivers/mempool/dpaa/dpaa_mempool.h b/drivers/mempool/dpaa/dpaa_mempool.h
index 9435dd2..092f326 100644
--- a/drivers/mempool/dpaa/dpaa_mempool.h
+++ b/drivers/mempool/dpaa/dpaa_mempool.h
@@ -46,7 +46,7 @@ static inline void *
DPAA_MEMPOOL_PTOV(struct dpaa_bp_info *bp_info, uint64_t addr)
{
if (bp_info->ptov_off)
- return ((void *)(addr + bp_info->ptov_off));
+ return ((void *) (size_t)(addr + bp_info->ptov_off));
return rte_dpaa_mem_ptov(addr);
}
diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 0dea8e7..8d53137 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -90,11 +90,10 @@ static inline void dpaa_slow_parsing(struct rte_mbuf *m __rte_unused,
/*TBD:XXX: to be implemented*/
}
-static inline void dpaa_eth_packet_info(struct rte_mbuf *m,
- uint64_t fd_virt_addr)
+static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
{
struct annotations_t *annot = GET_ANNOTATIONS(fd_virt_addr);
- uint64_t prs = *((uint64_t *)(&annot->parse)) & DPAA_PARSE_MASK;
+ uint64_t prs = *((uintptr_t *)(&annot->parse)) & DPAA_PARSE_MASK;
DPAA_DP_LOG(DEBUG, " Parsing mbuf: %p with annotations: %p", m, annot);
@@ -351,7 +350,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
prev_seg = cur_seg;
}
- dpaa_eth_packet_info(first_seg, (uint64_t)vaddr);
+ dpaa_eth_packet_info(first_seg, vaddr);
rte_pktmbuf_free_seg(temp);
return first_seg;
@@ -394,7 +393,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
mbuf->ol_flags = 0;
mbuf->next = NULL;
rte_mbuf_refcnt_set(mbuf, 1);
- dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
return mbuf;
}
@@ -455,7 +454,7 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
mbuf->ol_flags = 0;
mbuf->next = NULL;
rte_mbuf_refcnt_set(mbuf, 1);
- dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
}
}
@@ -593,7 +592,7 @@ uint16_t dpaa_eth_queue_rx(void *q,
static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info)
{
int ret;
- uint64_t buf = 0;
+ size_t buf = 0;
struct bm_buffer bufs;
ret = bman_acquire(bp_info->bp, &bufs, 1, 0);
@@ -602,10 +601,10 @@ static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info)
return (void *)buf;
}
- DPAA_DP_LOG(DEBUG, "got buffer 0x%lx from pool %d",
+ DPAA_DP_LOG(DEBUG, "got buffer 0x%" PRIx64 " from pool %d",
(uint64_t)bufs.addr, bufs.bpid);
- buf = (uint64_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr)
+ buf = (size_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr)
- bp_info->meta_data_size;
if (!buf)
goto out;
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 04/10] dpaa2: prepare for 32 bit compilation
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (2 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 03/10] dpaa: prepare for 32 bit compilation Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 05/10] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
` (6 subsequent siblings)
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch prepare the dpaa2 drivers for compilation on 32 bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/fslmc_vfio.c | 10 ++---
drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 4 +-
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++++++---------
drivers/bus/fslmc/qbman/qbman_portal.c | 14 +++----
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 60 ++++++++++++++---------------
drivers/event/dpaa2/dpaa2_eventdev.c | 6 +--
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 ++--
drivers/net/dpaa2/Makefile | 1 -
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +-
drivers/net/dpaa2/dpaa2_ethdev.c | 6 +--
drivers/net/dpaa2/dpaa2_rxtx.c | 38 ++++++++----------
12 files changed, 90 insertions(+), 98 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 1241295..e840ad6 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -76,7 +76,7 @@ fslmc_get_container_group(int *groupid)
if (!g_container) {
container = getenv("DPRC");
if (container == NULL) {
- RTE_LOG(WARNING, EAL, "DPAA2: DPRC not available\n");
+ RTE_LOG(DEBUG, EAL, "DPAA2: DPRC not available\n");
return -EINVAL;
}
@@ -270,7 +270,7 @@ int rte_fslmc_vfio_dmamap(void)
static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
{
- int64_t v_addr = (int64_t)MAP_FAILED;
+ intptr_t v_addr = (intptr_t)MAP_FAILED;
int32_t ret, mc_fd;
struct vfio_device_info d_info = { .argsz = sizeof(d_info) };
@@ -301,7 +301,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
FSLMC_VFIO_LOG(DEBUG, "region offset = %llx , region size = %llx",
reg_info.offset, reg_info.size);
- v_addr = (uint64_t)mmap(NULL, reg_info.size,
+ v_addr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
mc_fd, reg_info.offset);
@@ -469,7 +469,7 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev)
static int
fslmc_process_mcp(struct rte_dpaa2_device *dev)
{
- int64_t v_addr;
+ intptr_t v_addr;
char *dev_name;
struct fsl_mc_io dpmng = {0};
struct mc_version mc_ver_info = {0};
@@ -489,7 +489,7 @@ fslmc_process_mcp(struct rte_dpaa2_device *dev)
}
v_addr = vfio_map_mcp_obj(&vfio_group, dev_name);
- if (v_addr == (int64_t)MAP_FAILED) {
+ if (v_addr == (intptr_t)MAP_FAILED) {
FSLMC_VFIO_LOG(ERR, "Error mapping region (errno = %d)",
errno);
free(rte_mcp_ptr_list);
diff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h
index a3c3e79..ac91961 100644
--- a/drivers/bus/fslmc/mc/fsl_mc_cmd.h
+++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h
@@ -27,7 +27,7 @@
#define le32_to_cpu rte_le_to_cpu_32
#define le16_to_cpu rte_le_to_cpu_16
-#define BITS_PER_LONG 64
+#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
#define GENMASK(h, l) \
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index eefde15..9bbc219 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -427,7 +427,7 @@ dpaa2_create_dpio_device(int vdev_fd,
}
dpio_dev->ce_size = reg_info.size;
- dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
+ dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
vdev_fd, reg_info.offset);
@@ -439,7 +439,7 @@ dpaa2_create_dpio_device(int vdev_fd,
}
dpio_dev->ci_size = reg_info.size;
- dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
+ dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
vdev_fd, reg_info.offset);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index d421dbf..3191ead 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -174,7 +174,7 @@ enum qbman_fd_format {
};
/*Macros to define operations on FD*/
#define DPAA2_SET_FD_ADDR(fd, addr) do { \
- (fd)->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
+ (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
(fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
} while (0)
#define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
@@ -193,33 +193,32 @@ enum qbman_fd_format {
#define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
#define DPAA2_SET_FD_FLC(fd, addr) do { \
- (fd)->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
+ (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
(fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
} while (0)
#define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
#define DPAA2_GET_FLE_ADDR(fle) \
(uint64_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
#define DPAA2_SET_FLE_ADDR(fle, addr) do { \
- (fle)->addr_lo = lower_32_bits((uint64_t)addr); \
- (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
+ (fle)->addr_lo = lower_32_bits((size_t)addr); \
+ (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
} while (0)
#define DPAA2_GET_FLE_CTXT(fle) \
- (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \
- (fle)->reserved[0])
+ ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
#define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
- (fle)->reserved[0] = lower_32_bits((uint64_t)addr); \
- (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
+ (fle)->reserved[0] = lower_32_bits((size_t)addr); \
+ (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
} while (0)
#define DPAA2_SET_FLE_OFFSET(fle, offset) \
((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
-#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
+#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
#define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
-#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 31)
+#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
#define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
#define DPAA2_SET_FD_COMPOUND_FMT(fd) \
((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
#define DPAA2_GET_FD_ADDR(fd) \
-((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
+((size_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
#define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
#define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
@@ -231,7 +230,7 @@ enum qbman_fd_format {
(((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
#define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
- ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
+ ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
#define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
@@ -265,14 +264,14 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr)
int i;
if (dpaa2_virt_mode)
- return (void *)paddr;
+ return (void *)(size_t)paddr;
memseg = rte_eal_get_physmem_layout();
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (paddr >= memseg[i].iova &&
- (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
- return (void *)(memseg[i].addr_64
+ paddr < memseg[i].iova + memseg[i].len)
+ return (void *)(size_t)(memseg[i].addr_64
+ (paddr - memseg[i].iova));
}
return NULL;
@@ -295,7 +294,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
return memseg[i].iova
+ (vaddr - memseg[i].addr_64);
}
- return (phys_addr_t)(NULL);
+ return (size_t)(NULL);
}
/**
@@ -311,18 +310,18 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
/**
* macro to convert Virtual address to IOVA
*/
-#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
+#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
/**
* macro to convert IOVA to Virtual address
*/
-#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
+#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
/**
* macro to convert modify the memory containing IOVA to Virtual address
*/
#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
- {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
+ {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
#else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c
index e221733..713ec96 100644
--- a/drivers/bus/fslmc/qbman/qbman_portal.c
+++ b/drivers/bus/fslmc/qbman/qbman_portal.c
@@ -553,10 +553,9 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s,
/* Flush all the cacheline without load/store in between */
eqcr_pi = s->eqcr.pi;
- addr_cena = (uint64_t)s->sys.addr_cena;
+ addr_cena = (size_t)s->sys.addr_cena;
for (i = 0; i < num_enqueued; i++) {
- dcbf((uint64_t *)(addr_cena +
- QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
eqcr_pi++;
eqcr_pi &= 0xF;
}
@@ -620,10 +619,9 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
/* Flush all the cacheline without load/store in between */
eqcr_pi = s->eqcr.pi;
- addr_cena = (uint64_t)s->sys.addr_cena;
+ addr_cena = (size_t)s->sys.addr_cena;
for (i = 0; i < num_enqueued; i++) {
- dcbf((uint64_t *)(addr_cena +
- QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
eqcr_pi++;
eqcr_pi &= 0xF;
}
@@ -690,7 +688,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
dma_addr_t storage_phys,
int stash)
{
- d->pull.rsp_addr_virt = (uint64_t)storage;
+ d->pull.rsp_addr_virt = (size_t)storage;
if (!storage) {
d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
@@ -749,7 +747,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
}
d->pull.tok = s->sys.idx + 1;
- s->vdq.storage = (void *)d->pull.rsp_addr_virt;
+ s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt;
p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
memcpy(&p[1], &cl[1], 12);
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 9a790dd..a7f3b04 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -77,11 +77,11 @@ build_proto_fd(dpaa2_sec_session *sess,
DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
DPAA2_SET_FD_OFFSET(fd, sym_op->m_src->data_off);
DPAA2_SET_FD_LEN(fd, sym_op->m_src->pkt_len);
- DPAA2_SET_FD_FLC(fd, ((uint64_t)flc));
+ DPAA2_SET_FD_FLC(fd, (ptrdiff_t)flc);
/* save physical address of mbuf */
op->sym->aead.digest.phys_addr = mbuf->buf_iova;
- mbuf->buf_iova = (uint64_t)op;
+ mbuf->buf_iova = (size_t)op;
return 0;
}
@@ -118,7 +118,7 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_SG_MEM_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -269,7 +269,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_POOL_BUF_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
if (likely(bpid < MAX_BPID)) {
@@ -414,7 +414,7 @@ build_authenc_sg_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_SG_MEM_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -563,7 +563,7 @@ build_authenc_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_POOL_BUF_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
if (likely(bpid < MAX_BPID)) {
@@ -692,7 +692,7 @@ static inline int build_auth_sg_fd(
memset(fle, 0, FLE_SG_MEM_SIZE);
/* first FLE entry used to store mbuf and session ctxt */
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
sge = fle + 3;
@@ -773,7 +773,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
* We can have a better approach to use the inline Mbuf
*/
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
if (likely(bpid < MAX_BPID)) {
@@ -865,7 +865,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
memset(fle, 0, FLE_SG_MEM_SIZE);
/* first FLE entry used to store mbuf and session ctxt */
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -987,7 +987,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
* We can have a better approach to use the inline Mbuf
*/
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
@@ -1206,7 +1206,7 @@ sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id)
DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
- op = (struct rte_crypto_op *)mbuf->buf_iova;
+ op = (struct rte_crypto_op *)(size_t)mbuf->buf_iova;
mbuf->buf_iova = op->sym->aead.digest.phys_addr;
op->sym->aead.digest.phys_addr = 0L;
@@ -1276,7 +1276,7 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id)
/* free the fle memory */
if (likely(rte_pktmbuf_is_contiguous(src))) {
- priv = (struct ctxt_priv *)DPAA2_GET_FLE_CTXT(fle - 1);
+ priv = (struct ctxt_priv *)(size_t)DPAA2_GET_FLE_CTXT(fle - 1);
rte_mempool_put(priv->fle_pool, (void *)(fle-1));
} else
rte_free((void *)(fle-1));
@@ -1455,7 +1455,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
dev->data->queue_pairs[qp_id] = qp;
cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;
- cfg.user_ctx = (uint64_t)(&qp->rx_vq);
+ cfg.user_ctx = (size_t)(&qp->rx_vq);
retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,
qp_id, &cfg);
return retcode;
@@ -1536,7 +1536,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
memcpy(session->cipher_key.data, xform->cipher.key.data,
xform->cipher.key.length);
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -1595,10 +1595,10 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
@@ -1651,7 +1651,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, xform->auth.key.data,
xform->auth.key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -1720,10 +1720,10 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -1786,7 +1786,7 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev,
session->aead_key.length = aead_xform->key.length;
ctxt->auth_only_len = aead_xform->aad_length;
- aeaddata.key = (uint64_t)session->aead_key.data;
+ aeaddata.key = (size_t)session->aead_key.data;
aeaddata.keylen = session->aead_key.length;
aeaddata.key_enc_flags = 0;
aeaddata.key_type = RTA_DATA_IMM;
@@ -1840,10 +1840,10 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev,
session->digest_length);
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -1928,7 +1928,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, auth_xform->key.data,
auth_xform->key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -1988,7 +1988,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
auth_xform->algo);
goto error_out;
}
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -2066,10 +2066,10 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -2202,7 +2202,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, auth_xform->key.data,
auth_xform->key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -2261,7 +2261,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
auth_xform->algo);
goto out;
}
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -2345,10 +2345,10 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
/* Enable the stashing control bit */
DPAA2_SET_FLC_RSC(flc);
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq) | 0x14);
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
/* Set EWS bit i.e. enable write-safe */
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index c3e6fbf..9bdc014 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -126,7 +126,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
goto send_partial;
}
rte_memcpy(ev_temp, event, sizeof(struct rte_event));
- DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
+ DPAA2_SET_FD_ADDR((&fd_arr[loop]), (size_t)ev_temp);
DPAA2_SET_FD_LEN((&fd_arr[loop]),
sizeof(struct rte_event));
}
@@ -258,7 +258,7 @@ dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
qbman_swp_prefetch_dqrr_next(swp);
fd = qbman_result_DQ_fd(dq);
- rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
+ rxq = (struct dpaa2_queue *)(size_t)qbman_result_DQ_fqd_ctx(dq);
if (rxq) {
rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
} else {
@@ -736,7 +736,7 @@ dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
dpaa2_eventdev_process_atomic;
for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
- rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
+ rx_queue_cfg.user_ctx = (size_t)(&dpci_dev->queue[i]);
ret = dpci_set_rx_queue(&dpci_dev->dpci,
CMD_PRI_LOW,
dpci_dev->token, i,
diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
index 2bd62e8..1a618ae 100644
--- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
+++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
@@ -242,7 +242,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
#endif
struct qbman_swp *swp;
uint16_t bpid;
- uint64_t bufs[DPAA2_MBUF_MAX_ACQ_REL];
+ size_t bufs[DPAA2_MBUF_MAX_ACQ_REL];
int i, ret;
unsigned int n = 0;
struct dpaa2_bp_info *bp_info;
@@ -270,10 +270,10 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
* then the remainder.
*/
if ((count - n) > DPAA2_MBUF_MAX_ACQ_REL) {
- ret = qbman_swp_acquire(swp, bpid, bufs,
+ ret = qbman_swp_acquire(swp, bpid, (void *)bufs,
DPAA2_MBUF_MAX_ACQ_REL);
} else {
- ret = qbman_swp_acquire(swp, bpid, bufs,
+ ret = qbman_swp_acquire(swp, bpid, (void *)bufs,
count - n);
}
/* In case of less than requested number of buffers available
@@ -290,7 +290,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
}
/* assigning mbuf from the acquired objects */
for (i = 0; (i < ret) && bufs[i]; i++) {
- DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], uint64_t);
+ DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], size_t);
obj_table[n] = (struct rte_mbuf *)
(bufs[i] - bp_info->meta_data_size);
PMD_TX_LOG(DEBUG, "Acquired %p address %p from BMAN",
diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile
index 5a93a0b..068e9d3 100644
--- a/drivers/net/dpaa2/Makefile
+++ b/drivers/net/dpaa2/Makefile
@@ -25,7 +25,6 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include
CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc
CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal
CFLAGS += -I$(RTE_SDK)/drivers/mempool/dpaa2
-CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2
CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
# versioning export map
diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
index b93376d..4b60f56 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
@@ -50,7 +50,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg);
if (ret) {
- PMD_INIT_LOG(ERR, "given rss_hf (%lx) not supported",
+ PMD_INIT_LOG(ERR, "given rss_hf (%" PRIx64 ") not supported",
req_dist_set);
rte_free(p_params);
return ret;
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 09a11d6..fd5897e 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -445,7 +445,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
memset(&cfg, 0, sizeof(struct dpni_queue));
options = options | DPNI_QUEUE_OPT_USER_CTX;
- cfg.user_context = (uint64_t)(dpaa2_q);
+ cfg.user_context = (size_t)(dpaa2_q);
/*if ls2088 or rev2 device, enable the stashing */
@@ -560,7 +560,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
*/
cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
cong_notif_cfg.message_ctx = 0;
- cong_notif_cfg.message_iova = (uint64_t)dpaa2_q->cscn;
+ cong_notif_cfg.message_iova = (size_t)dpaa2_q->cscn;
cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
cong_notif_cfg.notification_mode =
DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
@@ -1702,7 +1702,7 @@ int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
}
options |= DPNI_QUEUE_OPT_USER_CTX;
- cfg.user_context = (uint64_t)(dpaa2_ethq);
+ cfg.user_context = (size_t)(dpaa2_ethq);
ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
dpaa2_ethq->tc_index, flow_id, options, &cfg);
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 183293c..f33b1fd 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -21,7 +21,6 @@
#include <dpaa2_hw_pvt.h>
#include <dpaa2_hw_dpio.h>
#include <dpaa2_hw_mempool.h>
-#include <dpaa2_eventdev.h>
#include "dpaa2_ethdev.h"
#include "base/dpaa2_hw_dpni_annot.h"
@@ -104,11 +103,9 @@ dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc)
}
static inline uint32_t __attribute__((hot))
-dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
+dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation)
{
uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
- struct dpaa2_annot_hdr *annotation =
- (struct dpaa2_annot_hdr *)hw_annot_addr;
PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4);
if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
@@ -167,7 +164,7 @@ dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
}
static inline uint32_t __attribute__((hot))
-dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
+dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
{
struct dpaa2_annot_hdr *annotation =
(struct dpaa2_annot_hdr *)hw_annot_addr;
@@ -207,25 +204,24 @@ dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
break;
}
- return dpaa2_dev_rx_parse_slow(hw_annot_addr);
+ return dpaa2_dev_rx_parse_slow(annotation);
}
static inline struct rte_mbuf *__attribute__((hot))
eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
{
struct qbman_sge *sgt, *sge;
- dma_addr_t sg_addr;
+ size_t sg_addr, fd_addr;
int i = 0;
- uint64_t fd_addr;
struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
- fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
+ fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
/* Get Scatter gather table address */
sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
sge = &sgt[i++];
- sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
+ sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
/* First Scatter gather entry */
first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
@@ -243,14 +239,14 @@ eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
DPAA2_GET_FD_FRC_PARSE_SUM(fd));
else
first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
- + DPAA2_FD_PTA_SIZE);
+ (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ + DPAA2_FD_PTA_SIZE));
rte_mbuf_refcnt_set(first_seg, 1);
cur_seg = first_seg;
while (!DPAA2_SG_IS_FINAL(sge)) {
sge = &sgt[i++];
- sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(
+ sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
DPAA2_GET_FLE_ADDR(sge));
next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
@@ -299,8 +295,8 @@ eth_fd_to_mbuf(const struct qbman_fd *fd)
dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd));
else
mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
- + DPAA2_FD_PTA_SIZE);
+ (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ + DPAA2_FD_PTA_SIZE));
PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
"fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n",
@@ -340,7 +336,7 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
/*Set Scatter gather table and Scatter gather entries*/
sgt = (struct qbman_sge *)(
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ DPAA2_GET_FD_OFFSET(fd));
for (i = 0; i < mbuf->nb_segs; i++) {
@@ -523,8 +519,8 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
}
dq_storage = q_storage->active_dqs;
- rte_prefetch0((void *)((uint64_t)(dq_storage)));
- rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
+ rte_prefetch0((void *)(size_t)(dq_storage));
+ rte_prefetch0((void *)(size_t)(dq_storage + 1));
/* Prepare next pull descriptor. This will give space for the
* prefething done on DQRR entries
@@ -554,7 +550,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
*/
while (!qbman_check_new_result(dq_storage))
;
- rte_prefetch0((void *)((uint64_t)(dq_storage + 2)));
+ rte_prefetch0((void *)((size_t)(dq_storage + 2)));
/* Check whether Last Pull command is Expired and
* setting Condition for Loop termination
*/
@@ -569,7 +565,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
next_fd = qbman_result_DQ_fd(dq_storage + 1);
/* Prefetch Annotation address for the parse results */
- rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(next_fd)
+ rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd)
+ DPAA2_FD_PTA_SIZE + 16));
if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
@@ -726,7 +722,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
fd_arr[loop].simple.frc = 0;
DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
- DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
+ DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL);
if (likely(RTE_MBUF_DIRECT(*bufs))) {
mp = (*bufs)->pool;
/* Check the basic scenario and set
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 05/10] bus/fslmc: add 32 bit functional support for ARM
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (3 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 04/10] dpaa2: " Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 06/10] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
` (5 subsequent siblings)
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch adds the functional logic to make the dpaa2 drivers
work on 32bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++++++++++++++++++++++--
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 9 +++++++++
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h
index 846788e..0b460c4 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys.h
@@ -20,6 +20,9 @@
#include "qbman_sys_decl.h"
+#define CENA_WRITE_ENABLE 0
+#define CINH_WRITE_ENABLE 1
+
/* Debugging assists */
static inline void __hexdump(unsigned long start, unsigned long end,
unsigned long p, size_t sz, const unsigned char *c)
@@ -178,7 +181,11 @@ static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
s->addr_cena, s->idx, offset);
#endif
QBMAN_BUG_ON(offset & 63);
+#ifdef RTE_ARCH_64
return (s->addr_cena + offset);
+#else
+ return (s->addr_cinh + offset);
+#endif
}
static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
@@ -191,11 +198,19 @@ static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
s->addr_cena, s->idx, offset, shadow);
hexdump(cmd, 64);
#endif
+#ifdef RTE_ARCH_64
for (loop = 15; loop >= 1; loop--)
__raw_writel(shadow[loop], s->addr_cena +
offset + loop * 4);
lwsync();
__raw_writel(shadow[0], s->addr_cena + offset);
+#else
+ for (loop = 15; loop >= 1; loop--)
+ __raw_writel(shadow[loop], s->addr_cinh +
+ offset + loop * 4);
+ lwsync();
+ __raw_writel(shadow[0], s->addr_cinh + offset);
+#endif
dcbf(s->addr_cena + offset);
}
@@ -224,9 +239,15 @@ static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
s->addr_cena, s->idx, offset, shadow);
#endif
+#ifdef RTE_ARCH_64
for (loop = 0; loop < 16; loop++)
shadow[loop] = __raw_readl(s->addr_cena + offset
+ loop * 4);
+#else
+ for (loop = 0; loop < 16; loop++)
+ shadow[loop] = __raw_readl(s->addr_cinh + offset
+ + loop * 4);
+#endif
#ifdef QBMAN_CENA_TRACE
hexdump(shadow, 64);
#endif
@@ -313,6 +334,11 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
uint8_t dqrr_size)
{
uint32_t reg;
+#ifndef RTE_ARCH_64
+ uint8_t wn = CENA_WRITE_ENABLE;
+#else
+ uint8_t wn = CINH_WRITE_ENABLE;
+#endif
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
@@ -333,10 +359,10 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
QBMAN_BUG_ON(reg);
#endif
if (s->eqcr_mode == qman_eqcr_vb_array)
- reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1,
+ reg = qbman_set_swp_cfg(dqrr_size, wn, 0, 3, 2, 3, 1, 1, 1, 1,
1, 1);
else
- reg = qbman_set_swp_cfg(dqrr_size, 0, 1, 3, 2, 2, 1, 1, 1, 1,
+ reg = qbman_set_swp_cfg(dqrr_size, wn, 2, 3, 2, 2, 1, 1, 1, 1,
1, 1);
qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
index f82bb18..5640b04 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
@@ -15,6 +15,7 @@
/****************/
/* arch assists */
/****************/
+#if defined(RTE_ARCH_ARM64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define lwsync() { asm volatile("dmb st" : : : "memory"); }
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
@@ -28,3 +29,11 @@ static inline void prefetch_for_store(void *p)
{
asm volatile("prfm pstl1keep, [%0, #0]" : : "r" (p));
}
+#elif defined(RTE_ARCH_ARM)
+#define dcbz(p) memset(p, 0, 64)
+#define lwsync() { asm volatile("dmb st" : : : "memory"); }
+#define dcbf(p) RTE_SET_USED(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 06/10] bus/dpaa: enabling dpaa compilation for other platforms
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (4 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 05/10] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 07/10] bus/fslmc: enabling dpaa2 " Hemant Agrawal
` (4 subsequent siblings)
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/include/compat.h | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/dpaa/include/compat.h b/drivers/bus/dpaa/include/compat.h
index 53707bb..e4b5702 100644
--- a/drivers/bus/dpaa/include/compat.h
+++ b/drivers/bus/dpaa/include/compat.h
@@ -39,6 +39,7 @@
#include <rte_spinlock.h>
#include <rte_common.h>
#include <rte_debug.h>
+#include <rte_cycles.h>
/* The following definitions are primarily to allow the single-source driver
* interfaces to be included by arbitrary program code. Ie. for interfaces that
@@ -127,13 +128,15 @@ static inline void out_be32(volatile void *__p, u32 val)
*p = rte_cpu_to_be_32(val);
}
+#define hwsync() rte_rmb()
+#define lwsync() rte_wmb()
+
#define dcbt_ro(p) __builtin_prefetch(p, 0)
#define dcbt_rw(p) __builtin_prefetch(p, 1)
+#if defined(RTE_ARCH_ARM64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define dcbz_64(p) dcbz(p)
-#define hwsync() rte_rmb()
-#define lwsync() rte_wmb()
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
#define dcbf_64(p) dcbf(p)
#define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); }
@@ -144,9 +147,27 @@ static inline void out_be32(volatile void *__p, u32 val)
asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); \
} while (0)
+#elif defined(RTE_ARCH_ARM)
+#define dcbz(p) memset((p), 0, 32)
+#define dcbz_64(p) memset((p), 0, 64)
+#define dcbf(p) RTE_SET_USED(p)
+#define dcbf_64(p) dcbf(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define dcbit_ro(p) RTE_SET_USED(p)
+
+#else
+#define dcbz(p) RTE_SET_USED(p)
+#define dcbz_64(p) dcbz(p)
+#define dcbf(p) RTE_SET_USED(p)
+#define dcbf_64(p) dcbf(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define dcbit_ro(p) RTE_SET_USED(p)
+#endif
+
#define barrier() { asm volatile ("" : : : "memory"); }
#define cpu_relax barrier
+#if defined(RTE_ARCH_ARM64)
static inline uint64_t mfatb(void)
{
uint64_t ret, ret_new, timeout = 200;
@@ -160,6 +181,11 @@ static inline uint64_t mfatb(void)
DPAA_BUG_ON(!timeout && (ret != ret_new));
return ret * 64;
}
+#else
+
+#define mfatb rte_rdtsc
+
+#endif
/* Spin for a few cycles without bothering the bus */
static inline void cpu_spin(int cycles)
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 07/10] bus/fslmc: enabling dpaa2 compilation for other platforms
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (5 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 06/10] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
` (3 subsequent siblings)
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
index 5640b04..fa6977f 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
@@ -36,4 +36,18 @@ static inline void prefetch_for_store(void *p)
#define dccivac(p) RTE_SET_USED(p)
#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+
+#else
+#define dcbz(p) RTE_SET_USED(p)
+#define lwsync()
+#define dcbf(p) RTE_SET_USED(p)
+#define dccivac(p) RTE_SET_USED(p)
+static inline void prefetch_for_load(void *p)
+{
+ RTE_SET_USED(p);
+}
+static inline void prefetch_for_store(void *p)
+{
+ RTE_SET_USED(p);
+}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 08/10] config: add dpaaX build support in common linuxapp
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (6 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 07/10] bus/fslmc: enabling dpaa2 " Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-09 17:11 ` Thomas Monjalon
2018-03-01 7:33 ` [PATCH v2 09/10] build: add meson support for dpaaX platforms Hemant Agrawal
` (2 subsequent siblings)
10 siblings, 1 reply; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
config/common_armv8a_linuxapp | 58 -------------------------------------------
config/common_linuxapp | 37 +++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 58 deletions(-)
diff --git a/config/common_armv8a_linuxapp b/config/common_armv8a_linuxapp
index 507b28a..111c005 100644
--- a/config/common_armv8a_linuxapp
+++ b/config/common_armv8a_linuxapp
@@ -36,61 +36,3 @@ CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
CONFIG_RTE_LIBRTE_AVP_PMD=n
CONFIG_RTE_SCHED_VECTOR=n
-
-#
-# ARMv8 Specific driver compilation flags
-#
-
-#
-# Compile NXP DPAA Bus
-#
-CONFIG_RTE_LIBRTE_DPAA_BUS=y
-CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
-
-#
-# Compile NXP DPAA2 FSL-MC Bus
-#
-CONFIG_RTE_LIBRTE_FSLMC_BUS=y
-
-#
-# Compile NXP DPAA Mempool
-#
-CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y
-
-#
-# Compile NXP DPAA2 Mempool
-#
-CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
-
-#
-# Compile bust-oriented NXP DPAA PMD
-#
-CONFIG_RTE_LIBRTE_DPAA_PMD=y
-
-#
-# Compile burst-oriented NXP DPAA2 PMD driver
-#
-CONFIG_RTE_LIBRTE_DPAA2_PMD=y
-
-#
-# Compile schedule-oriented NXP DPAA Event Dev PMD
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y
-
-#
-# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
-
-#
-# Compile NXP DPAA caam - crypto driver
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y
-CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
-CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
-
-#
-# Compile NXP DPAA2 crypto sec driver for CAAM HW
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
-CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
diff --git a/config/common_linuxapp b/config/common_linuxapp
index ff98f23..275c033 100644
--- a/config/common_linuxapp
+++ b/config/common_linuxapp
@@ -23,3 +23,40 @@ CONFIG_RTE_LIBRTE_NFP_PMD=y
CONFIG_RTE_LIBRTE_POWER=y
CONFIG_RTE_VIRTIO_USER=y
CONFIG_RTE_PROC_INFO=y
+#
+# ARMv8 Specific driver compilation flags
+#
+
+# Compile NXP DPAA Bus
+CONFIG_RTE_LIBRTE_DPAA_BUS=y
+CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
+
+# Compile NXP DPAA Mempool
+CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y
+
+# Compile bust-oriented NXP DPAA PMD
+CONFIG_RTE_LIBRTE_DPAA_PMD=y
+
+# Compile schedule-oriented NXP DPAA Event Dev PMD
+CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y
+
+# Compile NXP DPAA caam - crypto driver
+CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y
+CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
+CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
+
+# Compile NXP DPAA2 FSL-MC Bus
+CONFIG_RTE_LIBRTE_FSLMC_BUS=y
+
+# Compile NXP DPAA2 Mempool
+CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
+
+# Compile burst-oriented NXP DPAA2 PMD driver
+CONFIG_RTE_LIBRTE_DPAA2_PMD=y
+
+# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
+CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
+
+# Compile NXP DPAA2 crypto sec driver for CAAM HW
+CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
+CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 09/10] build: add meson support for dpaaX platforms
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (7 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 10/10] build: add meson cross compile config for dpaaX Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, Akhil Goyal
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
app/test-pmd/meson.build | 3 +++
config/arm/meson.build | 13 +++++++++++++
config/rte_config.h | 12 +++++++++++-
drivers/bus/dpaa/meson.build | 29 +++++++++++++++++++++++++++++
drivers/bus/fslmc/meson.build | 27 +++++++++++++++++++++++++++
drivers/bus/meson.build | 2 +-
drivers/crypto/dpaa2_sec/meson.build | 14 ++++++++++++++
drivers/crypto/dpaa_sec/meson.build | 13 +++++++++++++
drivers/crypto/meson.build | 4 +++-
drivers/event/dpaa/meson.build | 10 ++++++++++
drivers/event/dpaa2/meson.build | 11 +++++++++++
drivers/event/meson.build | 2 +-
drivers/mempool/dpaa/meson.build | 9 +++++++++
drivers/mempool/dpaa2/meson.build | 9 +++++++++
drivers/mempool/meson.build | 2 +-
drivers/net/dpaa/meson.build | 14 ++++++++++++++
drivers/net/dpaa2/meson.build | 15 +++++++++++++++
drivers/net/meson.build | 2 +-
18 files changed, 185 insertions(+), 6 deletions(-)
create mode 100644 drivers/bus/dpaa/meson.build
create mode 100644 drivers/bus/fslmc/meson.build
create mode 100644 drivers/crypto/dpaa2_sec/meson.build
create mode 100644 drivers/crypto/dpaa_sec/meson.build
create mode 100644 drivers/event/dpaa/meson.build
create mode 100644 drivers/event/dpaa2/meson.build
create mode 100644 drivers/mempool/dpaa/meson.build
create mode 100644 drivers/mempool/dpaa2/meson.build
create mode 100644 drivers/net/dpaa/meson.build
create mode 100644 drivers/net/dpaa2/meson.build
diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build
index 7ed74db..83f8bb1 100644
--- a/app/test-pmd/meson.build
+++ b/app/test-pmd/meson.build
@@ -32,6 +32,9 @@ if dpdk_conf.has('RTE_LIBRTE_SOFTNIC_PMD')
sources += files('tm.c')
deps += 'pmd_softnic'
endif
+if dpdk_conf.has('RTE_LIBRTE_DPAA_PMD')
+ deps += ['bus_dpaa', 'mempool_dpaa', 'pmd_dpaa']
+endif
dep_objs = []
foreach d:deps
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 4e788a4..c1ab6ed 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,17 @@ flags_cavium = [
['RTE_MAX_LCORE', 96],
['RTE_MAX_VFIO_GROUPS', 128],
['RTE_RING_USE_C11_MEM_MODEL', false]]
+flags_dpaa = [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16]]
+flags_dpaa2 = [
+ ['RTE_MACHINE', '"dpaa2"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', 'n']]
## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -69,6 +80,8 @@ impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
impl_0x69 = ['Intel', flags_generic, machine_args_generic]
+impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
+impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
if cc.get_define('__clang__') != ''
diff --git a/config/rte_config.h b/config/rte_config.h
index 699878a..72c0aa2 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -74,10 +74,20 @@
/*
* Number of sessions to create in the session memory pool
- * on a single QuickAssist device.
+ * on a single instance of crypto HW device.
*/
+/* QuickAssist device */
#define RTE_QAT_PMD_MAX_NB_SESSIONS 2048
+/* DPAA2_SEC */
+#define RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS 2048
+
+/* DPAA_SEC */
+#define RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS 2048
+
+/* DPAA SEC max cryptodev devices*/
+#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
+
/* fm10k defines */
#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
diff --git a/drivers/bus/dpaa/meson.build b/drivers/bus/dpaa/meson.build
new file mode 100644
index 0000000..f5c6d7b
--- /dev/null
+++ b/drivers/bus/dpaa/meson.build
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['ethdev', 'eventdev']
+sources = files('base/fman/fman.c',
+ 'base/fman/fman_hw.c',
+ 'base/fman/netcfg_layer.c',
+ 'base/fman/of.c',
+ 'base/qbman/bman.c',
+ 'base/qbman/bman_driver.c',
+ 'base/qbman/dpaa_alloc.c',
+ 'base/qbman/dpaa_sys.c',
+ 'base/qbman/process.c',
+ 'base/qbman/qman.c',
+ 'base/qbman/qman_driver.c',
+ 'dpaa_bus.c')
+
+allow_experimental_apis = true
+
+if cc.has_argument('-Wno-cast-qual')
+ cflags += '-Wno-cast-qual'
+endif
+
+includes += include_directories('include', 'base/qbman')
+cflags += ['-D_GNU_SOURCE']
diff --git a/drivers/bus/fslmc/meson.build b/drivers/bus/fslmc/meson.build
new file mode 100644
index 0000000..e94340e
--- /dev/null
+++ b/drivers/bus/fslmc/meson.build
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['ethdev', 'eventdev', 'kvargs']
+sources = files('fslmc_bus.c',
+ 'fslmc_vfio.c',
+ 'mc/dpbp.c',
+ 'mc/dpci.c',
+ 'mc/dpcon.c',
+ 'mc/dpio.c',
+ 'mc/dpmng.c',
+ 'mc/mc_sys.c',
+ 'portal/dpaa2_hw_dpbp.c',
+ 'portal/dpaa2_hw_dpci.c',
+ 'portal/dpaa2_hw_dpio.c',
+ 'qbman/qbman_portal.c',
+ 'qbman/qbman_debug.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
+includes += include_directories('mc', 'qbman/include', 'portal')
+cflags += ['-D_GNU_SOURCE']
diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build
index c6af500..58dfbe2 100644
--- a/drivers/bus/meson.build
+++ b/drivers/bus/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['pci', 'vdev']
+drivers = ['dpaa', 'fslmc', 'pci', 'vdev']
std_deps = ['eal']
config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
driver_name_fmt = 'rte_bus_@0@'
diff --git a/drivers/crypto/dpaa2_sec/meson.build b/drivers/crypto/dpaa2_sec/meson.build
new file mode 100644
index 0000000..0fb4d96
--- /dev/null
+++ b/drivers/crypto/dpaa2_sec/meson.build
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_fslmc', 'security', 'mempool_dpaa2']
+sources = files('dpaa2_sec_dpseci.c',
+ 'mc/dpseci.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('mc', 'hw')
diff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build
new file mode 100644
index 0000000..8a57098
--- /dev/null
+++ b/drivers/crypto/dpaa_sec/meson.build
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_dpaa', 'security']
+sources = files('dpaa_sec.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('../dpaa2_sec/')
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 17041ad..736c9f5 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -1,7 +1,9 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['qat', 'null', 'openssl']
+drivers = ['dpaa_sec', 'dpaa2_sec',
+ 'openssl', 'null', 'qat']
+
std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
driver_name_fmt = 'rte_pmd_@0@'
diff --git a/drivers/event/dpaa/meson.build b/drivers/event/dpaa/meson.build
new file mode 100644
index 0000000..9bbd6c2
--- /dev/null
+++ b/drivers/event/dpaa/meson.build
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['mempool_dpaa', 'bus_dpaa', 'pmd_dpaa']
+sources = files('dpaa_eventdev.c')
+
+allow_experimental_apis = true
diff --git a/drivers/event/dpaa2/meson.build b/drivers/event/dpaa2/meson.build
new file mode 100644
index 0000000..835460c
--- /dev/null
+++ b/drivers/event/dpaa2/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['mempool_dpaa2', 'bus_fslmc', 'bus_vdev', 'pmd_dpaa2']
+sources = files('dpaa2_hw_dpcon.c',
+ 'dpaa2_eventdev.c')
+
+allow_experimental_apis = true
diff --git a/drivers/event/meson.build b/drivers/event/meson.build
index d7bc485..e951199 100644
--- a/drivers/event/meson.build
+++ b/drivers/event/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['skeleton', 'sw', 'octeontx']
+drivers = ['dpaa', 'dpaa2', 'octeontx', 'skeleton', 'sw']
std_deps = ['eventdev', 'kvargs']
config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD'
driver_name_fmt = 'rte_pmd_@0@_event'
diff --git a/drivers/mempool/dpaa/meson.build b/drivers/mempool/dpaa/meson.build
new file mode 100644
index 0000000..08423c2
--- /dev/null
+++ b/drivers/mempool/dpaa/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_dpaa']
+sources = files('dpaa_mempool.c')
diff --git a/drivers/mempool/dpaa2/meson.build b/drivers/mempool/dpaa2/meson.build
new file mode 100644
index 0000000..dee3a88
--- /dev/null
+++ b/drivers/mempool/dpaa2/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['mbuf', 'bus_fslmc']
+sources = files('dpaa2_hw_mempool.c')
diff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build
index 5991856..693a861 100644
--- a/drivers/mempool/meson.build
+++ b/drivers/mempool/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['ring', 'stack', 'octeontx']
+drivers = ['dpaa', 'dpaa2', 'octeontx', 'ring', 'stack']
std_deps = ['mempool']
config_flag_fmt = 'RTE_LIBRTE_@0@_MEMPOOL'
driver_name_fmt = 'rte_mempool_@0@'
diff --git a/drivers/net/dpaa/meson.build b/drivers/net/dpaa/meson.build
new file mode 100644
index 0000000..a4c40a6
--- /dev/null
+++ b/drivers/net/dpaa/meson.build
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['bus_dpaa', 'mempool_dpaa']
+
+sources = files('dpaa_ethdev.c',
+ 'dpaa_rxtx.c')
+
+allow_experimental_apis = true
+
+install_headers('rte_pmd_dpaa.h')
diff --git a/drivers/net/dpaa2/meson.build b/drivers/net/dpaa2/meson.build
new file mode 100644
index 0000000..ad1724d
--- /dev/null
+++ b/drivers/net/dpaa2/meson.build
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_fslmc', 'mempool_dpaa2']
+sources = files('base/dpaa2_hw_dpni.c',
+ 'dpaa2_ethdev.c',
+ 'dpaa2_rxtx.c',
+ 'mc/dpkg.c',
+ 'mc/dpni.c')
+
+includes += include_directories('base', 'mc')
diff --git a/drivers/net/meson.build b/drivers/net/meson.build
index 704cbe3..4ea6dcf 100644
--- a/drivers/net/meson.build
+++ b/drivers/net/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['af_packet', 'bonding',
+drivers = ['af_packet', 'bonding', 'dpaa', 'dpaa2',
'e1000', 'fm10k', 'i40e', 'ixgbe',
'null', 'octeontx', 'pcap', 'ring',
'sfc', 'thunderx']
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v2 10/10] build: add meson cross compile config for dpaaX
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (8 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 09/10] build: add meson support for dpaaX platforms Hemant Agrawal
@ 2018-03-01 7:33 ` Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
10 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-01 7:33 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
config/arm/arm64_dpaa2_linuxapp_gcc | 13 +++++++++++++
config/arm/arm64_dpaa_linuxapp_gcc | 14 ++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
diff --git a/config/arm/arm64_dpaa2_linuxapp_gcc b/config/arm/arm64_dpaa2_linuxapp_gcc
new file mode 100644
index 0000000..87337fb
--- /dev/null
+++ b/config/arm/arm64_dpaa2_linuxapp_gcc
@@ -0,0 +1,13 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = 'dpaa2'
diff --git a/config/arm/arm64_dpaa_linuxapp_gcc b/config/arm/arm64_dpaa_linuxapp_gcc
new file mode 100644
index 0000000..f769435
--- /dev/null
+++ b/config/arm/arm64_dpaa_linuxapp_gcc
@@ -0,0 +1,14 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = 'dpaa'
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH v2 02/10] bus/dpaa: fix the BE compilation issue
2018-03-01 7:33 ` [PATCH v2 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
@ 2018-03-01 12:22 ` Shreyansh Jain
0 siblings, 0 replies; 44+ messages in thread
From: Shreyansh Jain @ 2018-03-01 12:22 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, bruce.richardson, thomas, stable
On Thu, Mar 1, 2018 at 1:03 PM, Hemant Agrawal <hemant.agrawal@nxp.com> wrote:
>
> The array pointers were used without index.
>
> Fixes: b9083ea5e084 ("net/dpaa: further push mode optimizations")
> Cc: stable@dpdk.org
>
> Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
> drivers/bus/dpaa/base/qbman/qman.c | 5 +++--
> drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +----
> 2 files changed, 4 insertions(+), 6 deletions(-)
>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/7] build: add meson support for dpaaX platforms
2018-03-01 6:10 ` Hemant Agrawal
@ 2018-03-01 14:15 ` Thomas Monjalon
2018-03-09 16:49 ` Thomas Monjalon
0 siblings, 1 reply; 44+ messages in thread
From: Thomas Monjalon @ 2018-03-01 14:15 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: Bruce Richardson, dev, shreyansh.jain, Akhil Goyal
01/03/2018 07:10, Hemant Agrawal:
> On 2/28/2018 8:14 PM, Bruce Richardson wrote:
> > On Tue, Feb 27, 2018 at 10:55:52PM +0530, Hemant Agrawal wrote:
> >> +includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
> >
> > Is this not covered by the dependency on eal? Is it accessing things
> > directly in the EAL internals?
>
> We are accessing eal_vfio.h. so it is needed.
Let's try to fix it.
What is required exactly? Can it be in the exported header?
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/7] build: add meson support for dpaaX platforms
2018-03-01 14:15 ` Thomas Monjalon
@ 2018-03-09 16:49 ` Thomas Monjalon
2018-03-09 17:42 ` Hemant Agrawal
0 siblings, 1 reply; 44+ messages in thread
From: Thomas Monjalon @ 2018-03-09 16:49 UTC (permalink / raw)
To: Hemant Agrawal, shreyansh.jain, Akhil Goyal; +Cc: dev, Bruce Richardson
ping
01/03/2018 15:15, Thomas Monjalon:
> 01/03/2018 07:10, Hemant Agrawal:
> > On 2/28/2018 8:14 PM, Bruce Richardson wrote:
> > > On Tue, Feb 27, 2018 at 10:55:52PM +0530, Hemant Agrawal wrote:
> > >> +includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
> > >
> > > Is this not covered by the dependency on eal? Is it accessing things
> > > directly in the EAL internals?
> >
> > We are accessing eal_vfio.h. so it is needed.
>
> Let's try to fix it.
> What is required exactly? Can it be in the exported header?
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/10] config: add dpaaX build support in common linuxapp
2018-03-01 7:33 ` [PATCH v2 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
@ 2018-03-09 17:11 ` Thomas Monjalon
2018-03-09 17:22 ` Hemant Agrawal
0 siblings, 1 reply; 44+ messages in thread
From: Thomas Monjalon @ 2018-03-09 17:11 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, bruce.richardson
Hi,
As you know the config options should be declared in common_base
and overwritten in common_linuxapp.
That's why there is no need to add comments in common_linuxapp.
And some of the options should be only in common_base, like
CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
Please try to move all the options in common_base with their comments,
and only overwrite what is needed for Linux compilation.
Thanks
01/03/2018 08:33, Hemant Agrawal:
> --- a/config/common_linuxapp
> +++ b/config/common_linuxapp
> @@ -23,3 +23,40 @@ CONFIG_RTE_LIBRTE_NFP_PMD=y
> CONFIG_RTE_LIBRTE_POWER=y
> CONFIG_RTE_VIRTIO_USER=y
> CONFIG_RTE_PROC_INFO=y
> +#
> +# ARMv8 Specific driver compilation flags
> +#
> +
> +# Compile NXP DPAA Bus
> +CONFIG_RTE_LIBRTE_DPAA_BUS=y
> +CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
> +
> +# Compile NXP DPAA Mempool
> +CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y
> +
> +# Compile bust-oriented NXP DPAA PMD
> +CONFIG_RTE_LIBRTE_DPAA_PMD=y
> +
> +# Compile schedule-oriented NXP DPAA Event Dev PMD
> +CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y
> +
> +# Compile NXP DPAA caam - crypto driver
> +CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y
> +CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
> +CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
> +
> +# Compile NXP DPAA2 FSL-MC Bus
> +CONFIG_RTE_LIBRTE_FSLMC_BUS=y
> +
> +# Compile NXP DPAA2 Mempool
> +CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
> +
> +# Compile burst-oriented NXP DPAA2 PMD driver
> +CONFIG_RTE_LIBRTE_DPAA2_PMD=y
> +
> +# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
> +CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
> +
> +# Compile NXP DPAA2 crypto sec driver for CAAM HW
> +CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
> +CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v2 08/10] config: add dpaaX build support in common linuxapp
2018-03-09 17:11 ` Thomas Monjalon
@ 2018-03-09 17:22 ` Hemant Agrawal
0 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-09 17:22 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev, bruce.richardson
Hi Thomas,
>
> As you know the config options should be declared in common_base and
> overwritten in common_linuxapp.
>
> That's why there is no need to add comments in common_linuxapp.
> And some of the options should be only in common_base, like
> CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
>
> Please try to move all the options in common_base with their comments, and
> only overwrite what is needed for Linux compilation.
>
[Hemant] Thanks for the review. I will fix these in v3.
Regards,
Hemant
> Thanks
>
>
> 01/03/2018 08:33, Hemant Agrawal:
> > --- a/config/common_linuxapp
> > +++ b/config/common_linuxapp
> > @@ -23,3 +23,40 @@ CONFIG_RTE_LIBRTE_NFP_PMD=y
> > CONFIG_RTE_LIBRTE_POWER=y CONFIG_RTE_VIRTIO_USER=y
> > CONFIG_RTE_PROC_INFO=y
> > +#
> > +# ARMv8 Specific driver compilation flags #
> > +
> > +# Compile NXP DPAA Bus
> > +CONFIG_RTE_LIBRTE_DPAA_BUS=y
> > +CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
> > +
> > +# Compile NXP DPAA Mempool
> > +CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y
> > +
> > +# Compile bust-oriented NXP DPAA PMD
> > +CONFIG_RTE_LIBRTE_DPAA_PMD=y
> > +
> > +# Compile schedule-oriented NXP DPAA Event Dev PMD
> > +CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y
> > +
> > +# Compile NXP DPAA caam - crypto driver
> > +CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y
> > +CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
> > +CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
> > +
> > +# Compile NXP DPAA2 FSL-MC Bus
> > +CONFIG_RTE_LIBRTE_FSLMC_BUS=y
> > +
> > +# Compile NXP DPAA2 Mempool
> > +CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
> > +
> > +# Compile burst-oriented NXP DPAA2 PMD driver
> > +CONFIG_RTE_LIBRTE_DPAA2_PMD=y
> > +
> > +# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
> > +CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
> > +
> > +# Compile NXP DPAA2 crypto sec driver for CAAM HW
> > +CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
> > +CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
>
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/7] build: add meson support for dpaaX platforms
2018-03-09 16:49 ` Thomas Monjalon
@ 2018-03-09 17:42 ` Hemant Agrawal
0 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-09 17:42 UTC (permalink / raw)
To: Thomas Monjalon, Shreyansh Jain, Akhil Goyal; +Cc: dev, Bruce Richardson
Hi Thomas,
>
> ping
>
> 01/03/2018 15:15, Thomas Monjalon:
> > 01/03/2018 07:10, Hemant Agrawal:
> > > On 2/28/2018 8:14 PM, Bruce Richardson wrote:
> > > > On Tue, Feb 27, 2018 at 10:55:52PM +0530, Hemant Agrawal wrote:
> > > >> +includes +=
> > > >> +include_directories('../../../lib/librte_eal/linuxapp/eal')
> > > >
> > > > Is this not covered by the dependency on eal? Is it accessing
> > > > things directly in the EAL internals?
> > >
> > > We are accessing eal_vfio.h. so it is needed.
> >
> > Let's try to fix it.
> > What is required exactly? Can it be in the exported header?
>
>
Currently we are accessing few of the internal vfio functions such as vfio_get_container_fd or vfio_get_group_fd
Yes, they can be moved to rte_vfio.h
Regards,
Hemant
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 00/10] meson build support for dpaaX
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
` (9 preceding siblings ...)
2018-03-01 7:33 ` [PATCH v2 10/10] build: add meson cross compile config for dpaaX Hemant Agrawal
@ 2018-03-14 7:55 ` Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 01/10] event/dpaa: fix include header Hemant Agrawal
` (11 more replies)
10 siblings, 12 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:55 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Earlier dpaaX was only compiled for armv8 target. This patch series first prepares the dpaaX drivers to be compiled for non-ARM platform as well.
Note: This patch changes all of the dpaa drivers/modules - So it shall be applied to master tree instead of meson build tree.
v3:
- improved cross files and a function issue in dpaa2 bus.
v2:
- handle review comments from Bruce
- move the dpaaX compilation to linuxapp
Hemant Agrawal (10):
event/dpaa: fix include header
bus/dpaa: fix the BE compilation issue
dpaa: prepare for 32 bit compilation
dpaa2: prepare for 32 bit compilation
bus/fslmc: add 32 bit functional support for ARM
bus/dpaa: enabling dpaa compilation for other platforms
bus/fslmc: enabling dpaa2 compilation for other platforms
config: add dpaaX build support in common linuxapp
build: add meson support for dpaaX platforms
build: add meson cross compile config for dpaaX
app/test-pmd/meson.build | 3 +
config/arm/arm64_dpaa2_linuxapp_gcc | 15 +++++
config/arm/arm64_dpaa_linuxapp_gcc | 15 +++++
config/arm/meson.build | 13 ++++
config/common_armv8a_linuxapp | 58 ----------------
config/common_base | 4 ++
config/common_linuxapp | 14 ++++
config/rte_config.h | 12 +++-
drivers/bus/dpaa/base/fman/fman.c | 2 +-
drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +-
drivers/bus/dpaa/base/qbman/qman.c | 5 +-
drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +-
drivers/bus/dpaa/dpaa_bus.c | 3 +-
drivers/bus/dpaa/include/compat.h | 30 ++++++++-
drivers/bus/dpaa/meson.build | 29 ++++++++
drivers/bus/fslmc/fslmc_vfio.c | 10 +--
drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-
drivers/bus/fslmc/meson.build | 27 ++++++++
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 22 +++---
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++-----
drivers/bus/fslmc/qbman/qbman_portal.c | 14 ++--
drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++-
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 23 +++++++
drivers/bus/meson.build | 2 +-
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 101 ++++++++++++++--------------
drivers/crypto/dpaa2_sec/meson.build | 14 ++++
drivers/crypto/dpaa_sec/dpaa_sec.c | 30 ++++-----
drivers/crypto/dpaa_sec/meson.build | 13 ++++
drivers/crypto/meson.build | 4 +-
drivers/event/dpaa/dpaa_eventdev.c | 2 +-
drivers/event/dpaa/meson.build | 10 +++
drivers/event/dpaa2/dpaa2_eventdev.c | 10 +--
drivers/event/dpaa2/meson.build | 11 +++
drivers/event/meson.build | 2 +-
drivers/mempool/dpaa/dpaa_mempool.c | 10 +--
drivers/mempool/dpaa/dpaa_mempool.h | 2 +-
drivers/mempool/dpaa/meson.build | 9 +++
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 +--
drivers/mempool/dpaa2/meson.build | 9 +++
drivers/mempool/meson.build | 2 +-
drivers/net/dpaa/dpaa_rxtx.c | 19 +++---
drivers/net/dpaa/meson.build | 14 ++++
drivers/net/dpaa2/Makefile | 1 -
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +-
drivers/net/dpaa2/dpaa2_ethdev.c | 6 +-
drivers/net/dpaa2/dpaa2_rxtx.c | 63 +++++++++--------
drivers/net/dpaa2/meson.build | 15 +++++
drivers/net/meson.build | 2 +-
48 files changed, 487 insertions(+), 249 deletions(-)
create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
create mode 100644 drivers/bus/dpaa/meson.build
create mode 100644 drivers/bus/fslmc/meson.build
create mode 100644 drivers/crypto/dpaa2_sec/meson.build
create mode 100644 drivers/crypto/dpaa_sec/meson.build
create mode 100644 drivers/event/dpaa/meson.build
create mode 100644 drivers/event/dpaa2/meson.build
create mode 100644 drivers/mempool/dpaa/meson.build
create mode 100644 drivers/mempool/dpaa2/meson.build
create mode 100644 drivers/net/dpaa/meson.build
create mode 100644 drivers/net/dpaa2/meson.build
--
2.7.4
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 01/10] event/dpaa: fix include header
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
@ 2018-03-14 7:55 ` Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
` (10 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:55 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, stable
rte_cycles.h shall be included instead of rte_cycles_64.h
dpaa_eventdev.c:32:27:
fatal error: rte_cycles_64.h: No such file or directory
Fixes: 9caac5dd1e7f ("event/dpaa: introduce PMD")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/event/dpaa/dpaa_eventdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
index 0006801..cd13d0c 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -29,7 +29,7 @@
#include <rte_event_eth_rx_adapter.h>
#include <rte_dpaa_bus.h>
#include <rte_dpaa_logs.h>
-#include <rte_cycles_64.h>
+#include <rte_cycles.h>
#include <dpaa_ethdev.h>
#include "dpaa_eventdev.h"
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 02/10] bus/dpaa: fix the BE compilation issue
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 01/10] event/dpaa: fix include header Hemant Agrawal
@ 2018-03-14 7:55 ` Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 03/10] dpaa: prepare for 32 bit compilation Hemant Agrawal
` (9 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:55 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, stable
The array pointers were used without index.
Fixes: b9083ea5e084 ("net/dpaa: further push mode optimizations")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman.c | 5 +++--
drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 2b97671..2810fdd 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -1087,7 +1087,7 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
shadow[rx_number]->fd.opaque =
be32_to_cpu(dq[rx_number]->fd.opaque);
#else
- shadow = dq;
+ shadow[rx_number] = dq[rx_number];
#endif
/* SDQCR: context_b points to the FQ */
@@ -1095,7 +1095,8 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
fq[rx_number] = qman_fq_lookup_table[be32_to_cpu(
dq[rx_number]->contextB)];
#else
- fq[rx_number] = (void *)(uintptr_t)be32_to_cpu(dq->contextB);
+ fq[rx_number] = (void *)be32_to_cpu(
+ dq[rx_number]->contextB);
#endif
fq[rx_number]->cb.dqrr_prepare(shadow[rx_number],
&bufs[rx_number]);
diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c
index 7cfa8ee..66838d2 100644
--- a/drivers/bus/dpaa/base/qbman/qman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/qman_driver.c
@@ -246,7 +246,6 @@ int fsl_qman_portal_destroy(struct qman_portal *qp)
int qman_global_init(void)
{
const struct device_node *dt_node;
- int ret = 0;
size_t lenp;
const u32 *chanid;
static int ccsr_map_fd;
@@ -352,9 +351,7 @@ int qman_global_init(void)
qman_clk = be32_to_cpu(*clk);
#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
- ret = qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX);
- if (ret)
- return ret;
+ return qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX);
#endif
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 03/10] dpaa: prepare for 32 bit compilation
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 01/10] event/dpaa: fix include header Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
@ 2018-03-14 7:55 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 04/10] dpaa2: " Hemant Agrawal
` (8 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:55 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch prepares the dpaa drivers for compilation on 32 bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/base/fman/fman.c | 2 +-
drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +-
drivers/bus/dpaa/dpaa_bus.c | 3 +--
drivers/crypto/dpaa_sec/dpaa_sec.c | 30 +++++++++++++++---------------
drivers/mempool/dpaa/dpaa_mempool.c | 10 +++++-----
drivers/mempool/dpaa/dpaa_mempool.h | 2 +-
drivers/net/dpaa/dpaa_rxtx.c | 19 +++++++++----------
7 files changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c
index bda62e0..e6fd5f3 100644
--- a/drivers/bus/dpaa/base/fman/fman.c
+++ b/drivers/bus/dpaa/base/fman/fman.c
@@ -300,7 +300,7 @@ fman_if_init(const struct device_node *dpa_node)
_errno = fman_get_mac_index(regs_addr_host, &__if->__if.mac_idx);
if (_errno) {
- FMAN_ERR(-EINVAL, "Invalid register address: %lu",
+ FMAN_ERR(-EINVAL, "Invalid register address: %" PRIx64,
regs_addr_host);
goto err;
}
diff --git a/drivers/bus/dpaa/base/qbman/bman_driver.c b/drivers/bus/dpaa/base/qbman/bman_driver.c
index a1ef392..1381da3 100644
--- a/drivers/bus/dpaa/base/qbman/bman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/bman_driver.c
@@ -161,7 +161,7 @@ int bman_init_ccsr(const struct device_node *node)
PROT_WRITE, MAP_SHARED, ccsr_map_fd, phys_addr);
if (bman_ccsr_map == MAP_FAILED) {
pr_err("Can not map BMan CCSR base Bman: "
- "0x%x Phys: 0x%lx size 0x%lx",
+ "0x%x Phys: 0x%" PRIx64 " size 0x%" PRIu64,
*bman_addr, phys_addr, regs_size);
return -EINVAL;
}
diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index f2bb3b1..3535da5 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -19,7 +19,6 @@
#include <rte_interrupts.h>
#include <rte_log.h>
#include <rte_debug.h>
-#include <rte_pci.h>
#include <rte_atomic.h>
#include <rte_branch_prediction.h>
#include <rte_memory.h>
@@ -235,7 +234,7 @@ int rte_dpaa_portal_init(void *arg)
BUS_INIT_FUNC_TRACE();
- if ((uint64_t)arg == 1 || cpu == LCORE_ID_ANY)
+ if ((size_t)arg == 1 || cpu == LCORE_ID_ANY)
cpu = rte_get_master_lcore();
/* if the core id is not supported */
else
diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 18681cf..c5191ce 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -84,7 +84,7 @@ dpaa_sec_alloc_ctx(dpaa_sec_session *ses)
dcbz_64(&ctx->job.sg[SG_CACHELINE_3]);
ctx->ctx_pool = ses->ctx_pool;
- ctx->vtop_offset = (uint64_t) ctx
+ ctx->vtop_offset = (size_t) ctx
- rte_mempool_virt2iova(ctx);
return ctx;
@@ -97,7 +97,7 @@ dpaa_mem_vtop(void *vaddr)
uint64_t vaddr_64, paddr;
int i;
- vaddr_64 = (uint64_t)vaddr;
+ vaddr_64 = (size_t)vaddr;
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (vaddr_64 >= memseg[i].addr_64 &&
vaddr_64 < memseg[i].addr_64 + memseg[i].len) {
@@ -107,14 +107,14 @@ dpaa_mem_vtop(void *vaddr)
return (rte_iova_t)paddr;
}
}
- return (rte_iova_t)(NULL);
+ return (size_t)NULL;
}
/* virtual address conversin when mempool support is available for ctx */
static inline phys_addr_t
dpaa_mem_vtop_ctx(struct dpaa_sec_op_ctx *ctx, void *vaddr)
{
- return (uint64_t)vaddr - ctx->vtop_offset;
+ return (size_t)vaddr - ctx->vtop_offset;
}
static inline void *
@@ -125,8 +125,8 @@ dpaa_mem_ptov(rte_iova_t paddr)
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (paddr >= memseg[i].iova &&
- (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
- return (void *)(memseg[i].addr_64 +
+ paddr < memseg[i].iova + memseg[i].len)
+ return (void *)(size_t)(memseg[i].addr_64 +
(paddr - memseg[i].iova));
}
return NULL;
@@ -406,7 +406,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_c.key = (uint64_t)ses->cipher_key.data;
+ alginfo_c.key = (size_t)ses->cipher_key.data;
alginfo_c.keylen = ses->cipher_key.length;
alginfo_c.key_enc_flags = 0;
alginfo_c.key_type = RTA_DATA_IMM;
@@ -424,7 +424,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_a.key = (uint64_t)ses->auth_key.data;
+ alginfo_a.key = (size_t)ses->auth_key.data;
alginfo_a.keylen = ses->auth_key.length;
alginfo_a.key_enc_flags = 0;
alginfo_a.key_type = RTA_DATA_IMM;
@@ -439,7 +439,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
PMD_TX_LOG(ERR, "not supported aead alg\n");
return -ENOTSUP;
}
- alginfo.key = (uint64_t)ses->aead_key.data;
+ alginfo.key = (size_t)ses->aead_key.data;
alginfo.keylen = ses->aead_key.length;
alginfo.key_enc_flags = 0;
alginfo.key_type = RTA_DATA_IMM;
@@ -463,7 +463,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_c.key = (uint64_t)ses->cipher_key.data;
+ alginfo_c.key = (size_t)ses->cipher_key.data;
alginfo_c.keylen = ses->cipher_key.length;
alginfo_c.key_enc_flags = 0;
alginfo_c.key_type = RTA_DATA_IMM;
@@ -474,7 +474,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
return -ENOTSUP;
}
- alginfo_a.key = (uint64_t)ses->auth_key.data;
+ alginfo_a.key = (size_t)ses->auth_key.data;
alginfo_a.keylen = ses->auth_key.length;
alginfo_a.key_enc_flags = 0;
alginfo_a.key_type = RTA_DATA_IMM;
@@ -493,15 +493,15 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses)
if (cdb->sh_desc[2] & 1)
alginfo_c.key_type = RTA_DATA_IMM;
else {
- alginfo_c.key = (uint64_t)dpaa_mem_vtop(
- (void *)alginfo_c.key);
+ alginfo_c.key = (size_t)dpaa_mem_vtop(
+ (void *)(size_t)alginfo_c.key);
alginfo_c.key_type = RTA_DATA_PTR;
}
if (cdb->sh_desc[2] & (1<<1))
alginfo_a.key_type = RTA_DATA_IMM;
else {
- alginfo_a.key = (uint64_t)dpaa_mem_vtop(
- (void *)alginfo_a.key);
+ alginfo_a.key = (size_t)dpaa_mem_vtop(
+ (void *)(size_t)alginfo_a.key);
alginfo_a.key_type = RTA_DATA_PTR;
}
cdb->sh_desc[0] = 0;
diff --git a/drivers/mempool/dpaa/dpaa_mempool.c b/drivers/mempool/dpaa/dpaa_mempool.c
index fb3b6ba..7b82f4b 100644
--- a/drivers/mempool/dpaa/dpaa_mempool.c
+++ b/drivers/mempool/dpaa/dpaa_mempool.c
@@ -115,7 +115,8 @@ dpaa_buf_free(struct dpaa_bp_info *bp_info, uint64_t addr)
struct bm_buffer buf;
int ret;
- DPAA_MEMPOOL_DEBUG("Free 0x%lx to bpid: %d", addr, bp_info->bpid);
+ DPAA_MEMPOOL_DEBUG("Free 0x%" PRIx64 " to bpid: %d",
+ addr, bp_info->bpid);
bm_buffer_set64(&buf, addr);
retry:
@@ -154,8 +155,7 @@ dpaa_mbuf_free_bulk(struct rte_mempool *pool,
if (unlikely(!bp_info->ptov_off)) {
/* buffers are from single mem segment */
if (bp_info->flags & DPAA_MPOOL_SINGLE_SEGMENT) {
- bp_info->ptov_off
- = (uint64_t)obj_table[i] - phy;
+ bp_info->ptov_off = (size_t)obj_table[i] - phy;
rte_dpaa_bpid_info[bp_info->bpid].ptov_off
= bp_info->ptov_off;
}
@@ -282,8 +282,8 @@ dpaa_register_memory_area(const struct rte_mempool *mp,
bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;
- DPAA_MEMPOOL_DEBUG("Req size %lu vs Available %u\n",
- len, total_elt_sz * mp->size);
+ DPAA_MEMPOOL_DEBUG("Req size %" PRIx64 " vs Available %u\n",
+ (uint64_t)len, total_elt_sz * mp->size);
/* Detect pool area has sufficient space for elements in this memzone */
if (len >= total_elt_sz * mp->size)
diff --git a/drivers/mempool/dpaa/dpaa_mempool.h b/drivers/mempool/dpaa/dpaa_mempool.h
index 9435dd2..092f326 100644
--- a/drivers/mempool/dpaa/dpaa_mempool.h
+++ b/drivers/mempool/dpaa/dpaa_mempool.h
@@ -46,7 +46,7 @@ static inline void *
DPAA_MEMPOOL_PTOV(struct dpaa_bp_info *bp_info, uint64_t addr)
{
if (bp_info->ptov_off)
- return ((void *)(addr + bp_info->ptov_off));
+ return ((void *) (size_t)(addr + bp_info->ptov_off));
return rte_dpaa_mem_ptov(addr);
}
diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 0dea8e7..bdb7f66 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -59,7 +59,7 @@
} while (0)
#if (defined RTE_LIBRTE_DPAA_DEBUG_DRIVER)
-void dpaa_display_frame(const struct qm_fd *fd)
+static void dpaa_display_frame(const struct qm_fd *fd)
{
int ii;
char *ptr;
@@ -90,11 +90,10 @@ static inline void dpaa_slow_parsing(struct rte_mbuf *m __rte_unused,
/*TBD:XXX: to be implemented*/
}
-static inline void dpaa_eth_packet_info(struct rte_mbuf *m,
- uint64_t fd_virt_addr)
+static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
{
struct annotations_t *annot = GET_ANNOTATIONS(fd_virt_addr);
- uint64_t prs = *((uint64_t *)(&annot->parse)) & DPAA_PARSE_MASK;
+ uint64_t prs = *((uintptr_t *)(&annot->parse)) & DPAA_PARSE_MASK;
DPAA_DP_LOG(DEBUG, " Parsing mbuf: %p with annotations: %p", m, annot);
@@ -351,7 +350,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
prev_seg = cur_seg;
}
- dpaa_eth_packet_info(first_seg, (uint64_t)vaddr);
+ dpaa_eth_packet_info(first_seg, vaddr);
rte_pktmbuf_free_seg(temp);
return first_seg;
@@ -394,7 +393,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
mbuf->ol_flags = 0;
mbuf->next = NULL;
rte_mbuf_refcnt_set(mbuf, 1);
- dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
return mbuf;
}
@@ -455,7 +454,7 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
mbuf->ol_flags = 0;
mbuf->next = NULL;
rte_mbuf_refcnt_set(mbuf, 1);
- dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
}
}
@@ -593,7 +592,7 @@ uint16_t dpaa_eth_queue_rx(void *q,
static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info)
{
int ret;
- uint64_t buf = 0;
+ size_t buf = 0;
struct bm_buffer bufs;
ret = bman_acquire(bp_info->bp, &bufs, 1, 0);
@@ -602,10 +601,10 @@ static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info)
return (void *)buf;
}
- DPAA_DP_LOG(DEBUG, "got buffer 0x%lx from pool %d",
+ DPAA_DP_LOG(DEBUG, "got buffer 0x%" PRIx64 " from pool %d",
(uint64_t)bufs.addr, bufs.bpid);
- buf = (uint64_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr)
+ buf = (size_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr)
- bp_info->meta_data_size;
if (!buf)
goto out;
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 04/10] dpaa2: prepare for 32 bit compilation
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (2 preceding siblings ...)
2018-03-14 7:55 ` [PATCH v3 03/10] dpaa: prepare for 32 bit compilation Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 05/10] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
` (7 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch prepare the dpaa2 drivers for compilation on 32 bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/fslmc_vfio.c | 10 +--
drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 22 +++---
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++-----
drivers/bus/fslmc/qbman/qbman_portal.c | 14 ++--
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 101 ++++++++++++++--------------
drivers/event/dpaa2/dpaa2_eventdev.c | 10 +--
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 +--
drivers/net/dpaa2/Makefile | 1 -
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +-
drivers/net/dpaa2/dpaa2_ethdev.c | 6 +-
drivers/net/dpaa2/dpaa2_rxtx.c | 63 +++++++++--------
12 files changed, 137 insertions(+), 139 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 1241295..e840ad6 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -76,7 +76,7 @@ fslmc_get_container_group(int *groupid)
if (!g_container) {
container = getenv("DPRC");
if (container == NULL) {
- RTE_LOG(WARNING, EAL, "DPAA2: DPRC not available\n");
+ RTE_LOG(DEBUG, EAL, "DPAA2: DPRC not available\n");
return -EINVAL;
}
@@ -270,7 +270,7 @@ int rte_fslmc_vfio_dmamap(void)
static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
{
- int64_t v_addr = (int64_t)MAP_FAILED;
+ intptr_t v_addr = (intptr_t)MAP_FAILED;
int32_t ret, mc_fd;
struct vfio_device_info d_info = { .argsz = sizeof(d_info) };
@@ -301,7 +301,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj)
FSLMC_VFIO_LOG(DEBUG, "region offset = %llx , region size = %llx",
reg_info.offset, reg_info.size);
- v_addr = (uint64_t)mmap(NULL, reg_info.size,
+ v_addr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
mc_fd, reg_info.offset);
@@ -469,7 +469,7 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev)
static int
fslmc_process_mcp(struct rte_dpaa2_device *dev)
{
- int64_t v_addr;
+ intptr_t v_addr;
char *dev_name;
struct fsl_mc_io dpmng = {0};
struct mc_version mc_ver_info = {0};
@@ -489,7 +489,7 @@ fslmc_process_mcp(struct rte_dpaa2_device *dev)
}
v_addr = vfio_map_mcp_obj(&vfio_group, dev_name);
- if (v_addr == (int64_t)MAP_FAILED) {
+ if (v_addr == (intptr_t)MAP_FAILED) {
FSLMC_VFIO_LOG(ERR, "Error mapping region (errno = %d)",
errno);
free(rte_mcp_ptr_list);
diff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h
index a3c3e79..ac91961 100644
--- a/drivers/bus/fslmc/mc/fsl_mc_cmd.h
+++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h
@@ -27,7 +27,7 @@
#define le32_to_cpu rte_le_to_cpu_32
#define le16_to_cpu rte_le_to_cpu_16
-#define BITS_PER_LONG 64
+#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
#define GENMASK(h, l) \
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index eefde15..7b671ef 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -291,7 +291,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
if (!dpio_dev)
return NULL;
- PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
+ PMD_DRV_LOG(DEBUG, "New Portal %p (%d) affined thread - %lu",
dpio_dev, dpio_dev->index, syscall(SYS_gettid));
ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
@@ -314,8 +314,9 @@ dpaa2_affine_qbman_swp(void)
return -1;
if (dpaa2_io_portal[lcore_id].dpio_dev) {
- PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
- " between thread %lu and current %lu",
+ PMD_DRV_LOG(INFO, "DPAAPortal=%p (%d) is being shared"
+ " between thread %" PRIu64 " and current "
+ "%" PRIu64 "\n",
dpaa2_io_portal[lcore_id].dpio_dev,
dpaa2_io_portal[lcore_id].dpio_dev->index,
dpaa2_io_portal[lcore_id].net_tid,
@@ -326,7 +327,8 @@ dpaa2_affine_qbman_swp(void)
[lcore_id].dpio_dev->ref_count);
dpaa2_io_portal[lcore_id].net_tid = tid;
- PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
+ PMD_DRV_LOG(DEBUG, "Old Portal=%p (%d)"
+ "affined thread - %" PRIu64 "\n",
dpaa2_io_portal[lcore_id].dpio_dev,
dpaa2_io_portal[lcore_id].dpio_dev->index,
tid);
@@ -360,8 +362,9 @@ dpaa2_affine_qbman_swp_sec(void)
return -1;
if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
- PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
- " between thread %lu and current %lu",
+ PMD_DRV_LOG(INFO, "DPAAPortal=%p (%d) is being shared"
+ " between thread %" PRIu64 " and current "
+ "%" PRIu64 "\n",
dpaa2_io_portal[lcore_id].sec_dpio_dev,
dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
dpaa2_io_portal[lcore_id].sec_tid,
@@ -372,7 +375,8 @@ dpaa2_affine_qbman_swp_sec(void)
[lcore_id].sec_dpio_dev->ref_count);
dpaa2_io_portal[lcore_id].sec_tid = tid;
- PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
+ PMD_DRV_LOG(DEBUG, "Old Portal=%p (%d) "
+ "affined thread - %" PRIu64 "\n",
dpaa2_io_portal[lcore_id].sec_dpio_dev,
dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
tid);
@@ -427,7 +431,7 @@ dpaa2_create_dpio_device(int vdev_fd,
}
dpio_dev->ce_size = reg_info.size;
- dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
+ dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
vdev_fd, reg_info.offset);
@@ -439,7 +443,7 @@ dpaa2_create_dpio_device(int vdev_fd,
}
dpio_dev->ci_size = reg_info.size;
- dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
+ dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
vdev_fd, reg_info.offset);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index d421dbf..4a19d42 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -174,7 +174,7 @@ enum qbman_fd_format {
};
/*Macros to define operations on FD*/
#define DPAA2_SET_FD_ADDR(fd, addr) do { \
- (fd)->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
+ (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
(fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
} while (0)
#define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
@@ -193,33 +193,32 @@ enum qbman_fd_format {
#define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
#define DPAA2_SET_FD_FLC(fd, addr) do { \
- (fd)->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
+ (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
(fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
} while (0)
#define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
#define DPAA2_GET_FLE_ADDR(fle) \
(uint64_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
#define DPAA2_SET_FLE_ADDR(fle, addr) do { \
- (fle)->addr_lo = lower_32_bits((uint64_t)addr); \
- (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
+ (fle)->addr_lo = lower_32_bits((size_t)addr); \
+ (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
} while (0)
#define DPAA2_GET_FLE_CTXT(fle) \
- (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \
- (fle)->reserved[0])
+ ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
#define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
- (fle)->reserved[0] = lower_32_bits((uint64_t)addr); \
- (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
+ (fle)->reserved[0] = lower_32_bits((size_t)addr); \
+ (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
} while (0)
#define DPAA2_SET_FLE_OFFSET(fle, offset) \
((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
-#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
+#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
#define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
-#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 31)
+#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
#define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
#define DPAA2_SET_FD_COMPOUND_FMT(fd) \
((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
#define DPAA2_GET_FD_ADDR(fd) \
-((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
+(((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
#define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
#define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
@@ -231,7 +230,7 @@ enum qbman_fd_format {
(((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
#define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
- ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
+ ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
#define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
@@ -265,14 +264,14 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr)
int i;
if (dpaa2_virt_mode)
- return (void *)paddr;
+ return (void *)(size_t)paddr;
memseg = rte_eal_get_physmem_layout();
for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
if (paddr >= memseg[i].iova &&
- (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
- return (void *)(memseg[i].addr_64
+ paddr < memseg[i].iova + memseg[i].len)
+ return (void *)(size_t)(memseg[i].addr_64
+ (paddr - memseg[i].iova));
}
return NULL;
@@ -295,7 +294,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
return memseg[i].iova
+ (vaddr - memseg[i].addr_64);
}
- return (phys_addr_t)(NULL);
+ return (size_t)(NULL);
}
/**
@@ -311,18 +310,18 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
/**
* macro to convert Virtual address to IOVA
*/
-#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
+#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
/**
* macro to convert IOVA to Virtual address
*/
-#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
+#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
/**
* macro to convert modify the memory containing IOVA to Virtual address
*/
#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
- {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
+ {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
#else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c
index e221733..713ec96 100644
--- a/drivers/bus/fslmc/qbman/qbman_portal.c
+++ b/drivers/bus/fslmc/qbman/qbman_portal.c
@@ -553,10 +553,9 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s,
/* Flush all the cacheline without load/store in between */
eqcr_pi = s->eqcr.pi;
- addr_cena = (uint64_t)s->sys.addr_cena;
+ addr_cena = (size_t)s->sys.addr_cena;
for (i = 0; i < num_enqueued; i++) {
- dcbf((uint64_t *)(addr_cena +
- QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
eqcr_pi++;
eqcr_pi &= 0xF;
}
@@ -620,10 +619,9 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
/* Flush all the cacheline without load/store in between */
eqcr_pi = s->eqcr.pi;
- addr_cena = (uint64_t)s->sys.addr_cena;
+ addr_cena = (size_t)s->sys.addr_cena;
for (i = 0; i < num_enqueued; i++) {
- dcbf((uint64_t *)(addr_cena +
- QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
+ dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
eqcr_pi++;
eqcr_pi &= 0xF;
}
@@ -690,7 +688,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
dma_addr_t storage_phys,
int stash)
{
- d->pull.rsp_addr_virt = (uint64_t)storage;
+ d->pull.rsp_addr_virt = (size_t)storage;
if (!storage) {
d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
@@ -749,7 +747,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
}
d->pull.tok = s->sys.idx + 1;
- s->vdq.storage = (void *)d->pull.rsp_addr_virt;
+ s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt;
p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
memcpy(&p[1], &cl[1], 12);
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 9a790dd..9a74845 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -77,11 +77,11 @@ build_proto_fd(dpaa2_sec_session *sess,
DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
DPAA2_SET_FD_OFFSET(fd, sym_op->m_src->data_off);
DPAA2_SET_FD_LEN(fd, sym_op->m_src->pkt_len);
- DPAA2_SET_FD_FLC(fd, ((uint64_t)flc));
+ DPAA2_SET_FD_FLC(fd, (ptrdiff_t)flc);
/* save physical address of mbuf */
op->sym->aead.digest.phys_addr = mbuf->buf_iova;
- mbuf->buf_iova = (uint64_t)op;
+ mbuf->buf_iova = (size_t)op;
return 0;
}
@@ -118,7 +118,7 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_SG_MEM_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -269,7 +269,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_POOL_BUF_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
if (likely(bpid < MAX_BPID)) {
@@ -414,7 +414,7 @@ build_authenc_sg_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_SG_MEM_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -563,7 +563,7 @@ build_authenc_fd(dpaa2_sec_session *sess,
}
memset(fle, 0, FLE_POOL_BUF_SIZE);
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
if (likely(bpid < MAX_BPID)) {
@@ -692,7 +692,7 @@ static inline int build_auth_sg_fd(
memset(fle, 0, FLE_SG_MEM_SIZE);
/* first FLE entry used to store mbuf and session ctxt */
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
sge = fle + 3;
@@ -773,7 +773,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
* We can have a better approach to use the inline Mbuf
*/
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
if (likely(bpid < MAX_BPID)) {
@@ -865,7 +865,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
memset(fle, 0, FLE_SG_MEM_SIZE);
/* first FLE entry used to store mbuf and session ctxt */
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
op_fle = fle + 1;
ip_fle = fle + 2;
@@ -944,13 +944,13 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
DPAA2_SET_FD_COMPOUND_FMT(fd);
DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
- PMD_TX_LOG(DEBUG,
- "CIPHER SG: fdaddr =%p bpid =%d meta =%d off =%d, len =%d",
- (void *)DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[bpid].meta_data_size,
- DPAA2_GET_FD_OFFSET(fd),
- DPAA2_GET_FD_LEN(fd));
+ PMD_TX_LOG(DEBUG, "CIPHER SG: fdaddr =%" PRIx64
+ " bpid =%d meta =%d off =%d, len =%d\n",
+ DPAA2_GET_FD_ADDR(fd),
+ DPAA2_GET_FD_BPID(fd),
+ rte_dpaa2_bpid_info[bpid].meta_data_size,
+ DPAA2_GET_FD_OFFSET(fd),
+ DPAA2_GET_FD_LEN(fd));
return 0;
}
@@ -987,7 +987,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
* We can have a better approach to use the inline Mbuf
*/
DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
- DPAA2_FLE_SAVE_CTXT(fle, priv);
+ DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);
fle = fle + 1;
sge = fle + 2;
@@ -1206,7 +1206,7 @@ sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id)
DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
- op = (struct rte_crypto_op *)mbuf->buf_iova;
+ op = (struct rte_crypto_op *)(size_t)mbuf->buf_iova;
mbuf->buf_iova = op->sym->aead.digest.phys_addr;
op->sym->aead.digest.phys_addr = 0L;
@@ -1267,16 +1267,17 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id)
PMD_RX_LOG(DEBUG, "mbuf %p BMAN buf addr %p",
(void *)dst, dst->buf_addr);
- PMD_RX_LOG(DEBUG, "fdaddr =%p bpid =%d meta =%d off =%d, len =%d",
- (void *)DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
- DPAA2_GET_FD_OFFSET(fd),
- DPAA2_GET_FD_LEN(fd));
+ PMD_RX_LOG(DEBUG, "fdaddr =%" PRIx64
+ " bpid =%d meta =%d off =%d, len =%d",
+ DPAA2_GET_FD_ADDR(fd),
+ DPAA2_GET_FD_BPID(fd),
+ rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
+ DPAA2_GET_FD_OFFSET(fd),
+ DPAA2_GET_FD_LEN(fd));
/* free the fle memory */
if (likely(rte_pktmbuf_is_contiguous(src))) {
- priv = (struct ctxt_priv *)DPAA2_GET_FLE_CTXT(fle - 1);
+ priv = (struct ctxt_priv *)(size_t)DPAA2_GET_FLE_CTXT(fle - 1);
rte_mempool_put(priv->fle_pool, (void *)(fle-1));
} else
rte_free((void *)(fle-1));
@@ -1455,7 +1456,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
dev->data->queue_pairs[qp_id] = qp;
cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;
- cfg.user_ctx = (uint64_t)(&qp->rx_vq);
+ cfg.user_ctx = (size_t)(&qp->rx_vq);
retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,
qp_id, &cfg);
return retcode;
@@ -1536,7 +1537,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
memcpy(session->cipher_key.data, xform->cipher.key.data,
xform->cipher.key.length);
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -1595,10 +1596,10 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
@@ -1651,7 +1652,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, xform->auth.key.data,
xform->auth.key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -1720,10 +1721,10 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -1786,7 +1787,7 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev,
session->aead_key.length = aead_xform->key.length;
ctxt->auth_only_len = aead_xform->aad_length;
- aeaddata.key = (uint64_t)session->aead_key.data;
+ aeaddata.key = (size_t)session->aead_key.data;
aeaddata.keylen = session->aead_key.length;
aeaddata.key_enc_flags = 0;
aeaddata.key_type = RTA_DATA_IMM;
@@ -1840,10 +1841,10 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev,
session->digest_length);
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -1928,7 +1929,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, auth_xform->key.data,
auth_xform->key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -1988,7 +1989,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
auth_xform->algo);
goto error_out;
}
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -2066,10 +2067,10 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev,
flc->word1_sdl = (uint8_t)bufsize;
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
session->ctxt = priv;
for (i = 0; i < bufsize; i++)
@@ -2202,7 +2203,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
memcpy(session->auth_key.data, auth_xform->key.data,
auth_xform->key.length);
- authdata.key = (uint64_t)session->auth_key.data;
+ authdata.key = (size_t)session->auth_key.data;
authdata.keylen = session->auth_key.length;
authdata.key_enc_flags = 0;
authdata.key_type = RTA_DATA_IMM;
@@ -2261,7 +2262,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
auth_xform->algo);
goto out;
}
- cipherdata.key = (uint64_t)session->cipher_key.data;
+ cipherdata.key = (size_t)session->cipher_key.data;
cipherdata.keylen = session->cipher_key.length;
cipherdata.key_enc_flags = 0;
cipherdata.key_type = RTA_DATA_IMM;
@@ -2345,10 +2346,10 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
/* Enable the stashing control bit */
DPAA2_SET_FLC_RSC(flc);
flc->word2_rflc_31_0 = lower_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq) | 0x14);
flc->word3_rflc_63_32 = upper_32_bits(
- (uint64_t)&(((struct dpaa2_sec_qp *)
+ (size_t)&(((struct dpaa2_sec_qp *)
dev->data->queue_pairs[0])->rx_vq));
/* Set EWS bit i.e. enable write-safe */
@@ -2647,13 +2648,13 @@ void dpaa2_sec_stats_get(struct rte_cryptodev *dev,
PMD_DRV_LOG(ERR, "dpseci_get_sec_counters failed\n");
} else {
PMD_DRV_LOG(INFO, "dpseci hw stats:"
- "\n\tNumber of Requests Dequeued = %lu"
- "\n\tNumber of Outbound Encrypt Requests = %lu"
- "\n\tNumber of Inbound Decrypt Requests = %lu"
- "\n\tNumber of Outbound Bytes Encrypted = %lu"
- "\n\tNumber of Outbound Bytes Protected = %lu"
- "\n\tNumber of Inbound Bytes Decrypted = %lu"
- "\n\tNumber of Inbound Bytes Validated = %lu",
+ "\n\tNumber of Requests Dequeued = %" PRIu64
+ "\n\tNumber of Outbound Encrypt Requests = %" PRIu64
+ "\n\tNumber of Inbound Decrypt Requests = %" PRIu64
+ "\n\tNumber of Outbound Bytes Encrypted = %" PRIu64
+ "\n\tNumber of Outbound Bytes Protected = %" PRIu64
+ "\n\tNumber of Inbound Bytes Decrypted = %" PRIu64
+ "\n\tNumber of Inbound Bytes Validated = %" PRIu64,
counters.dequeued_requests,
counters.ob_enc_requests,
counters.ib_dec_requests,
diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c
index c3e6fbf..8800b47 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -126,7 +126,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
goto send_partial;
}
rte_memcpy(ev_temp, event, sizeof(struct rte_event));
- DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
+ DPAA2_SET_FD_ADDR((&fd_arr[loop]), (size_t)ev_temp);
DPAA2_SET_FD_LEN((&fd_arr[loop]),
sizeof(struct rte_event));
}
@@ -182,7 +182,7 @@ static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
struct rte_event *ev)
{
struct rte_event *ev_temp =
- (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
+ (struct rte_event *)(size_t)DPAA2_GET_FD_ADDR(fd);
RTE_SET_USED(rxq);
@@ -199,7 +199,7 @@ static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
struct rte_event *ev)
{
struct rte_event *ev_temp =
- (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
+ (struct rte_event *)(size_t)DPAA2_GET_FD_ADDR(fd);
uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
RTE_SET_USED(swp);
@@ -258,7 +258,7 @@ dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
qbman_swp_prefetch_dqrr_next(swp);
fd = qbman_result_DQ_fd(dq);
- rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
+ rxq = (struct dpaa2_queue *)(size_t)qbman_result_DQ_fqd_ctx(dq);
if (rxq) {
rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]);
} else {
@@ -736,7 +736,7 @@ dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
dpaa2_eventdev_process_atomic;
for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
- rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
+ rx_queue_cfg.user_ctx = (size_t)(&dpci_dev->queue[i]);
ret = dpci_set_rx_queue(&dpci_dev->dpci,
CMD_PRI_LOW,
dpci_dev->token, i,
diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
index 2bd62e8..1a618ae 100644
--- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
+++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
@@ -242,7 +242,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
#endif
struct qbman_swp *swp;
uint16_t bpid;
- uint64_t bufs[DPAA2_MBUF_MAX_ACQ_REL];
+ size_t bufs[DPAA2_MBUF_MAX_ACQ_REL];
int i, ret;
unsigned int n = 0;
struct dpaa2_bp_info *bp_info;
@@ -270,10 +270,10 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
* then the remainder.
*/
if ((count - n) > DPAA2_MBUF_MAX_ACQ_REL) {
- ret = qbman_swp_acquire(swp, bpid, bufs,
+ ret = qbman_swp_acquire(swp, bpid, (void *)bufs,
DPAA2_MBUF_MAX_ACQ_REL);
} else {
- ret = qbman_swp_acquire(swp, bpid, bufs,
+ ret = qbman_swp_acquire(swp, bpid, (void *)bufs,
count - n);
}
/* In case of less than requested number of buffers available
@@ -290,7 +290,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
}
/* assigning mbuf from the acquired objects */
for (i = 0; (i < ret) && bufs[i]; i++) {
- DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], uint64_t);
+ DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], size_t);
obj_table[n] = (struct rte_mbuf *)
(bufs[i] - bp_info->meta_data_size);
PMD_TX_LOG(DEBUG, "Acquired %p address %p from BMAN",
diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile
index 5a93a0b..068e9d3 100644
--- a/drivers/net/dpaa2/Makefile
+++ b/drivers/net/dpaa2/Makefile
@@ -25,7 +25,6 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include
CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc
CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal
CFLAGS += -I$(RTE_SDK)/drivers/mempool/dpaa2
-CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2
CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
# versioning export map
diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
index b93376d..4b60f56 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
@@ -50,7 +50,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg);
if (ret) {
- PMD_INIT_LOG(ERR, "given rss_hf (%lx) not supported",
+ PMD_INIT_LOG(ERR, "given rss_hf (%" PRIx64 ") not supported",
req_dist_set);
rte_free(p_params);
return ret;
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 09a11d6..fd5897e 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -445,7 +445,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
memset(&cfg, 0, sizeof(struct dpni_queue));
options = options | DPNI_QUEUE_OPT_USER_CTX;
- cfg.user_context = (uint64_t)(dpaa2_q);
+ cfg.user_context = (size_t)(dpaa2_q);
/*if ls2088 or rev2 device, enable the stashing */
@@ -560,7 +560,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
*/
cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
cong_notif_cfg.message_ctx = 0;
- cong_notif_cfg.message_iova = (uint64_t)dpaa2_q->cscn;
+ cong_notif_cfg.message_iova = (size_t)dpaa2_q->cscn;
cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
cong_notif_cfg.notification_mode =
DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
@@ -1702,7 +1702,7 @@ int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
}
options |= DPNI_QUEUE_OPT_USER_CTX;
- cfg.user_context = (uint64_t)(dpaa2_ethq);
+ cfg.user_context = (size_t)(dpaa2_ethq);
ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
dpaa2_ethq->tc_index, flow_id, options, &cfg);
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 183293c..21a08b6 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -21,7 +21,6 @@
#include <dpaa2_hw_pvt.h>
#include <dpaa2_hw_dpio.h>
#include <dpaa2_hw_mempool.h>
-#include <dpaa2_eventdev.h>
#include "dpaa2_ethdev.h"
#include "base/dpaa2_hw_dpni_annot.h"
@@ -104,13 +103,11 @@ dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc)
}
static inline uint32_t __attribute__((hot))
-dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
+dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation)
{
uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
- struct dpaa2_annot_hdr *annotation =
- (struct dpaa2_annot_hdr *)hw_annot_addr;
- PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4);
+ PMD_RX_LOG(DEBUG, "annotation = 0x%" PRIx64, annotation->word4);
if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
pkt_type = RTE_PTYPE_L2_ETHER_ARP;
goto parse_done;
@@ -167,12 +164,12 @@ dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
}
static inline uint32_t __attribute__((hot))
-dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
+dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
{
struct dpaa2_annot_hdr *annotation =
(struct dpaa2_annot_hdr *)hw_annot_addr;
- PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4);
+ PMD_RX_LOG(DEBUG, "annotation = 0x%" PRIx64, annotation->word4);
/* Check offloads first */
if (BIT_ISSET_AT_POS(annotation->word3,
@@ -207,25 +204,24 @@ dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
break;
}
- return dpaa2_dev_rx_parse_slow(hw_annot_addr);
+ return dpaa2_dev_rx_parse_slow(annotation);
}
static inline struct rte_mbuf *__attribute__((hot))
eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
{
struct qbman_sge *sgt, *sge;
- dma_addr_t sg_addr;
+ size_t sg_addr, fd_addr;
int i = 0;
- uint64_t fd_addr;
struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
- fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
+ fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
/* Get Scatter gather table address */
sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
sge = &sgt[i++];
- sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
+ sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
/* First Scatter gather entry */
first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
@@ -243,14 +239,14 @@ eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
DPAA2_GET_FD_FRC_PARSE_SUM(fd));
else
first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
- + DPAA2_FD_PTA_SIZE);
+ (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ + DPAA2_FD_PTA_SIZE));
rte_mbuf_refcnt_set(first_seg, 1);
cur_seg = first_seg;
while (!DPAA2_SG_IS_FINAL(sge)) {
sge = &sgt[i++];
- sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(
+ sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
DPAA2_GET_FLE_ADDR(sge));
next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
@@ -299,12 +295,12 @@ eth_fd_to_mbuf(const struct qbman_fd *fd)
dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd));
else
mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
- + DPAA2_FD_PTA_SIZE);
+ (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ + DPAA2_FD_PTA_SIZE));
PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
- "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n",
- mbuf, mbuf->buf_addr, mbuf->data_off,
+ "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n",
+ (void *)mbuf, (void *)mbuf->buf_addr, mbuf->data_off,
DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
@@ -340,7 +336,7 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
/*Set Scatter gather table and Scatter gather entries*/
sgt = (struct qbman_sge *)(
- (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
+ DPAA2_GET_FD_OFFSET(fd));
for (i = 0; i < mbuf->nb_segs; i++) {
@@ -402,8 +398,8 @@ eth_mbuf_to_fd(struct rte_mbuf *mbuf,
DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d,"
- "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n",
- mbuf, mbuf->buf_addr, mbuf->data_off,
+ "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n",
+ (void *)mbuf, mbuf->buf_addr, mbuf->data_off,
DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
@@ -458,11 +454,12 @@ eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p",
(void *)mbuf, mbuf->buf_addr);
- PMD_TX_LOG(DEBUG, " fdaddr =%lx bpid =%d meta =%d off =%d, len =%d",
- DPAA2_GET_FD_ADDR(fd),
- DPAA2_GET_FD_BPID(fd),
- rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
+ PMD_TX_LOG(DEBUG,
+ "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n",
DPAA2_GET_FD_OFFSET(fd),
+ DPAA2_GET_FD_ADDR(fd),
+ rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
+ DPAA2_GET_FD_BPID(fd),
DPAA2_GET_FD_LEN(fd));
return 0;
@@ -523,8 +520,8 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
}
dq_storage = q_storage->active_dqs;
- rte_prefetch0((void *)((uint64_t)(dq_storage)));
- rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
+ rte_prefetch0((void *)(size_t)(dq_storage));
+ rte_prefetch0((void *)(size_t)(dq_storage + 1));
/* Prepare next pull descriptor. This will give space for the
* prefething done on DQRR entries
@@ -554,7 +551,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
*/
while (!qbman_check_new_result(dq_storage))
;
- rte_prefetch0((void *)((uint64_t)(dq_storage + 2)));
+ rte_prefetch0((void *)((size_t)(dq_storage + 2)));
/* Check whether Last Pull command is Expired and
* setting Condition for Loop termination
*/
@@ -569,7 +566,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
next_fd = qbman_result_DQ_fd(dq_storage + 1);
/* Prefetch Annotation address for the parse results */
- rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(next_fd)
+ rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd)
+ DPAA2_FD_PTA_SIZE + 16));
if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
@@ -616,7 +613,7 @@ dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
struct dpaa2_queue *rxq,
struct rte_event *ev)
{
- rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(fd) +
+ rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
DPAA2_FD_PTA_SIZE + 16));
ev->flow_id = rxq->ev.flow_id;
@@ -641,7 +638,7 @@ dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)),
{
uint8_t dqrr_index;
- rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(fd) +
+ rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
DPAA2_FD_PTA_SIZE + 16));
ev->flow_id = rxq->ev.flow_id;
@@ -726,7 +723,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
fd_arr[loop].simple.frc = 0;
DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
- DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
+ DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL);
if (likely(RTE_MBUF_DIRECT(*bufs))) {
mp = (*bufs)->pool;
/* Check the basic scenario and set
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 05/10] bus/fslmc: add 32 bit functional support for ARM
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (3 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 04/10] dpaa2: " Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 06/10] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
` (6 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
This patch adds the functional logic to make the dpaa2 drivers
work on 32bit machine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++++++++++++++++++++++--
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 9 +++++++++
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h
index 846788e..2bd33ea 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys.h
@@ -20,6 +20,9 @@
#include "qbman_sys_decl.h"
+#define CENA_WRITE_ENABLE 0
+#define CINH_WRITE_ENABLE 1
+
/* Debugging assists */
static inline void __hexdump(unsigned long start, unsigned long end,
unsigned long p, size_t sz, const unsigned char *c)
@@ -178,7 +181,11 @@ static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
s->addr_cena, s->idx, offset);
#endif
QBMAN_BUG_ON(offset & 63);
+#ifdef RTE_ARCH_64
return (s->addr_cena + offset);
+#else
+ return (s->addr_cinh + offset);
+#endif
}
static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
@@ -191,11 +198,19 @@ static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
s->addr_cena, s->idx, offset, shadow);
hexdump(cmd, 64);
#endif
+#ifdef RTE_ARCH_64
for (loop = 15; loop >= 1; loop--)
__raw_writel(shadow[loop], s->addr_cena +
offset + loop * 4);
lwsync();
__raw_writel(shadow[0], s->addr_cena + offset);
+#else
+ for (loop = 15; loop >= 1; loop--)
+ __raw_writel(shadow[loop], s->addr_cinh +
+ offset + loop * 4);
+ lwsync();
+ __raw_writel(shadow[0], s->addr_cinh + offset);
+#endif
dcbf(s->addr_cena + offset);
}
@@ -224,9 +239,15 @@ static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
s->addr_cena, s->idx, offset, shadow);
#endif
+#ifdef RTE_ARCH_64
for (loop = 0; loop < 16; loop++)
shadow[loop] = __raw_readl(s->addr_cena + offset
+ loop * 4);
+#else
+ for (loop = 0; loop < 16; loop++)
+ shadow[loop] = __raw_readl(s->addr_cinh + offset
+ + loop * 4);
+#endif
#ifdef QBMAN_CENA_TRACE
hexdump(shadow, 64);
#endif
@@ -313,6 +334,11 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
uint8_t dqrr_size)
{
uint32_t reg;
+#ifdef RTE_ARCH_64
+ uint8_t wn = CENA_WRITE_ENABLE;
+#else
+ uint8_t wn = CINH_WRITE_ENABLE;
+#endif
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
@@ -333,10 +359,10 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
QBMAN_BUG_ON(reg);
#endif
if (s->eqcr_mode == qman_eqcr_vb_array)
- reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1,
+ reg = qbman_set_swp_cfg(dqrr_size, wn, 0, 3, 2, 3, 1, 1, 1, 1,
1, 1);
else
- reg = qbman_set_swp_cfg(dqrr_size, 0, 1, 3, 2, 2, 1, 1, 1, 1,
+ reg = qbman_set_swp_cfg(dqrr_size, wn, 1, 3, 2, 2, 1, 1, 1, 1,
1, 1);
qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
index f82bb18..5640b04 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
@@ -15,6 +15,7 @@
/****************/
/* arch assists */
/****************/
+#if defined(RTE_ARCH_ARM64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define lwsync() { asm volatile("dmb st" : : : "memory"); }
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
@@ -28,3 +29,11 @@ static inline void prefetch_for_store(void *p)
{
asm volatile("prfm pstl1keep, [%0, #0]" : : "r" (p));
}
+#elif defined(RTE_ARCH_ARM)
+#define dcbz(p) memset(p, 0, 64)
+#define lwsync() { asm volatile("dmb st" : : : "memory"); }
+#define dcbf(p) RTE_SET_USED(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 06/10] bus/dpaa: enabling dpaa compilation for other platforms
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (4 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 05/10] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 07/10] bus/fslmc: enabling dpaa2 " Hemant Agrawal
` (5 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/dpaa/include/compat.h | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/dpaa/include/compat.h b/drivers/bus/dpaa/include/compat.h
index 53707bb..e4b5702 100644
--- a/drivers/bus/dpaa/include/compat.h
+++ b/drivers/bus/dpaa/include/compat.h
@@ -39,6 +39,7 @@
#include <rte_spinlock.h>
#include <rte_common.h>
#include <rte_debug.h>
+#include <rte_cycles.h>
/* The following definitions are primarily to allow the single-source driver
* interfaces to be included by arbitrary program code. Ie. for interfaces that
@@ -127,13 +128,15 @@ static inline void out_be32(volatile void *__p, u32 val)
*p = rte_cpu_to_be_32(val);
}
+#define hwsync() rte_rmb()
+#define lwsync() rte_wmb()
+
#define dcbt_ro(p) __builtin_prefetch(p, 0)
#define dcbt_rw(p) __builtin_prefetch(p, 1)
+#if defined(RTE_ARCH_ARM64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define dcbz_64(p) dcbz(p)
-#define hwsync() rte_rmb()
-#define lwsync() rte_wmb()
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
#define dcbf_64(p) dcbf(p)
#define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); }
@@ -144,9 +147,27 @@ static inline void out_be32(volatile void *__p, u32 val)
asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); \
} while (0)
+#elif defined(RTE_ARCH_ARM)
+#define dcbz(p) memset((p), 0, 32)
+#define dcbz_64(p) memset((p), 0, 64)
+#define dcbf(p) RTE_SET_USED(p)
+#define dcbf_64(p) dcbf(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define dcbit_ro(p) RTE_SET_USED(p)
+
+#else
+#define dcbz(p) RTE_SET_USED(p)
+#define dcbz_64(p) dcbz(p)
+#define dcbf(p) RTE_SET_USED(p)
+#define dcbf_64(p) dcbf(p)
+#define dccivac(p) RTE_SET_USED(p)
+#define dcbit_ro(p) RTE_SET_USED(p)
+#endif
+
#define barrier() { asm volatile ("" : : : "memory"); }
#define cpu_relax barrier
+#if defined(RTE_ARCH_ARM64)
static inline uint64_t mfatb(void)
{
uint64_t ret, ret_new, timeout = 200;
@@ -160,6 +181,11 @@ static inline uint64_t mfatb(void)
DPAA_BUG_ON(!timeout && (ret != ret_new));
return ret * 64;
}
+#else
+
+#define mfatb rte_rdtsc
+
+#endif
/* Spin for a few cycles without bothering the bus */
static inline void cpu_spin(int cycles)
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 07/10] bus/fslmc: enabling dpaa2 compilation for other platforms
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (5 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 06/10] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
` (4 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/bus/fslmc/qbman/qbman_sys_decl.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
index 5640b04..fa6977f 100644
--- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h
+++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h
@@ -36,4 +36,18 @@ static inline void prefetch_for_store(void *p)
#define dccivac(p) RTE_SET_USED(p)
#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
+
+#else
+#define dcbz(p) RTE_SET_USED(p)
+#define lwsync()
+#define dcbf(p) RTE_SET_USED(p)
+#define dccivac(p) RTE_SET_USED(p)
+static inline void prefetch_for_load(void *p)
+{
+ RTE_SET_USED(p);
+}
+static inline void prefetch_for_store(void *p)
+{
+ RTE_SET_USED(p);
+}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 08/10] config: add dpaaX build support in common linuxapp
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (6 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 07/10] bus/fslmc: enabling dpaa2 " Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 09/10] build: add meson support for dpaaX platforms Hemant Agrawal
` (3 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
config/common_armv8a_linuxapp | 58 -------------------------------------------
config/common_base | 4 +++
config/common_linuxapp | 14 +++++++++++
3 files changed, 18 insertions(+), 58 deletions(-)
diff --git a/config/common_armv8a_linuxapp b/config/common_armv8a_linuxapp
index 507b28a..111c005 100644
--- a/config/common_armv8a_linuxapp
+++ b/config/common_armv8a_linuxapp
@@ -36,61 +36,3 @@ CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
CONFIG_RTE_LIBRTE_AVP_PMD=n
CONFIG_RTE_SCHED_VECTOR=n
-
-#
-# ARMv8 Specific driver compilation flags
-#
-
-#
-# Compile NXP DPAA Bus
-#
-CONFIG_RTE_LIBRTE_DPAA_BUS=y
-CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
-
-#
-# Compile NXP DPAA2 FSL-MC Bus
-#
-CONFIG_RTE_LIBRTE_FSLMC_BUS=y
-
-#
-# Compile NXP DPAA Mempool
-#
-CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y
-
-#
-# Compile NXP DPAA2 Mempool
-#
-CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
-
-#
-# Compile bust-oriented NXP DPAA PMD
-#
-CONFIG_RTE_LIBRTE_DPAA_PMD=y
-
-#
-# Compile burst-oriented NXP DPAA2 PMD driver
-#
-CONFIG_RTE_LIBRTE_DPAA2_PMD=y
-
-#
-# Compile schedule-oriented NXP DPAA Event Dev PMD
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y
-
-#
-# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
-
-#
-# Compile NXP DPAA caam - crypto driver
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y
-CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
-CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
-
-#
-# Compile NXP DPAA2 crypto sec driver for CAAM HW
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
-CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
diff --git a/config/common_base b/config/common_base
index ad03cf4..ee10b44 100644
--- a/config/common_base
+++ b/config/common_base
@@ -172,6 +172,7 @@ CONFIG_RTE_LIBRTE_CXGBE_TPUT=y
CONFIG_RTE_LIBRTE_DPAA_BUS=n
CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=n
CONFIG_RTE_LIBRTE_DPAA_PMD=n
+CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
#
# Compile NXP DPAA2 FSL-MC Bus
@@ -458,6 +459,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=n
CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n
CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n
CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n
+CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
#
# NXP DPAA caam - crypto driver
@@ -466,6 +468,8 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n
CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_INIT=n
CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_DRIVER=n
CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_RX=n
+CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
+CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
# Compile PMD for QuickAssist based devices
diff --git a/config/common_linuxapp b/config/common_linuxapp
index ff98f23..d0437e5 100644
--- a/config/common_linuxapp
+++ b/config/common_linuxapp
@@ -23,3 +23,17 @@ CONFIG_RTE_LIBRTE_NFP_PMD=y
CONFIG_RTE_LIBRTE_POWER=y
CONFIG_RTE_VIRTIO_USER=y
CONFIG_RTE_PROC_INFO=y
+
+# NXP DPAA BUS and drivers
+CONFIG_RTE_LIBRTE_DPAA_BUS=y
+CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=y
+CONFIG_RTE_LIBRTE_DPAA_PMD=y
+CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=y
+CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=y
+
+# NXP FSLMC BUS and DPAA2 drivers
+CONFIG_RTE_LIBRTE_FSLMC_BUS=y
+CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
+CONFIG_RTE_LIBRTE_DPAA2_PMD=y
+CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
+CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 09/10] build: add meson support for dpaaX platforms
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (7 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 10/10] build: add meson cross compile config for dpaaX Hemant Agrawal
` (2 subsequent siblings)
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas, Akhil Goyal
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
app/test-pmd/meson.build | 3 +++
config/arm/meson.build | 13 +++++++++++++
config/rte_config.h | 12 +++++++++++-
drivers/bus/dpaa/meson.build | 29 +++++++++++++++++++++++++++++
drivers/bus/fslmc/meson.build | 27 +++++++++++++++++++++++++++
drivers/bus/meson.build | 2 +-
drivers/crypto/dpaa2_sec/meson.build | 14 ++++++++++++++
drivers/crypto/dpaa_sec/meson.build | 13 +++++++++++++
drivers/crypto/meson.build | 4 +++-
drivers/event/dpaa/meson.build | 10 ++++++++++
drivers/event/dpaa2/meson.build | 11 +++++++++++
drivers/event/meson.build | 2 +-
drivers/mempool/dpaa/meson.build | 9 +++++++++
drivers/mempool/dpaa2/meson.build | 9 +++++++++
drivers/mempool/meson.build | 2 +-
drivers/net/dpaa/meson.build | 14 ++++++++++++++
drivers/net/dpaa2/meson.build | 15 +++++++++++++++
drivers/net/meson.build | 2 +-
18 files changed, 185 insertions(+), 6 deletions(-)
create mode 100644 drivers/bus/dpaa/meson.build
create mode 100644 drivers/bus/fslmc/meson.build
create mode 100644 drivers/crypto/dpaa2_sec/meson.build
create mode 100644 drivers/crypto/dpaa_sec/meson.build
create mode 100644 drivers/event/dpaa/meson.build
create mode 100644 drivers/event/dpaa2/meson.build
create mode 100644 drivers/mempool/dpaa/meson.build
create mode 100644 drivers/mempool/dpaa2/meson.build
create mode 100644 drivers/net/dpaa/meson.build
create mode 100644 drivers/net/dpaa2/meson.build
diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build
index 7ed74db..83f8bb1 100644
--- a/app/test-pmd/meson.build
+++ b/app/test-pmd/meson.build
@@ -32,6 +32,9 @@ if dpdk_conf.has('RTE_LIBRTE_SOFTNIC_PMD')
sources += files('tm.c')
deps += 'pmd_softnic'
endif
+if dpdk_conf.has('RTE_LIBRTE_DPAA_PMD')
+ deps += ['bus_dpaa', 'mempool_dpaa', 'pmd_dpaa']
+endif
dep_objs = []
foreach d:deps
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 4e788a4..c1ab6ed 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,17 @@ flags_cavium = [
['RTE_MAX_LCORE', 96],
['RTE_MAX_VFIO_GROUPS', 128],
['RTE_RING_USE_C11_MEM_MODEL', false]]
+flags_dpaa = [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16]]
+flags_dpaa2 = [
+ ['RTE_MACHINE', '"dpaa2"'],
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', 'n']]
## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -69,6 +80,8 @@ impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
impl_0x69 = ['Intel', flags_generic, machine_args_generic]
+impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
+impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
if cc.get_define('__clang__') != ''
diff --git a/config/rte_config.h b/config/rte_config.h
index 699878a..72c0aa2 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -74,10 +74,20 @@
/*
* Number of sessions to create in the session memory pool
- * on a single QuickAssist device.
+ * on a single instance of crypto HW device.
*/
+/* QuickAssist device */
#define RTE_QAT_PMD_MAX_NB_SESSIONS 2048
+/* DPAA2_SEC */
+#define RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS 2048
+
+/* DPAA_SEC */
+#define RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS 2048
+
+/* DPAA SEC max cryptodev devices*/
+#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
+
/* fm10k defines */
#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
diff --git a/drivers/bus/dpaa/meson.build b/drivers/bus/dpaa/meson.build
new file mode 100644
index 0000000..f5c6d7b
--- /dev/null
+++ b/drivers/bus/dpaa/meson.build
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['ethdev', 'eventdev']
+sources = files('base/fman/fman.c',
+ 'base/fman/fman_hw.c',
+ 'base/fman/netcfg_layer.c',
+ 'base/fman/of.c',
+ 'base/qbman/bman.c',
+ 'base/qbman/bman_driver.c',
+ 'base/qbman/dpaa_alloc.c',
+ 'base/qbman/dpaa_sys.c',
+ 'base/qbman/process.c',
+ 'base/qbman/qman.c',
+ 'base/qbman/qman_driver.c',
+ 'dpaa_bus.c')
+
+allow_experimental_apis = true
+
+if cc.has_argument('-Wno-cast-qual')
+ cflags += '-Wno-cast-qual'
+endif
+
+includes += include_directories('include', 'base/qbman')
+cflags += ['-D_GNU_SOURCE']
diff --git a/drivers/bus/fslmc/meson.build b/drivers/bus/fslmc/meson.build
new file mode 100644
index 0000000..e94340e
--- /dev/null
+++ b/drivers/bus/fslmc/meson.build
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['ethdev', 'eventdev', 'kvargs']
+sources = files('fslmc_bus.c',
+ 'fslmc_vfio.c',
+ 'mc/dpbp.c',
+ 'mc/dpci.c',
+ 'mc/dpcon.c',
+ 'mc/dpio.c',
+ 'mc/dpmng.c',
+ 'mc/mc_sys.c',
+ 'portal/dpaa2_hw_dpbp.c',
+ 'portal/dpaa2_hw_dpci.c',
+ 'portal/dpaa2_hw_dpio.c',
+ 'qbman/qbman_portal.c',
+ 'qbman/qbman_debug.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('../../../lib/librte_eal/linuxapp/eal')
+includes += include_directories('mc', 'qbman/include', 'portal')
+cflags += ['-D_GNU_SOURCE']
diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build
index c6af500..58dfbe2 100644
--- a/drivers/bus/meson.build
+++ b/drivers/bus/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['pci', 'vdev']
+drivers = ['dpaa', 'fslmc', 'pci', 'vdev']
std_deps = ['eal']
config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
driver_name_fmt = 'rte_bus_@0@'
diff --git a/drivers/crypto/dpaa2_sec/meson.build b/drivers/crypto/dpaa2_sec/meson.build
new file mode 100644
index 0000000..0fb4d96
--- /dev/null
+++ b/drivers/crypto/dpaa2_sec/meson.build
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_fslmc', 'security', 'mempool_dpaa2']
+sources = files('dpaa2_sec_dpseci.c',
+ 'mc/dpseci.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('mc', 'hw')
diff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build
new file mode 100644
index 0000000..8a57098
--- /dev/null
+++ b/drivers/crypto/dpaa_sec/meson.build
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_dpaa', 'security']
+sources = files('dpaa_sec.c')
+
+allow_experimental_apis = true
+
+includes += include_directories('../dpaa2_sec/')
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 17041ad..736c9f5 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -1,7 +1,9 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['qat', 'null', 'openssl']
+drivers = ['dpaa_sec', 'dpaa2_sec',
+ 'openssl', 'null', 'qat']
+
std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
driver_name_fmt = 'rte_pmd_@0@'
diff --git a/drivers/event/dpaa/meson.build b/drivers/event/dpaa/meson.build
new file mode 100644
index 0000000..9bbd6c2
--- /dev/null
+++ b/drivers/event/dpaa/meson.build
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['mempool_dpaa', 'bus_dpaa', 'pmd_dpaa']
+sources = files('dpaa_eventdev.c')
+
+allow_experimental_apis = true
diff --git a/drivers/event/dpaa2/meson.build b/drivers/event/dpaa2/meson.build
new file mode 100644
index 0000000..835460c
--- /dev/null
+++ b/drivers/event/dpaa2/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['mempool_dpaa2', 'bus_fslmc', 'bus_vdev', 'pmd_dpaa2']
+sources = files('dpaa2_hw_dpcon.c',
+ 'dpaa2_eventdev.c')
+
+allow_experimental_apis = true
diff --git a/drivers/event/meson.build b/drivers/event/meson.build
index d7bc485..e951199 100644
--- a/drivers/event/meson.build
+++ b/drivers/event/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['skeleton', 'sw', 'octeontx']
+drivers = ['dpaa', 'dpaa2', 'octeontx', 'skeleton', 'sw']
std_deps = ['eventdev', 'kvargs']
config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD'
driver_name_fmt = 'rte_pmd_@0@_event'
diff --git a/drivers/mempool/dpaa/meson.build b/drivers/mempool/dpaa/meson.build
new file mode 100644
index 0000000..08423c2
--- /dev/null
+++ b/drivers/mempool/dpaa/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_dpaa']
+sources = files('dpaa_mempool.c')
diff --git a/drivers/mempool/dpaa2/meson.build b/drivers/mempool/dpaa2/meson.build
new file mode 100644
index 0000000..dee3a88
--- /dev/null
+++ b/drivers/mempool/dpaa2/meson.build
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['mbuf', 'bus_fslmc']
+sources = files('dpaa2_hw_mempool.c')
diff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build
index 5991856..693a861 100644
--- a/drivers/mempool/meson.build
+++ b/drivers/mempool/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['ring', 'stack', 'octeontx']
+drivers = ['dpaa', 'dpaa2', 'octeontx', 'ring', 'stack']
std_deps = ['mempool']
config_flag_fmt = 'RTE_LIBRTE_@0@_MEMPOOL'
driver_name_fmt = 'rte_mempool_@0@'
diff --git a/drivers/net/dpaa/meson.build b/drivers/net/dpaa/meson.build
new file mode 100644
index 0000000..a4c40a6
--- /dev/null
+++ b/drivers/net/dpaa/meson.build
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['bus_dpaa', 'mempool_dpaa']
+
+sources = files('dpaa_ethdev.c',
+ 'dpaa_rxtx.c')
+
+allow_experimental_apis = true
+
+install_headers('rte_pmd_dpaa.h')
diff --git a/drivers/net/dpaa2/meson.build b/drivers/net/dpaa2/meson.build
new file mode 100644
index 0000000..ad1724d
--- /dev/null
+++ b/drivers/net/dpaa2/meson.build
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2018 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_fslmc', 'mempool_dpaa2']
+sources = files('base/dpaa2_hw_dpni.c',
+ 'dpaa2_ethdev.c',
+ 'dpaa2_rxtx.c',
+ 'mc/dpkg.c',
+ 'mc/dpni.c')
+
+includes += include_directories('base', 'mc')
diff --git a/drivers/net/meson.build b/drivers/net/meson.build
index 704cbe3..4ea6dcf 100644
--- a/drivers/net/meson.build
+++ b/drivers/net/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['af_packet', 'bonding',
+drivers = ['af_packet', 'bonding', 'dpaa', 'dpaa2',
'e1000', 'fm10k', 'i40e', 'ixgbe',
'null', 'octeontx', 'pcap', 'ring',
'sfc', 'thunderx']
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v3 10/10] build: add meson cross compile config for dpaaX
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (8 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 09/10] build: add meson support for dpaaX platforms Hemant Agrawal
@ 2018-03-14 7:56 ` Hemant Agrawal
2018-03-14 9:08 ` [PATCH v3 00/10] meson build support " Bruce Richardson
2018-03-15 17:10 ` Bruce Richardson
11 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 7:56 UTC (permalink / raw)
To: dev, bruce.richardson; +Cc: thomas
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
config/arm/arm64_dpaa2_linuxapp_gcc | 15 +++++++++++++++
config/arm/arm64_dpaa_linuxapp_gcc | 15 +++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc
create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc
diff --git a/config/arm/arm64_dpaa2_linuxapp_gcc b/config/arm/arm64_dpaa2_linuxapp_gcc
new file mode 100644
index 0000000..7ec74ec
--- /dev/null
+++ b/config/arm/arm64_dpaa2_linuxapp_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-ar'
+as = 'aarch64-linux-gnu-as'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = 'dpaa2'
diff --git a/config/arm/arm64_dpaa_linuxapp_gcc b/config/arm/arm64_dpaa_linuxapp_gcc
new file mode 100644
index 0000000..73a8f0b
--- /dev/null
+++ b/config/arm/arm64_dpaa_linuxapp_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-ar'
+as = 'aarch64-linux-gnu-as'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = 'dpaa'
--
2.7.4
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH v3 00/10] meson build support for dpaaX
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (9 preceding siblings ...)
2018-03-14 7:56 ` [PATCH v3 10/10] build: add meson cross compile config for dpaaX Hemant Agrawal
@ 2018-03-14 9:08 ` Bruce Richardson
2018-03-14 9:12 ` Hemant Agrawal
2018-03-15 17:10 ` Bruce Richardson
11 siblings, 1 reply; 44+ messages in thread
From: Bruce Richardson @ 2018-03-14 9:08 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, thomas
On Wed, Mar 14, 2018 at 01:25:56PM +0530, Hemant Agrawal wrote:
> Earlier dpaaX was only compiled for armv8 target. This patch series first prepares the dpaaX drivers to be compiled for non-ARM platform as well.
>
>
> Note: This patch changes all of the dpaa drivers/modules - So it shall be applied to master tree instead of meson build tree.
>
>From discussion with Thomas, the proposal was for me to take this entire
set into the build tree. However, if it's likely to cause conflicts with
future patches from you, I can send a pull-request shortly after merge
to get it into main tree too. Would that work for you? Thomas, you ok to
take an early PR for next-build?
/Bruce
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v3 00/10] meson build support for dpaaX
2018-03-14 9:08 ` [PATCH v3 00/10] meson build support " Bruce Richardson
@ 2018-03-14 9:12 ` Hemant Agrawal
0 siblings, 0 replies; 44+ messages in thread
From: Hemant Agrawal @ 2018-03-14 9:12 UTC (permalink / raw)
To: Bruce Richardson; +Cc: dev, thomas, Shreyansh Jain
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bruce Richardson
> Sent: Wednesday, March 14, 2018 2:39 PM
> On Wed, Mar 14, 2018 at 01:25:56PM +0530, Hemant Agrawal wrote:
> > Earlier dpaaX was only compiled for armv8 target. This patch series first
> prepares the dpaaX drivers to be compiled for non-ARM platform as well.
> >
> >
> > Note: This patch changes all of the dpaa drivers/modules - So it shall be
> applied to master tree instead of meson build tree.
> >
>
> From discussion with Thomas, the proposal was for me to take this entire set
> into the build tree. However, if it's likely to cause conflicts with future patches
> from you, I can send a pull-request shortly after merge to get it into main tree
> too. Would that work for you? Thomas, you ok to take an early PR for next-
> build?
[Hemant] yes, an early pull request will help.
Shreyansh's dynamic logging is already dependent on this patchset.
>
> /Bruce
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v3 00/10] meson build support for dpaaX
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
` (10 preceding siblings ...)
2018-03-14 9:08 ` [PATCH v3 00/10] meson build support " Bruce Richardson
@ 2018-03-15 17:10 ` Bruce Richardson
11 siblings, 0 replies; 44+ messages in thread
From: Bruce Richardson @ 2018-03-15 17:10 UTC (permalink / raw)
To: Hemant Agrawal; +Cc: dev, thomas
On Wed, Mar 14, 2018 at 01:25:56PM +0530, Hemant Agrawal wrote:
> Earlier dpaaX was only compiled for armv8 target. This patch series first prepares the dpaaX drivers to be compiled for non-ARM platform as well.
>
>
> Note: This patch changes all of the dpaa drivers/modules - So it shall be applied to master tree instead of meson build tree.
>
> v3:
> - improved cross files and a function issue in dpaa2 bus.
>
> v2:
> - handle review comments from Bruce
> - move the dpaaX compilation to linuxapp
>
> Hemant Agrawal (10):
> event/dpaa: fix include header
> bus/dpaa: fix the BE compilation issue
> dpaa: prepare for 32 bit compilation
> dpaa2: prepare for 32 bit compilation
> bus/fslmc: add 32 bit functional support for ARM
> bus/dpaa: enabling dpaa compilation for other platforms
> bus/fslmc: enabling dpaa2 compilation for other platforms
> config: add dpaaX build support in common linuxapp
> build: add meson support for dpaaX platforms
> build: add meson cross compile config for dpaaX
>
Patches applied to dpdk-next-build.
Pull-request to master to follow shortly.
/Bruce
^ permalink raw reply [flat|nested] 44+ messages in thread
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2018-02-27 17:25 [PATCH 0/7] meson build support for dpaaX Hemant Agrawal
2018-02-27 17:25 ` [PATCH 1/7] event/dpaa: fix include header Hemant Agrawal
2018-02-27 17:25 ` [PATCH 2/7] dpaa: prepare for 32 bit compilation Hemant Agrawal
2018-02-27 17:25 ` [PATCH 3/7] dpaa2: " Hemant Agrawal
2018-02-27 17:25 ` [PATCH 4/7] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
2018-02-27 17:25 ` [PATCH 5/7] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
2018-02-27 17:25 ` [PATCH 6/7] bus/fslmc: enabling dpaa2 " Hemant Agrawal
2018-02-28 14:45 ` Bruce Richardson
2018-02-28 16:02 ` Hemant Agrawal
2018-02-28 16:33 ` Richardson, Bruce
2018-02-27 17:25 ` [PATCH 7/7] build: add meson support for dpaaX platforms Hemant Agrawal
2018-02-28 14:44 ` Bruce Richardson
2018-03-01 6:10 ` Hemant Agrawal
2018-03-01 14:15 ` Thomas Monjalon
2018-03-09 16:49 ` Thomas Monjalon
2018-03-09 17:42 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 00/10] meson build support for dpaaX Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 01/10] event/dpaa: fix include header Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
2018-03-01 12:22 ` Shreyansh Jain
2018-03-01 7:33 ` [PATCH v2 03/10] dpaa: prepare for 32 bit compilation Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 04/10] dpaa2: " Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 05/10] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 06/10] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 07/10] bus/fslmc: enabling dpaa2 " Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
2018-03-09 17:11 ` Thomas Monjalon
2018-03-09 17:22 ` Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 09/10] build: add meson support for dpaaX platforms Hemant Agrawal
2018-03-01 7:33 ` [PATCH v2 10/10] build: add meson cross compile config for dpaaX Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 00/10] meson build support " Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 01/10] event/dpaa: fix include header Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 02/10] bus/dpaa: fix the BE compilation issue Hemant Agrawal
2018-03-14 7:55 ` [PATCH v3 03/10] dpaa: prepare for 32 bit compilation Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 04/10] dpaa2: " Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 05/10] bus/fslmc: add 32 bit functional support for ARM Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 06/10] bus/dpaa: enabling dpaa compilation for other platforms Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 07/10] bus/fslmc: enabling dpaa2 " Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 08/10] config: add dpaaX build support in common linuxapp Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 09/10] build: add meson support for dpaaX platforms Hemant Agrawal
2018-03-14 7:56 ` [PATCH v3 10/10] build: add meson cross compile config for dpaaX Hemant Agrawal
2018-03-14 9:08 ` [PATCH v3 00/10] meson build support " Bruce Richardson
2018-03-14 9:12 ` Hemant Agrawal
2018-03-15 17:10 ` Bruce Richardson
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