Re: [Qemu-devel] [PULL 00/42] target-arm queue - no-reply

From: no-reply@patchew.org
To: peter.maydell@linaro.org
Cc: famz@redhat.com, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PULL 00/42] target-arm queue
Date: Thu, 1 Mar 2018 05:00:46 -0800 (PST)	[thread overview]
Message-ID: <151990924540.1290.18181910407458585370@bdbb90650ae5> (raw)
In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org>

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180301112403.12487-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/42] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   5116c331c6..2963d78204  master     -> master
 * [new tag]               patchew/20180301112403.12487-1-peter.maydell@linaro.org -> patchew/20180301112403.12487-1-peter.maydell@linaro.org
Switched to a new branch 'test'
b8d820da8e MAINTAINERS: Update my email address
fafefeede8 linux-user: Report AArch64 FP16 support via hwcap bits
1e47f0c8d0 target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
a1d78601d3 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
ef1aeecd4b arm/translate-a64: implement simd_scalar_three_reg_same_fp16
6f2836d485 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
a35291f349 arm/translate-a64: add FP16 FMOV to simd_mod_imm
0a27cbb4ed arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
0a441b7da4 arm/helper.c: re-factor rsqrte and add rsqrte_f16
da2e0fc44a arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
4cef2369d2 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
1b4f1ab980 arm/translate-a64: add FP16 FRECPE
73a9e97036 arm/helper.c: re-factor recpe and add recepe_f16
90ba4bd8c2 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
73fd85ed2b arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
f19cc5a183 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
65f396e589 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
0e24214ab5 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
f196ce6fe6 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
34d06595e7 arm/translate-a64: add FP16 x2 ops for simd_indexed
1cbb0530d6 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
2784d82ed6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
d384cdd281 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
8f8a6ce448 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
126916bc89 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
4173362d9a arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
933cd48012 arm/translate-a64: initial decode for simd_three_reg_same_fp16
b990db46a4 arm/translate-a64: handle_3same_64 comment fix
d35bfc6ddd arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
f7b5043d8e target/arm/helper: pass explicit fpst to set_rmode
f4942cc7c8 target/arm/cpu.h: add additional float_status flags
8f2a0f5575 target/arm/cpu.h: update comment for half-precision values
3059f5906d target/arm/cpu64: introduce ARM_V8_FP16 feature bit
aac25f27be include/exec/helper-head.h: support f16 in helper calls
5998ce1e24 arm/vexpress: Add proper display connector emulation
cd734131b2 hw/sii9022: Add support for Silicon Image SII9022
94b945c24d hw/i2c-ddc: Do not fail writes
fb66477d35 i2c: Move the bus class to i2c.h
96b6d99806 i2c: Fix some brace style issues
6fdd76003e xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
0a63d14eaa xilinx_spips: Enable only two slaves when reading/writing with stripe
3a5412277e hw: register: Run post_write hook on reset

=== OUTPUT BEGIN ===
Checking PATCH 1/42: hw: register: Run post_write hook on reset...
Checking PATCH 2/42: xilinx_spips: Enable only two slaves when reading/writing with stripe...
Checking PATCH 3/42: xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands...
Checking PATCH 4/42: i2c: Fix some brace style issues...
Checking PATCH 5/42: i2c: Move the bus class to i2c.h...
Checking PATCH 6/42: hw/i2c-ddc: Do not fail writes...
Checking PATCH 7/42: hw/sii9022: Add support for Silicon Image SII9022...
Checking PATCH 8/42: arm/vexpress: Add proper display connector emulation...
Checking PATCH 9/42: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 10/42: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 11/42: target/arm/cpu.h: update comment for half-precision values...
Checking PATCH 12/42: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 13/42: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 14/42: arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)...
Checking PATCH 15/42: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 16/42: arm/translate-a64: initial decode for simd_three_reg_same_fp16...
Checking PATCH 17/42: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16...
Checking PATCH 18/42: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16...
Checking PATCH 19/42: arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16...
Checking PATCH 20/42: arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16...
Checking PATCH 21/42: arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16...
Checking PATCH 22/42: arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed...
Checking PATCH 23/42: arm/translate-a64: add FP16 x2 ops for simd_indexed...
Checking PATCH 24/42: arm/translate-a64: initial decode for simd_two_reg_misc_fp16...
Checking PATCH 25/42: arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16...
Checking PATCH 26/42: arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16...
Checking PATCH 27/42: arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16...
Checking PATCH 28/42: arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16...
ERROR: space prohibited before that close parenthesis ')'
#28: FILE: target/arm/helper.c:11305:
+FLOAT_CONVS(si, h, 16, )

total: 1 errors, 0 warnings, 208 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 29/42: arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16...
Checking PATCH 30/42: arm/helper.c: re-factor recpe and add recepe_f16...
Checking PATCH 31/42: arm/translate-a64: add FP16 FRECPE...
Checking PATCH 32/42: arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16...
Checking PATCH 33/42: arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16...
Checking PATCH 34/42: arm/helper.c: re-factor rsqrte and add rsqrte_f16...
Checking PATCH 35/42: arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16...
Checking PATCH 36/42: arm/translate-a64: add FP16 FMOV to simd_mod_imm...
Checking PATCH 37/42: arm/translate-a64: add all FP16 ops in simd_scalar_pairwise...
Checking PATCH 38/42: arm/translate-a64: implement simd_scalar_three_reg_same_fp16...
Checking PATCH 39/42: arm/translate-a64: add all single op FP16 to handle_fp_1src_half...
Checking PATCH 40/42: target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU...
Checking PATCH 41/42: linux-user: Report AArch64 FP16 support via hwcap bits...
Checking PATCH 42/42: MAINTAINERS: Update my email address...
=== OUTPUT END ===

Test command exited with code: 1

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