From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7B3BCA9EAF for ; Thu, 24 Oct 2019 16:11:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4E7C205F4 for ; Thu, 24 Oct 2019 16:11:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436800AbfJXQLA (ORCPT ); Thu, 24 Oct 2019 12:11:00 -0400 Received: from foss.arm.com ([217.140.110.172]:55488 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436675AbfJXQLA (ORCPT ); Thu, 24 Oct 2019 12:11:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2834228; Thu, 24 Oct 2019 09:10:47 -0700 (PDT) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09B8D3F71F; Thu, 24 Oct 2019 09:10:45 -0700 (PDT) Subject: Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Mark Rutland , Suzuki K Poulose , Catalin Marinas , Will Deacon , Julien Thierry References: <20191019095521.31722-1-maz@kernel.org> <20191019095521.31722-5-maz@kernel.org> From: James Morse Message-ID: <151fc868-6709-3017-e34d-649ec0e1812c@arm.com> Date: Thu, 24 Oct 2019 17:10:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191019095521.31722-5-maz@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, On 19/10/2019 10:55, Marc Zyngier wrote: > When handling erratum 1319367, we must ensure that the page table > walker cannot parse the S1 page tables while the guest is in an > inconsistent state. This is done as follows: > > On guest entry: > - TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - all system registers are restored, except for TCR_EL1 and SCTLR_EL1 > - stage-2 is restored > - SCTLR_EL1 and TCR_EL1 are restored > > On guest exit: > - SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - stage-2 is disabled > - All host system registers are restored Reviewed-by: James Morse (whitespace nit below) > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 69e10b29cbd0..5765b17c38c7 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) > } > > write_sysreg(val, cptr_el2); > + > + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; > + > + isb(); > + /* > + * At this stage, and thanks to the above isb(), S2 is > + * configured and enabled. We can now restore the guest's S1 > + * configuration: SCTLR, and only then TCR. > + */ (note for my future self: because the guest may have had M=0 and rubbish in the TTBRs) > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + isb(); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } > } > > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c > index 7ddbc849b580..fb97547bfa79 100644 > --- a/arch/arm64/kvm/hyp/sysreg-sr.c > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c > @@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > { > write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2); > write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1); > - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + > + if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } else if (!ctxt->__hyp_running_vcpu) { > + /* > + * Must only be done for guest registers, hence the context > + * test. We'recoming from the host, so SCTLR.M is already (Nit: We'recoming?) > + * set. Pairs with __activate_traps_nvhe(). > + */ > + write_sysreg_el1((ctxt->sys_regs[TCR_EL1] | > + TCR_EPD1_MASK | TCR_EPD0_MASK), > + SYS_TCR); > + isb(); > + } Thanks, James From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1647BCA9EBB for ; Thu, 24 Oct 2019 16:10:52 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id C6C56205F4 for ; Thu, 24 Oct 2019 16:10:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6C56205F4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6B58B4A5D5; Thu, 24 Oct 2019 12:10:51 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zYvB8kyQu3-2; Thu, 24 Oct 2019 12:10:50 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 550684A609; Thu, 24 Oct 2019 12:10:50 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0479F4A609 for ; Thu, 24 Oct 2019 12:10:49 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6nv-j1ghPc4n for ; Thu, 24 Oct 2019 12:10:47 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6A46D4A586 for ; Thu, 24 Oct 2019 12:10:47 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2834228; Thu, 24 Oct 2019 09:10:47 -0700 (PDT) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09B8D3F71F; Thu, 24 Oct 2019 09:10:45 -0700 (PDT) Subject: Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context To: Marc Zyngier References: <20191019095521.31722-1-maz@kernel.org> <20191019095521.31722-5-maz@kernel.org> From: James Morse Message-ID: <151fc868-6709-3017-e34d-649ec0e1812c@arm.com> Date: Thu, 24 Oct 2019 17:10:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191019095521.31722-5-maz@kernel.org> Content-Language: en-GB Cc: kvm@vger.kernel.org, Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, On 19/10/2019 10:55, Marc Zyngier wrote: > When handling erratum 1319367, we must ensure that the page table > walker cannot parse the S1 page tables while the guest is in an > inconsistent state. This is done as follows: > > On guest entry: > - TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - all system registers are restored, except for TCR_EL1 and SCTLR_EL1 > - stage-2 is restored > - SCTLR_EL1 and TCR_EL1 are restored > > On guest exit: > - SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - stage-2 is disabled > - All host system registers are restored Reviewed-by: James Morse (whitespace nit below) > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 69e10b29cbd0..5765b17c38c7 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) > } > > write_sysreg(val, cptr_el2); > + > + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; > + > + isb(); > + /* > + * At this stage, and thanks to the above isb(), S2 is > + * configured and enabled. We can now restore the guest's S1 > + * configuration: SCTLR, and only then TCR. > + */ (note for my future self: because the guest may have had M=0 and rubbish in the TTBRs) > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + isb(); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } > } > > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c > index 7ddbc849b580..fb97547bfa79 100644 > --- a/arch/arm64/kvm/hyp/sysreg-sr.c > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c > @@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > { > write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2); > write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1); > - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + > + if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } else if (!ctxt->__hyp_running_vcpu) { > + /* > + * Must only be done for guest registers, hence the context > + * test. We'recoming from the host, so SCTLR.M is already (Nit: We'recoming?) > + * set. Pairs with __activate_traps_nvhe(). > + */ > + write_sysreg_el1((ctxt->sys_regs[TCR_EL1] | > + TCR_EPD1_MASK | TCR_EPD0_MASK), > + SYS_TCR); > + isb(); > + } Thanks, James _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3718CA9EAF for ; Thu, 24 Oct 2019 16:11:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6EA72166E for ; Thu, 24 Oct 2019 16:11:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Q5MJF4ac" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6EA72166E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e+r63xSvFmA+rPV/FEHUkcDMOyk5f2/+GShlXOslIOU=; b=Q5MJF4acKCNukX oayyMz6H41vJHz8bHlCP6Bc1ELTMFl7pMGFpp/73FBaTXJzG5ktN4AWjbFn2gENCMZmftGGex+Lp7 FORKnlegV5HWy4mK4LzFIvT+0AmakfwiEI5vmCySNvcS1upwqqxroR3ZLo+vp9AfpecrdSgaqGCZ6 Y4YTTlmYTVF3Mtz8xGWKFy6QvGwxfehnelqfcPgXs/Gf9MwnrXRU5hqoJI90MOqJ12JHtEnoNb4vs 68zR39t4Y7NV5egWmcZtR47/R6n8O+ZvUxopjUqggAkPkjIBGi13dR2ImSl6/+rO1nQzQCCwT2yg/ rltk1gkQGipghr34bwEQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iNfhc-00026p-Ez; Thu, 24 Oct 2019 16:11:08 +0000 Received: from [217.140.110.172] (helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iNfhS-0001qc-Po for linux-arm-kernel@lists.infradead.org; Thu, 24 Oct 2019 16:11:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2834228; Thu, 24 Oct 2019 09:10:47 -0700 (PDT) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09B8D3F71F; Thu, 24 Oct 2019 09:10:45 -0700 (PDT) Subject: Re: [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context To: Marc Zyngier References: <20191019095521.31722-1-maz@kernel.org> <20191019095521.31722-5-maz@kernel.org> From: James Morse Message-ID: <151fc868-6709-3017-e34d-649ec0e1812c@arm.com> Date: Thu, 24 Oct 2019 17:10:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191019095521.31722-5-maz@kernel.org> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191024_091058_905988_A8FEADDF X-CRM114-Status: GOOD ( 18.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , kvm@vger.kernel.org, Suzuki K Poulose , Catalin Marinas , Julien Thierry , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 19/10/2019 10:55, Marc Zyngier wrote: > When handling erratum 1319367, we must ensure that the page table > walker cannot parse the S1 page tables while the guest is in an > inconsistent state. This is done as follows: > > On guest entry: > - TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - all system registers are restored, except for TCR_EL1 and SCTLR_EL1 > - stage-2 is restored > - SCTLR_EL1 and TCR_EL1 are restored > > On guest exit: > - SCTLR_EL1.M and TCR_EL1.EPD{0,1} are set, ensuring that no PTW can occur > - stage-2 is disabled > - All host system registers are restored Reviewed-by: James Morse (whitespace nit below) > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 69e10b29cbd0..5765b17c38c7 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -118,6 +118,20 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) > } > > write_sysreg(val, cptr_el2); > + > + if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; > + > + isb(); > + /* > + * At this stage, and thanks to the above isb(), S2 is > + * configured and enabled. We can now restore the guest's S1 > + * configuration: SCTLR, and only then TCR. > + */ (note for my future self: because the guest may have had M=0 and rubbish in the TTBRs) > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + isb(); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } > } > > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c > index 7ddbc849b580..fb97547bfa79 100644 > --- a/arch/arm64/kvm/hyp/sysreg-sr.c > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c > @@ -117,12 +117,26 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > { > write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2); > write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1); > - write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + > + if (!cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { > + write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR); > + write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR); > + } else if (!ctxt->__hyp_running_vcpu) { > + /* > + * Must only be done for guest registers, hence the context > + * test. We'recoming from the host, so SCTLR.M is already (Nit: We'recoming?) > + * set. Pairs with __activate_traps_nvhe(). > + */ > + write_sysreg_el1((ctxt->sys_regs[TCR_EL1] | > + TCR_EPD1_MASK | TCR_EPD0_MASK), > + SYS_TCR); > + isb(); > + } Thanks, James _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel