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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	RISC-V Patches map <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v1 04/22] RISC-V: Use ROM base address and size from memory
Date: Wed,  7 Mar 2018 09:43:39 +1300	[thread overview]
Message-ID: <1520369037-37977-5-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1520369037-37977-1-git-send-email-mjc@sifive.com>

Another case of replaceing hard coded constants, this time
referring to the definition in the virt machine's memmap.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/virt.c         | 4 ++--
 include/hw/riscv/virt.h | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0055439..0d101fc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -338,11 +338,11 @@ static void riscv_virt_board_init(MachineState *machine)
     };
 
     /* copy in the reset vector */
-    copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec));
+    copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec));
 
     /* copy in the device tree */
     qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
-    cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec),
+    cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
         s->fdt, s->fdt_size);
 
     /* create PLIC hart topology configuration string */
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 2fbe808..655e85d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,8 +23,6 @@
 #define VIRT(obj) \
     OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
 
-enum { ROM_BASE = 0x1000 };
-
 typedef struct {
     /*< private >*/
     SysBusDevice parent_obj;
-- 
2.7.0

  parent reply	other threads:[~2018-03-06 20:45 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-06 20:43 [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 01/22] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-06 22:56   ` Philippe Mathieu-Daudé
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike Michael Clark
2018-03-06 20:43 ` Michael Clark [this message]
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 05/22] RISC-V: Remove redundant identity_translate from Michael Clark
2018-03-06 23:00   ` Philippe Mathieu-Daudé
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code and Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from Michael Clark
     [not found]   ` <8787c302-b90a-df1f-9eb3-3ee16022a92e@amsat.org>
2018-03-07  4:14     ` Michael Clark
2018-03-07  4:30       ` Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure the emulated rom has space for Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in Michael Clark
2018-03-06 23:09   ` Philippe Mathieu-Daudé
2018-03-07  4:17     ` Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-09  3:54   ` Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in atomic pte Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 17/22] RISC-V: Ingore satp writes and return 0 for reads Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with Michael Clark
2018-03-06 23:09   ` Philippe Mathieu-Daudé
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional Michael Clark
2018-03-06 23:07 ` [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups Michael Clark
2018-03-06 23:47   ` Emilio G. Cota
2018-03-07  0:00     ` Michael Clark
2018-03-07 17:40       ` Emilio G. Cota

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