From: Ravi Kumar <Ravi1.kumar@amd.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com
Subject: [PATCH v3 03/18] net/axgbe: add phy register map and helper macros
Date: Fri, 9 Mar 2018 03:42:19 -0500 [thread overview]
Message-ID: <1520584954-130575-3-git-send-email-Ravi1.kumar@amd.com> (raw)
In-Reply-To: <1520584954-130575-1-git-send-email-Ravi1.kumar@amd.com>
Signed-off-by: Ravi Kumar <Ravi1.kumar@amd.com>
---
drivers/net/axgbe/axgbe_phy.h | 314 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 314 insertions(+)
create mode 100644 drivers/net/axgbe/axgbe_phy.h
diff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h
new file mode 100644
index 0000000..f7c8a88
--- /dev/null
+++ b/drivers/net/axgbe/axgbe_phy.h
@@ -0,0 +1,314 @@
+/*-
+ * Copyright(c) 2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2013 Synopsys, Inc.
+ *
+ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ * Inc. unless otherwise expressly agreed to in writing between Synopsys
+ * and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for Licensed
+ * Product with Synopsys or any supplement thereto. Permission is hereby
+ * granted, free of charge, to any person obtaining a copy of this software
+ * annotated with this license and the Software, to deal in the Software
+ * without restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2013 Synopsys, Inc.
+ *
+ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ * Inc. unless otherwise expressly agreed to in writing between Synopsys
+ * and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for Licensed
+ * Product with Synopsys or any supplement thereto. Permission is hereby
+ * granted, free of charge, to any person obtaining a copy of this software
+ * annotated with this license and the Software, to deal in the Software
+ * without restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AXGBE_PHY_H__
+#define __AXGBE_PHY_H__
+
+#define SPEED_10 10
+#define SPEED_100 100
+#define SPEED_1000 1000
+#define SPEED_2500 2500
+#define SPEED_10000 10000
+
+
+/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
+ * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
+ */
+#define MII_ADDR_C45 (1 << 30)
+
+/* Basic mode status register. */
+#define BMSR_LSTATUS 0x0004 /* Link status */
+
+/* Status register 1. */
+#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
+
+/* Generic MII registers. */
+#define MII_BMCR 0x00 /* Basic mode control register */
+#define MII_BMSR 0x01 /* Basic mode status register */
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */
+#define MII_LPA 0x05 /* Link partner ability reg */
+#define MII_EXPANSION 0x06 /* Expansion register */
+#define MII_CTRL1000 0x09 /* 1000BASE-T control */
+#define MII_STAT1000 0x0a /* 1000BASE-T status */
+#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
+#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
+#define MII_ESTATUS 0x0f /* Extended Status */
+#define MII_DCOUNTER 0x12 /* Disconnect counter */
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */
+#define MII_SREVISION 0x16 /* Silicon revision */
+#define MII_RESV1 0x17 /* Reserved... */
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
+#define MII_PHYADDR 0x19 /* PHY address */
+#define MII_RESV2 0x1a /* Reserved... */
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
+#define MII_NCONFIG 0x1c /* Network interface config */
+
+/* Basic mode control register. */
+#define BMCR_RESV 0x003f /* Unused... */
+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
+#define BMCR_CTST 0x0080 /* Collision test */
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
+#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
+#define BMCR_PDOWN 0x0800 /* Enable low power state */
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
+#define BMCR_RESET 0x8000 /* Reset to default state */
+#define BMCR_SPEED10 0x0000 /* Select 10Mbps */
+
+
+/* MDIO Manageable Devices (MMDs). */
+#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment
+ * Physical Medium Dependent
+ */
+#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
+#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
+#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
+#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
+#define MDIO_MMD_TC 6 /* Transmission Convergence */
+#define MDIO_MMD_AN 7 /* Auto-Negotiation */
+#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
+#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
+#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
+
+/* Generic MDIO registers. */
+#define MDIO_CTRL1 MII_BMCR
+#define MDIO_STAT1 MII_BMSR
+#define MDIO_DEVID1 MII_PHYSID1
+#define MDIO_DEVID2 MII_PHYSID2
+#define MDIO_SPEED 4 /* Speed ability */
+#define MDIO_DEVS1 5 /* Devices in package */
+#define MDIO_DEVS2 6
+#define MDIO_CTRL2 7 /* 10G control 2 */
+#define MDIO_STAT2 8 /* 10G status 2 */
+#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
+#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
+#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
+#define MDIO_PKGID1 14 /* Package identifier */
+#define MDIO_PKGID2 15
+#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
+#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
+#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
+#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
+#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
+#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
+#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
+
+/* Media-dependent registers. */
+#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
+#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
+#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
+ * Lanes B-D are numbered 134-136.
+ */
+#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
+#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
+#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
+#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
+
+/* Control register 1. */
+/* Enable extended speed selection */
+#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
+/* All speed selection bits */
+#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
+#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
+#define MDIO_CTRL1_LPOWER BMCR_PDOWN
+#define MDIO_CTRL1_RESET BMCR_RESET
+#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
+#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
+#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
+#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
+#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
+#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
+#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
+#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
+#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
+
+
+
+
+
+/* PMA 10GBASE-R FEC ability register. */
+#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
+#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
+
+
+/* Autoneg related */
+#define ADVERTISED_Autoneg (1 << 6)
+#define SUPPORTED_Autoneg (1 << 6)
+#define AUTONEG_DISABLE 0x00
+#define AUTONEG_ENABLE 0x01
+
+#define ADVERTISED_Pause (1 << 13)
+#define ADVERTISED_Asym_Pause (1 << 14)
+
+#define SUPPORTED_Pause (1 << 13)
+#define SUPPORTED_Asym_Pause (1 << 14)
+
+#define SUPPORTED_Backplane (1 << 16)
+#define SUPPORTED_TP (1 << 7)
+
+#define ADVERTISED_10000baseR_FEC (1 << 20)
+
+#define SUPPORTED_10000baseR_FEC (1 << 20)
+
+#define SUPPORTED_FIBRE (1 << 10)
+
+#define ADVERTISED_10000baseKR_Full (1 << 19)
+#define ADVERTISED_10000baseT_Full (1 << 12)
+#define ADVERTISED_2500baseX_Full (1 << 15)
+#define ADVERTISED_1000baseKX_Full (1 << 17)
+#define ADVERTISED_1000baseT_Full (1 << 5)
+#define ADVERTISED_100baseT_Full (1 << 3)
+#define ADVERTISED_TP (1 << 7)
+#define ADVERTISED_FIBRE (1 << 10)
+#define ADVERTISED_Backplane (1 << 16)
+
+#define SUPPORTED_1000baseKX_Full (1 << 17)
+#define SUPPORTED_10000baseKR_Full (1 << 19)
+#define SUPPORTED_2500baseX_Full (1 << 15)
+#define SUPPORTED_100baseT_Full (1 << 2)
+#define SUPPORTED_1000baseT_Full (1 << 5)
+#define SUPPORTED_10000baseT_Full (1 << 12)
+#define SUPPORTED_2500baseX_Full (1 << 15)
+
+
+#define SPEED_UNKNOWN -1
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF 0x00
+#define DUPLEX_FULL 0x01
+#define DUPLEX_UNKNOWN 0xff
+
+#endif
+/* PHY */
--
2.7.4
next prev parent reply other threads:[~2018-03-09 8:43 UTC|newest]
Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-30 13:10 [PATCH 01/16] net/axgbe: add minimal dev init and uninit support Ravi Kumar
2017-11-30 13:10 ` [PATCH 02/16] net/axgbe: add register map and related macros Ravi Kumar
2017-12-08 21:04 ` Ferruh Yigit
2017-12-11 7:20 ` Jianbo Liu
2017-11-30 13:10 ` [PATCH 03/16] net/axgbe: add phy register map and helper macros Ravi Kumar
2017-11-30 13:11 ` [PATCH 04/16] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2017-12-08 21:05 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 05/16] net/axgbe: add phy initialization and related apis Ravi Kumar
2017-11-30 13:11 ` [PATCH 06/16] net/axgbe: add phy programming apis Ravi Kumar
2017-11-30 13:11 ` [PATCH 07/16] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2017-12-08 21:06 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 08/16] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2017-11-30 13:11 ` [PATCH 09/16] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2017-12-08 21:07 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 10/16] net/axgbe: add transmit and receive data path apis Ravi Kumar
2017-12-08 21:08 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 11/16] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2017-11-30 13:11 ` [PATCH 12/16] net/axgbe: add promiscuous mode support Ravi Kumar
2017-12-08 21:08 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 13/16] net/axgbe: add generic transmit and receive stats support Ravi Kumar
2017-11-30 13:11 ` [PATCH 14/16] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2017-12-08 21:09 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 15/16] net/axgbe: add support for icc and clang build Ravi Kumar
2017-11-30 13:11 ` [PATCH 16/16] net/axgbe: add support for build 32-bit mode Ravi Kumar
2017-12-08 21:10 ` Ferruh Yigit
2017-12-05 0:25 ` [PATCH 01/16] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2017-12-08 21:04 ` Ferruh Yigit
2017-12-09 13:18 ` Kumar, Ravi1
2018-01-05 9:52 ` [PATCH v2 " Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 02/16] net/axgbe: add register map and related macros Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 03/16] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 04/16] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 05/16] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 06/16] net/axgbe: add phy programming apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 07/16] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 08/16] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 09/16] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 10/16] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 11/16] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-01-05 20:33 ` Stephen Hemminger
2018-01-08 5:40 ` Kumar, Ravi1
2018-01-15 14:51 ` Kovacevic, Marko
2018-01-05 9:52 ` [PATCH v2 12/16] net/axgbe: add link status update Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 13/16] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 14/16] net/axgbe: add promiscuous mode support Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 15/16] net/axgbe: add generic transmit and receive status support Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 16/16] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-01-05 20:32 ` Stephen Hemminger
2018-01-09 20:17 ` [PATCH v2 01/16] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-01-11 6:42 ` Kumar, Ravi1
2018-03-09 8:42 ` [PATCH v3 01/18] " Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 02/18] net/axgbe: add register map and related macros Ravi Kumar
2018-03-09 8:42 ` Ravi Kumar [this message]
2018-03-09 8:42 ` [PATCH v3 04/18] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-03-16 17:43 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 05/18] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 06/18] net/axgbe: add phy programming apis Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 07/18] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 08/18] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-03-16 17:44 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 09/18] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 10/18] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-03-16 17:45 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 11/18] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-03-16 17:46 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 12/18] net/axgbe: add link status update Ravi Kumar
2018-03-16 17:46 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 13/18] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 14/18] net/axgbe: add promiscuous mode support Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 15/18] net/axgbe: add generic transmit and receive stats support Ravi Kumar
2018-03-16 17:47 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 16/18] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 17/18] net/axgbe: add workaround for axgbe ethernet training bug Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 18/18] net/axgbe: moved license headers to SPDX format Ravi Kumar
2018-03-11 23:31 ` Stephen Hemminger
2018-03-12 11:23 ` Kumar, Ravi1
2018-03-09 16:13 ` [PATCH v3 01/18] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-03-09 16:39 ` Ferruh Yigit
2018-03-12 11:25 ` Kumar, Ravi1
2018-03-16 17:42 ` Ferruh Yigit
2018-03-19 12:33 ` Kumar, Ravi1
2018-04-03 12:21 ` Ferruh Yigit
2018-04-05 6:39 ` [PATCH v4 01/17] " Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 02/17] net/axgbe: add register map and related macros Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 03/17] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 04/17] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 05/17] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 06/17] net/axgbe: add phy programming apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 07/17] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 08/17] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 09/17] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 10/17] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-04-05 11:34 ` Ferruh Yigit
2018-04-06 12:40 ` Kumar, Ravi1
2018-04-05 6:39 ` [PATCH v4 11/17] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 12/17] net/axgbe: add link status update Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 13/17] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 14/17] net/axgbe: add promiscuous mode support Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 15/17] net/axgbe: support generic transmit and receive stats api Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 16/17] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 17/17] net/axgbe: add workaround for axgbe ethernet training bug Ravi Kumar
2018-04-05 11:35 ` Ferruh Yigit
2018-04-06 12:41 ` Kumar, Ravi1
2018-04-05 11:34 ` [PATCH v4 01/17] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-04-06 12:39 ` Kumar, Ravi1
2018-04-06 12:36 ` [PATCH v5 01/18] " Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 02/18] net/axgbe: add register map and related macros Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 03/18] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 04/18] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 05/18] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 06/18] net/axgbe: add phy programming apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 07/18] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 08/18] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-04-09 4:49 ` Rosen, Rami
2018-04-09 12:30 ` Ferruh Yigit
2018-04-06 12:36 ` [PATCH v5 09/18] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 10/18] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 11/18] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 12/18] net/axgbe: add link status update Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 13/18] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 14/18] net/axgbe: add promiscuous mode support Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 15/18] net/axgbe: support generic transmit and receive stats api Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 16/18] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 17/18] net/axgbe: add workaround for axgbe ethernet training bug Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 18/18] net/axgbe : support meson build Ravi Kumar
2018-04-06 15:55 ` [PATCH v5 01/18] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-04-09 6:00 ` Kumar, Ravi1
2018-11-22 14:39 ` Ferruh Yigit
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