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From: Michael Clark <mjc@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation
Date: Sat, 10 Mar 2018 09:29:34 +1300	[thread overview]
Message-ID: <1520627374-93719-1-git-send-email-mjc@sifive.com> (raw)

The following changes since commit e4ae62b802cec437f877f2cadc4ef059cc0eca76:

  Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2018-03-09 17:28:16 +0000)

are available in the git repository at:

  https://github.com/michaeljclark/riscv-qemu.git fix-riscv-isa-string

for you to fetch changes up to 32b3a5716062f805a42e1cae1df95f2f869a78c1:

  RISC-V: Fix isa string logic bug, use popcount to count bits (2018-03-10 09:17:29 +1300)

----------------------------------------------------------------
Michael Clark (1):
      RISC-V: Fix isa string logic bug, use popcount to count bits

 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

             reply	other threads:[~2018-03-09 20:30 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-09 20:29 Michael Clark [this message]
2018-03-09 20:54 ` [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size calculation Michael Clark
2018-03-10 16:51   ` Peter Maydell

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