* [PATCH v1 0/2] arm: npcm: Modify NPCM7XX machine code
@ 2018-03-15 23:10 ` Tomer Maimon
0 siblings, 0 replies; 23+ messages in thread
From: Tomer Maimon @ 2018-03-15 23:10 UTC (permalink / raw)
To: arnd, venture, yuenn, brendanhiggins, avifishman70, joel
Cc: openbmc, linux-kernel, linux-arm-kernel, Tomer Maimon
Addressed patches from:
Arnd Bergmann: https://www.spinics.net/lists/arm-kernel/msg639250.html
https://www.spinics.net/lists/arm-kernel/msg639249.html
Modify the NPCM and NPCM7XX configuration and enable L2 cache in
the DT_MACHINE_START.
Tomer Maimon (2):
arm: npcm: modify configuration for the NPCM7xx BMC.
arm: npcm: Enable L2 Cache in NPCM7xx
arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
arch/arm/mach-npcm/Makefile | 4 +++-
arch/arm/mach-npcm/npcm7xx.c | 2 ++
3 files changed, 16 insertions(+), 30 deletions(-)
--
2.14.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 0/2] arm: npcm: Modify NPCM7XX machine code
@ 2018-03-15 23:10 ` Tomer Maimon
0 siblings, 0 replies; 23+ messages in thread
From: Tomer Maimon @ 2018-03-15 23:10 UTC (permalink / raw)
To: linux-arm-kernel
Addressed patches from:
Arnd Bergmann: https://www.spinics.net/lists/arm-kernel/msg639250.html
https://www.spinics.net/lists/arm-kernel/msg639249.html
Modify the NPCM and NPCM7XX configuration and enable L2 cache in
the DT_MACHINE_START.
Tomer Maimon (2):
arm: npcm: modify configuration for the NPCM7xx BMC.
arm: npcm: Enable L2 Cache in NPCM7xx
arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
arch/arm/mach-npcm/Makefile | 4 +++-
arch/arm/mach-npcm/npcm7xx.c | 2 ++
3 files changed, 16 insertions(+), 30 deletions(-)
--
2.14.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
2018-03-15 23:10 ` Tomer Maimon
@ 2018-03-15 23:10 ` Tomer Maimon
-1 siblings, 0 replies; 23+ messages in thread
From: Tomer Maimon @ 2018-03-15 23:10 UTC (permalink / raw)
To: arnd, venture, yuenn, brendanhiggins, avifishman70, joel
Cc: openbmc, linux-kernel, linux-arm-kernel, Tomer Maimon
Modify configuration and MakeFile
for the Nuvoton NPCM and NPCM7xx BMC.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
arch/arm/mach-npcm/Makefile | 4 +++-
2 files changed, 14 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index 6ff9df2636be..684c9c9a32bd 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -1,48 +1,30 @@
menuconfig ARCH_NPCM
bool "Nuvoton NPCM Architecture"
- select ARCH_REQUIRE_GPIOLIB
- select USE_OF
+ depends on ARCH_MULTI_V7
select PINCTRL
- select PINCTRL_NPCM7XX
if ARCH_NPCM
-comment "NPCM7XX CPU type"
-
-config ARCH_NPCM750
- depends on ARCH_NPCM && ARCH_MULTI_V7
- bool "Support for NPCM750 BMC CPU (Poleg)"
+config ARCH_NPCM7XX
+ bool "Support for NPCM7xx BMC (Poleg)"
+ depends on ARCH_MULTI_V7
+ select PINCTRL_NPCM7XX
+ select NPCM7XX_TIMER
+ select ARCH_REQUIRE_GPIOLIB
select CACHE_L2X0
- select CPU_V7
select ARM_GIC
- select HAVE_SMP
- select SMP
- select SMP_ON_UP
- select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU if SMP
+ select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_754322
- select ARM_ERRATA_764369
select ARM_ERRATA_794072
select PL310_ERRATA_588369
select PL310_ERRATA_727915
- select USB_EHCI_ROOT_HUB_TT
- select USB_ARCH_HAS_HCD
- select USB_ARCH_HAS_EHCI
- select USB_EHCI_HCD
- select USB_ARCH_HAS_OHCI
- select USB_OHCI_HCD
- select USB
- select FIQ
- select CPU_USE_DOMAINS
- select GENERIC_CLOCKEVENTS
- select CLKDEV_LOOKUP
- select COMMON_CLK if OF
- select NPCM750_TIMER
select MFD_SYSCON
help
- Support for NPCM750 BMC CPU (Poleg).
+ General support for NPCM7xx BMC (Poleg).
- Nuvoton NPCM750 BMC based on the Cortex A9.
+ Nuvoton NPCM7xx BMC based on the Cortex A9.
endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
index c7a1316d27c1..0839e8926a84 100644
--- a/arch/arm/mach-npcm/Makefile
+++ b/arch/arm/mach-npcm/Makefile
@@ -1,3 +1,5 @@
AFLAGS_headsmp.o += -march=armv7-a
-obj-$(CONFIG_ARCH_NPCM750) += npcm7xx.o platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+
--
2.14.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
@ 2018-03-15 23:10 ` Tomer Maimon
0 siblings, 0 replies; 23+ messages in thread
From: Tomer Maimon @ 2018-03-15 23:10 UTC (permalink / raw)
To: linux-arm-kernel
Modify configuration and MakeFile
for the Nuvoton NPCM and NPCM7xx BMC.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
arch/arm/mach-npcm/Makefile | 4 +++-
2 files changed, 14 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index 6ff9df2636be..684c9c9a32bd 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -1,48 +1,30 @@
menuconfig ARCH_NPCM
bool "Nuvoton NPCM Architecture"
- select ARCH_REQUIRE_GPIOLIB
- select USE_OF
+ depends on ARCH_MULTI_V7
select PINCTRL
- select PINCTRL_NPCM7XX
if ARCH_NPCM
-comment "NPCM7XX CPU type"
-
-config ARCH_NPCM750
- depends on ARCH_NPCM && ARCH_MULTI_V7
- bool "Support for NPCM750 BMC CPU (Poleg)"
+config ARCH_NPCM7XX
+ bool "Support for NPCM7xx BMC (Poleg)"
+ depends on ARCH_MULTI_V7
+ select PINCTRL_NPCM7XX
+ select NPCM7XX_TIMER
+ select ARCH_REQUIRE_GPIOLIB
select CACHE_L2X0
- select CPU_V7
select ARM_GIC
- select HAVE_SMP
- select SMP
- select SMP_ON_UP
- select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU if SMP
+ select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_754322
- select ARM_ERRATA_764369
select ARM_ERRATA_794072
select PL310_ERRATA_588369
select PL310_ERRATA_727915
- select USB_EHCI_ROOT_HUB_TT
- select USB_ARCH_HAS_HCD
- select USB_ARCH_HAS_EHCI
- select USB_EHCI_HCD
- select USB_ARCH_HAS_OHCI
- select USB_OHCI_HCD
- select USB
- select FIQ
- select CPU_USE_DOMAINS
- select GENERIC_CLOCKEVENTS
- select CLKDEV_LOOKUP
- select COMMON_CLK if OF
- select NPCM750_TIMER
select MFD_SYSCON
help
- Support for NPCM750 BMC CPU (Poleg).
+ General support for NPCM7xx BMC (Poleg).
- Nuvoton NPCM750 BMC based on the Cortex A9.
+ Nuvoton NPCM7xx BMC based on the Cortex A9.
endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
index c7a1316d27c1..0839e8926a84 100644
--- a/arch/arm/mach-npcm/Makefile
+++ b/arch/arm/mach-npcm/Makefile
@@ -1,3 +1,5 @@
AFLAGS_headsmp.o += -march=armv7-a
-obj-$(CONFIG_ARCH_NPCM750) += npcm7xx.o platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+
--
2.14.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
2018-03-15 23:10 ` Tomer Maimon
@ 2018-03-15 23:10 ` Tomer Maimon
-1 siblings, 0 replies; 23+ messages in thread
From: Tomer Maimon @ 2018-03-15 23:10 UTC (permalink / raw)
To: arnd, venture, yuenn, brendanhiggins, avifishman70, joel
Cc: openbmc, linux-kernel, linux-arm-kernel, Tomer Maimon
Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
arch/arm/mach-npcm/npcm7xx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
index 5f7cd88103ef..c5f77d854c4f 100644
--- a/arch/arm/mach-npcm/npcm7xx.c
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
.atag_offset = 0x100,
.dt_compat = npcm7xx_dt_match,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
MACHINE_END
--
2.14.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-03-15 23:10 ` Tomer Maimon
0 siblings, 0 replies; 23+ messages in thread
From: Tomer Maimon @ 2018-03-15 23:10 UTC (permalink / raw)
To: linux-arm-kernel
Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
arch/arm/mach-npcm/npcm7xx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
index 5f7cd88103ef..c5f77d854c4f 100644
--- a/arch/arm/mach-npcm/npcm7xx.c
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
.atag_offset = 0x100,
.dt_compat = npcm7xx_dt_match,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
MACHINE_END
--
2.14.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
2018-03-15 23:10 ` Tomer Maimon
(?)
@ 2018-03-16 5:52 ` Brendan Higgins
-1 siblings, 0 replies; 23+ messages in thread
From: Brendan Higgins @ 2018-03-16 5:52 UTC (permalink / raw)
To: Tomer Maimon
Cc: Arnd Bergmann, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> Enable L2 Cache in Nuvoton NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm/mach-npcm/npcm7xx.c | 2 ++
> 1 file changed, 2 insertions(+)
> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> index 5f7cd88103ef..c5f77d854c4f 100644
> --- a/arch/arm/mach-npcm/npcm7xx.c
> +++ b/arch/arm/mach-npcm/npcm7xx.c
> @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
> DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> .atag_offset = 0x100,
> .dt_compat = npcm7xx_dt_match,
> + .l2c_aux_val = 0x0,
> + .l2c_aux_mask = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify
that
the l2c driver does not already manage that bit appropriately and that it
can
not be specified via the dtsi.
We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html
> MACHINE_END
> --
> 2.14.1
Cheers
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-03-16 5:52 ` Brendan Higgins
0 siblings, 0 replies; 23+ messages in thread
From: Brendan Higgins @ 2018-03-16 5:52 UTC (permalink / raw)
To: Tomer Maimon
Cc: Arnd Bergmann, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> Enable L2 Cache in Nuvoton NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm/mach-npcm/npcm7xx.c | 2 ++
> 1 file changed, 2 insertions(+)
> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> index 5f7cd88103ef..c5f77d854c4f 100644
> --- a/arch/arm/mach-npcm/npcm7xx.c
> +++ b/arch/arm/mach-npcm/npcm7xx.c
> @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
> DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> .atag_offset = 0x100,
> .dt_compat = npcm7xx_dt_match,
> + .l2c_aux_val = 0x0,
> + .l2c_aux_mask = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify
that
the l2c driver does not already manage that bit appropriately and that it
can
not be specified via the dtsi.
We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html
> MACHINE_END
> --
> 2.14.1
Cheers
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-03-16 5:52 ` Brendan Higgins
0 siblings, 0 replies; 23+ messages in thread
From: Brendan Higgins @ 2018-03-16 5:52 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> Enable L2 Cache in Nuvoton NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm/mach-npcm/npcm7xx.c | 2 ++
> 1 file changed, 2 insertions(+)
> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> index 5f7cd88103ef..c5f77d854c4f 100644
> --- a/arch/arm/mach-npcm/npcm7xx.c
> +++ b/arch/arm/mach-npcm/npcm7xx.c
> @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
> DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> .atag_offset = 0x100,
> .dt_compat = npcm7xx_dt_match,
> + .l2c_aux_val = 0x0,
> + .l2c_aux_mask = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify
that
the l2c driver does not already manage that bit appropriately and that it
can
not be specified via the dtsi.
We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html
> MACHINE_END
> --
> 2.14.1
Cheers
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
2018-03-15 23:10 ` Tomer Maimon
(?)
@ 2018-03-16 5:56 ` Brendan Higgins
-1 siblings, 0 replies; 23+ messages in thread
From: Brendan Higgins @ 2018-03-16 5:56 UTC (permalink / raw)
To: Tomer Maimon
Cc: Arnd Bergmann, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> Modify configuration and MakeFile
> for the Nuvoton NPCM and NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
> arch/arm/mach-npcm/Makefile | 4 +++-
> 2 files changed, 14 insertions(+), 30 deletions(-)
<snip>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
@ 2018-03-16 5:56 ` Brendan Higgins
0 siblings, 0 replies; 23+ messages in thread
From: Brendan Higgins @ 2018-03-16 5:56 UTC (permalink / raw)
To: Tomer Maimon
Cc: Arnd Bergmann, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> Modify configuration and MakeFile
> for the Nuvoton NPCM and NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
> arch/arm/mach-npcm/Makefile | 4 +++-
> 2 files changed, 14 insertions(+), 30 deletions(-)
<snip>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
@ 2018-03-16 5:56 ` Brendan Higgins
0 siblings, 0 replies; 23+ messages in thread
From: Brendan Higgins @ 2018-03-16 5:56 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> Modify configuration and MakeFile
> for the Nuvoton NPCM and NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
> arch/arm/mach-npcm/Makefile | 4 +++-
> 2 files changed, 14 insertions(+), 30 deletions(-)
<snip>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
2018-03-16 5:52 ` Brendan Higgins
(?)
(?)
@ 2018-03-16 21:51 ` Tomer Maimon
2018-04-05 12:54 ` Arnd Bergmann
-1 siblings, 1 reply; 23+ messages in thread
From: Tomer Maimon @ 2018-03-16 21:51 UTC (permalink / raw)
To: Brendan Higgins
Cc: Arnd Bergmann, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
[-- Attachment #1: Type: text/plain, Size: 1578 bytes --]
On 16 March 2018 at 07:52, Brendan Higgins <brendanhiggins@google.com>
wrote:
> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> > Enable L2 Cache in Nuvoton NPCM7xx BMC.
>
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> > arch/arm/mach-npcm/npcm7xx.c | 2 ++
> > 1 file changed, 2 insertions(+)
>
> > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> > index 5f7cd88103ef..c5f77d854c4f 100644
> > --- a/arch/arm/mach-npcm/npcm7xx.c
> > +++ b/arch/arm/mach-npcm/npcm7xx.c
> > @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
> > DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> > .atag_offset = 0x100,
> > .dt_compat = npcm7xx_dt_match,
> > + .l2c_aux_val = 0x0,
> > + .l2c_aux_mask = ~0x0,
>
> You need to limit this to the specific bit(s) you want to set and verify
> that
> the l2c driver does not already manage that bit appropriately and that it
> can
> not be specified via the dtsi.
>
Do you mean that I need to specify it the same as been done in V7?
because when I run with the above l2c_aux_val and l2c_aux_mask parameters
I get the same result.
Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to
the DT_MACHINE_START
the L2C cache does not initialize.
>
> We discussed this a little while ago with Rob here:
> https://www.spinics.net/lists/arm-kernel/msg613372.html
Sorry in this link I see only Russel king comment regarding the L2C
>
>
> > MACHINE_END
> > --
> > 2.14.1
>
>
> Cheers
>
Cheers
[-- Attachment #2: Type: text/html, Size: 5562 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
2018-03-16 5:56 ` Brendan Higgins
(?)
@ 2018-04-05 12:51 ` Arnd Bergmann
-1 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 12:51 UTC (permalink / raw)
To: Brendan Higgins
Cc: Tomer Maimon, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Fri, Mar 16, 2018 at 6:56 AM, Brendan Higgins
<brendanhiggins@google.com> wrote:
> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>
>> Modify configuration and MakeFile
>> for the Nuvoton NPCM and NPCM7xx BMC.
>
>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>> ---
>> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
>> arch/arm/mach-npcm/Makefile | 4 +++-
>> 2 files changed, 14 insertions(+), 30 deletions(-)
>
> <snip>
>
> Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Sorry for missing this earlier, I did ask for the rework but then
didn't see it as it
wasn't in my arm@kernel.org inbox.
Tomer, please make sure that all patches you want to have included in
the kernel are sent to that address, while patches you want to have reviewed
are not sent to it.
Normally I don't apply patches during the merge window, but this one fixes
some build problems, so I've decided to take it.
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
@ 2018-04-05 12:51 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 12:51 UTC (permalink / raw)
To: Brendan Higgins
Cc: Tomer Maimon, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Fri, Mar 16, 2018 at 6:56 AM, Brendan Higgins
<brendanhiggins@google.com> wrote:
> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>
>> Modify configuration and MakeFile
>> for the Nuvoton NPCM and NPCM7xx BMC.
>
>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>> ---
>> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
>> arch/arm/mach-npcm/Makefile | 4 +++-
>> 2 files changed, 14 insertions(+), 30 deletions(-)
>
> <snip>
>
> Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Sorry for missing this earlier, I did ask for the rework but then
didn't see it as it
wasn't in my arm@kernel.org inbox.
Tomer, please make sure that all patches you want to have included in
the kernel are sent to that address, while patches you want to have reviewed
are not sent to it.
Normally I don't apply patches during the merge window, but this one fixes
some build problems, so I've decided to take it.
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.
@ 2018-04-05 12:51 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 12:51 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Mar 16, 2018 at 6:56 AM, Brendan Higgins
<brendanhiggins@google.com> wrote:
> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>
>> Modify configuration and MakeFile
>> for the Nuvoton NPCM and NPCM7xx BMC.
>
>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>> ---
>> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
>> arch/arm/mach-npcm/Makefile | 4 +++-
>> 2 files changed, 14 insertions(+), 30 deletions(-)
>
> <snip>
>
> Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Sorry for missing this earlier, I did ask for the rework but then
didn't see it as it
wasn't in my arm at kernel.org inbox.
Tomer, please make sure that all patches you want to have included in
the kernel are sent to that address, while patches you want to have reviewed
are not sent to it.
Normally I don't apply patches during the merge window, but this one fixes
some build problems, so I've decided to take it.
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
2018-03-16 21:51 ` Tomer Maimon
2018-04-05 12:54 ` Arnd Bergmann
@ 2018-04-05 12:54 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 12:54 UTC (permalink / raw)
To: Tomer Maimon
Cc: Brendan Higgins, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
>
> On 16 March 2018 at 07:52, Brendan Higgins <brendanhiggins@google.com>
> wrote:
>>
>> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>>
>> > Enable L2 Cache in Nuvoton NPCM7xx BMC.
>>
>> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>> > ---
>> > arch/arm/mach-npcm/npcm7xx.c | 2 ++
>> > 1 file changed, 2 insertions(+)
>>
>> > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
>> > index 5f7cd88103ef..c5f77d854c4f 100644
>> > --- a/arch/arm/mach-npcm/npcm7xx.c
>> > +++ b/arch/arm/mach-npcm/npcm7xx.c
>> > @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
>> > DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
>> > .atag_offset = 0x100,
>> > .dt_compat = npcm7xx_dt_match,
>> > + .l2c_aux_val = 0x0,
>> > + .l2c_aux_mask = ~0x0,
>>
>> You need to limit this to the specific bit(s) you want to set and verify
>> that
>> the l2c driver does not already manage that bit appropriately and that it
>> can
>> not be specified via the dtsi.
>
>
> Do you mean that I need to specify it the same as been done in V7?
> because when I run with the above l2c_aux_val and l2c_aux_mask parameters I
> get the same result.
>
> Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to the
> DT_MACHINE_START
> the L2C cache does not initialize.
>>
>>
>> We discussed this a little while ago with Rob here:
>> https://www.spinics.net/lists/arm-kernel/msg613372.html
>
>
> Sorry in this link I see only Russel king comment regarding the L2C
I'm not sure what the outcome is, and the patch changelog doesn't
explain what the patch is for, so I've not applied it. If you need the
patch for correct operation, please resend it with a proper changelog
comment explaining why it's needed and why you ended up not setting
any of the bits.
The last email in that thread mentions
L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-04-05 12:54 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 12:54 UTC (permalink / raw)
To: Tomer Maimon
Cc: Brendan Higgins, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
>
> On 16 March 2018 at 07:52, Brendan Higgins <brendanhiggins@google.com>
> wrote:
>>
>> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>>
>> > Enable L2 Cache in Nuvoton NPCM7xx BMC.
>>
>> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>> > ---
>> > arch/arm/mach-npcm/npcm7xx.c | 2 ++
>> > 1 file changed, 2 insertions(+)
>>
>> > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
>> > index 5f7cd88103ef..c5f77d854c4f 100644
>> > --- a/arch/arm/mach-npcm/npcm7xx.c
>> > +++ b/arch/arm/mach-npcm/npcm7xx.c
>> > @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
>> > DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
>> > .atag_offset = 0x100,
>> > .dt_compat = npcm7xx_dt_match,
>> > + .l2c_aux_val = 0x0,
>> > + .l2c_aux_mask = ~0x0,
>>
>> You need to limit this to the specific bit(s) you want to set and verify
>> that
>> the l2c driver does not already manage that bit appropriately and that it
>> can
>> not be specified via the dtsi.
>
>
> Do you mean that I need to specify it the same as been done in V7?
> because when I run with the above l2c_aux_val and l2c_aux_mask parameters I
> get the same result.
>
> Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to the
> DT_MACHINE_START
> the L2C cache does not initialize.
>>
>>
>> We discussed this a little while ago with Rob here:
>> https://www.spinics.net/lists/arm-kernel/msg613372.html
>
>
> Sorry in this link I see only Russel king comment regarding the L2C
I'm not sure what the outcome is, and the patch changelog doesn't
explain what the patch is for, so I've not applied it. If you need the
patch for correct operation, please resend it with a proper changelog
comment explaining why it's needed and why you ended up not setting
any of the bits.
The last email in that thread mentions
L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-04-05 12:54 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 12:54 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
>
> On 16 March 2018 at 07:52, Brendan Higgins <brendanhiggins@google.com>
> wrote:
>>
>> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>>
>> > Enable L2 Cache in Nuvoton NPCM7xx BMC.
>>
>> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>> > ---
>> > arch/arm/mach-npcm/npcm7xx.c | 2 ++
>> > 1 file changed, 2 insertions(+)
>>
>> > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
>> > index 5f7cd88103ef..c5f77d854c4f 100644
>> > --- a/arch/arm/mach-npcm/npcm7xx.c
>> > +++ b/arch/arm/mach-npcm/npcm7xx.c
>> > @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
>> > DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
>> > .atag_offset = 0x100,
>> > .dt_compat = npcm7xx_dt_match,
>> > + .l2c_aux_val = 0x0,
>> > + .l2c_aux_mask = ~0x0,
>>
>> You need to limit this to the specific bit(s) you want to set and verify
>> that
>> the l2c driver does not already manage that bit appropriately and that it
>> can
>> not be specified via the dtsi.
>
>
> Do you mean that I need to specify it the same as been done in V7?
> because when I run with the above l2c_aux_val and l2c_aux_mask parameters I
> get the same result.
>
> Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to the
> DT_MACHINE_START
> the L2C cache does not initialize.
>>
>>
>> We discussed this a little while ago with Rob here:
>> https://www.spinics.net/lists/arm-kernel/msg613372.html
>
>
> Sorry in this link I see only Russel king comment regarding the L2C
I'm not sure what the outcome is, and the patch changelog doesn't
explain what the patch is for, so I've not applied it. If you need the
patch for correct operation, please resend it with a proper changelog
comment explaining why it's needed and why you ended up not setting
any of the bits.
The last email in that thread mentions
L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
2018-04-05 12:54 ` Arnd Bergmann
(?)
(?)
@ 2018-04-05 16:56 ` Tomer Maimon
2018-04-05 20:42 ` Arnd Bergmann
-1 siblings, 1 reply; 23+ messages in thread
From: Tomer Maimon @ 2018-04-05 16:56 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Brendan Higgins, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
[-- Attachment #1: Type: text/plain, Size: 2532 bytes --]
On 5 April 2018 at 15:54, Arnd Bergmann <arnd@arndb.de> wrote:
> On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com>
> wrote:
> >
> >
> > On 16 March 2018 at 07:52, Brendan Higgins <brendanhiggins@google.com>
> > wrote:
> >>
> >> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <tmaimon77@gmail.com>
> wrote:
> >>
> >> > Enable L2 Cache in Nuvoton NPCM7xx BMC.
> >>
> >> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> >> > ---
> >> > arch/arm/mach-npcm/npcm7xx.c | 2 ++
> >> > 1 file changed, 2 insertions(+)
> >>
> >> > diff --git a/arch/arm/mach-npcm/npcm7xx.c
> b/arch/arm/mach-npcm/npcm7xx.c
> >> > index 5f7cd88103ef..c5f77d854c4f 100644
> >> > --- a/arch/arm/mach-npcm/npcm7xx.c
> >> > +++ b/arch/arm/mach-npcm/npcm7xx.c
> >> > @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
> >> > DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> >> > .atag_offset = 0x100,
> >> > .dt_compat = npcm7xx_dt_match,
> >> > + .l2c_aux_val = 0x0,
> >> > + .l2c_aux_mask = ~0x0,
> >>
> >> You need to limit this to the specific bit(s) you want to set and verify
> >> that
> >> the l2c driver does not already manage that bit appropriately and that
> it
> >> can
> >> not be specified via the dtsi.
> >
> >
> > Do you mean that I need to specify it the same as been done in V7?
> > because when I run with the above l2c_aux_val and l2c_aux_mask
> parameters I
> > get the same result.
> >
> > Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to
> the
> > DT_MACHINE_START
> > the L2C cache does not initialize.
> >>
> >>
> >> We discussed this a little while ago with Rob here:
> >> https://www.spinics.net/lists/arm-kernel/msg613372.html
> >
> >
> > Sorry in this link I see only Russel king comment regarding the L2C
>
> I'm not sure what the outcome is, and the patch changelog doesn't
> explain what the patch is for, so I've not applied it. If you need the
> patch for correct operation, please resend it with a proper changelog
> comment explaining why it's needed and why you ended up not setting
> any of the bits.
>
Sorry for not explain it better,
It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the
DT_MACHINE_START
to enable the L2 Cache.
>
> The last email in that thread mentions
> L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
>
No it is not require this is why I added:
.l2c_aux_val = 0x0,
.l2c_aux_mask = ~0x0,
>
> Arnd
>
Can I resend it on Sunday?
Thanks,
Tomer
[-- Attachment #2: Type: text/html, Size: 5631 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
2018-04-05 16:56 ` Tomer Maimon
2018-04-05 20:42 ` Arnd Bergmann
@ 2018-04-05 20:42 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 20:42 UTC (permalink / raw)
To: Tomer Maimon
Cc: Brendan Higgins, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Thu, Apr 5, 2018 at 6:56 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
> On 5 April 2018 at 15:54, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the
> DT_MACHINE_START
> to enable the L2 Cache.
>>
>>
>> The last email in that thread mentions
>> L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
>
>
> No it is not require this is why I added:
> .l2c_aux_val = 0x0,
> .l2c_aux_mask = ~0x0,
>
> Can I resend it on Sunday?
Yes, please resend it as soon as you have the time to improve the changelog,
no need to wait if you can do it right away. We can always merge bugfixes,
but doing it earlier rather than later is better.
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-04-05 20:42 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 20:42 UTC (permalink / raw)
To: Tomer Maimon
Cc: Brendan Higgins, Patrick Venture, Avi Fishman, Joel Stanley,
OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM,
Nancy Yuen
On Thu, Apr 5, 2018 at 6:56 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
> On 5 April 2018 at 15:54, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the
> DT_MACHINE_START
> to enable the L2 Cache.
>>
>>
>> The last email in that thread mentions
>> L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
>
>
> No it is not require this is why I added:
> .l2c_aux_val = 0x0,
> .l2c_aux_mask = ~0x0,
>
> Can I resend it on Sunday?
Yes, please resend it as soon as you have the time to improve the changelog,
no need to wait if you can do it right away. We can always merge bugfixes,
but doing it earlier rather than later is better.
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx
@ 2018-04-05 20:42 ` Arnd Bergmann
0 siblings, 0 replies; 23+ messages in thread
From: Arnd Bergmann @ 2018-04-05 20:42 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 5, 2018 at 6:56 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
> On 5 April 2018 at 15:54, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the
> DT_MACHINE_START
> to enable the L2 Cache.
>>
>>
>> The last email in that thread mentions
>> L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
>
>
> No it is not require this is why I added:
> .l2c_aux_val = 0x0,
> .l2c_aux_mask = ~0x0,
>
> Can I resend it on Sunday?
Yes, please resend it as soon as you have the time to improve the changelog,
no need to wait if you can do it right away. We can always merge bugfixes,
but doing it earlier rather than later is better.
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-04-05 20:42 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-15 23:10 [PATCH v1 0/2] arm: npcm: Modify NPCM7XX machine code Tomer Maimon
2018-03-15 23:10 ` Tomer Maimon
2018-03-15 23:10 ` [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC Tomer Maimon
2018-03-15 23:10 ` Tomer Maimon
2018-03-16 5:56 ` Brendan Higgins
2018-03-16 5:56 ` Brendan Higgins
2018-03-16 5:56 ` Brendan Higgins
2018-04-05 12:51 ` Arnd Bergmann
2018-04-05 12:51 ` Arnd Bergmann
2018-04-05 12:51 ` Arnd Bergmann
2018-03-15 23:10 ` [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx Tomer Maimon
2018-03-15 23:10 ` Tomer Maimon
2018-03-16 5:52 ` Brendan Higgins
2018-03-16 5:52 ` Brendan Higgins
2018-03-16 5:52 ` Brendan Higgins
2018-03-16 21:51 ` Tomer Maimon
2018-04-05 12:54 ` Arnd Bergmann
2018-04-05 12:54 ` Arnd Bergmann
2018-04-05 12:54 ` Arnd Bergmann
2018-04-05 16:56 ` Tomer Maimon
2018-04-05 20:42 ` Arnd Bergmann
2018-04-05 20:42 ` Arnd Bergmann
2018-04-05 20:42 ` Arnd Bergmann
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