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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v4 04/26] RISC-V: Use ROM base address and size from memmap
Date: Mon, 19 Mar 2018 14:18:27 -0700	[thread overview]
Message-ID: <1521494329-19546-5-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com>

Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/riscv/virt.c         | 4 ++--
 include/hw/riscv/virt.h | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0055439..0d101fc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -338,11 +338,11 @@ static void riscv_virt_board_init(MachineState *machine)
     };
 
     /* copy in the reset vector */
-    copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec));
+    copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec));
 
     /* copy in the device tree */
     qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
-    cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec),
+    cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
         s->fdt, s->fdt_size);
 
     /* create PLIC hart topology configuration string */
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 2fbe808..655e85d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,8 +23,6 @@
 #define VIRT(obj) \
     OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
 
-enum { ROM_BASE = 0x1000 };
-
 typedef struct {
     /*< private >*/
     SysBusDevice parent_obj;
-- 
2.7.0

  parent reply	other threads:[~2018-03-19 21:19 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-19 21:18 [Qemu-devel] [PATCH v4 00/26] RISC-V Post-merge spec conformance and cleanup Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 01/26] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 02/26] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 03/26] RISC-V: Make virt board description match spike Michael Clark
2018-03-19 21:18 ` Michael Clark [this message]
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 05/26] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 06/26] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 07/26] RISC-V: Remove unused class definitions Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 08/26] RISC-V: Make sure rom has space for fdt Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 09/26] RISC-V: Include intruction hex in disassembly Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 10/26] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 11/26] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 12/26] RISC-V: Update E order and I extension order Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 13/26] RISC-V: Make some header guards more specific Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 14/26] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 15/26] RISC-V: Use memory_region_is_ram in pte update Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 16/26] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 17/26] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 18/26] RISC-V: Remove braces from satp case statement Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 19/26] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 20/26] RISC-V: vectored traps are optional Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 21/26] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 22/26] RISC-V: Remove support for adhoc X_COP interrupt Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 23/26] RISC-V: Convert cpu definition towards future model Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 24/26] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 25/26] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-03-19 21:18 ` [Qemu-devel] [PATCH v4 26/26] RISC-V: Fix riscv_isa_string memory size bug Michael Clark
2018-03-20 11:51   ` Peter Maydell
2018-03-20 20:51     ` Philippe Mathieu-Daudé
2018-03-20 21:35       ` [Qemu-devel] [patches] " Michael Clark

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