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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Yunwei Zhang <yunwei.zhang@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
Date: Mon, 19 Mar 2018 22:08:32 +0000	[thread overview]
Message-ID: <152149731253.3594.2771103883469825452@mail.alporthouse.com> (raw)
In-Reply-To: <1521496208-26132-1-git-send-email-yunwei.zhang@intel.com>

Quoting Yunwei Zhang (2018-03-19 21:50:07)
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
> 
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg for INSTDONE.
> 
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
> 
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 43 ++++++++++++++++++++++++++++++++--
>  1 file changed, 41 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a2b1e9e..bc8fed7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>         }
>  }
>  
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
> +{
> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);

INTEL_SSEU(dev_priv);

> +       u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
> +                                  sizeof(sseu->slice_mask));
> +       u32 subslice = find_last_bit((unsigned long *)&(sseu->subslice_mask[slice]),
> +                                     sizeof(sseu->subslice_mask[0]));

You seem to have mispelt fls().

Or send a patch to convert find_last_bit() into fls() for known small
sizes.
-Chris
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  parent reply	other threads:[~2018-03-19 22:08 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-19 21:50 [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Yunwei Zhang
2018-03-19 21:50 ` [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads Yunwei Zhang
2018-03-19 22:09   ` Chris Wilson
2018-03-19 22:08 ` Chris Wilson [this message]
2018-03-19 22:34 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads Patchwork
2018-03-19 22:50 ` ✗ Fi.CI.BAT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-03-22 18:05 [PATCH 1/2] " Yunwei Zhang
2018-03-23  8:50 ` Mika Kuoppala
2018-03-22 16:59 Yunwei Zhang
2018-03-14 23:22 Yunwei Zhang

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