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From: xiangxia.m.yue@gmail.com
To: wenzhuo.lu@intel.com, konstantin.ananyev@intel.com,
	beilei.xing@intel.com, wei.dai@intel.com
Cc: dev@dpdk.org, Tonghao Zhang <xiangxia.m.yue@gmail.com>
Subject: [PATCH v3 2/5] net/ixgbe: set the ITR via configuration.
Date: Thu, 22 Mar 2018 06:01:55 -0700	[thread overview]
Message-ID: <1521723718-93761-3-git-send-email-xiangxia.m.yue@gmail.com> (raw)
In-Reply-To: <1521723718-93761-1-git-send-email-xiangxia.m.yue@gmail.com>

From: Tonghao Zhang <xiangxia.m.yue@gmail.com>

With this patch, the ITR value of ixgbe PF, can be
configured as wanted.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 5 +----
 drivers/net/ixgbe/ixgbe_rxtx.c   | 3 ++-
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 495e72c..14296ea 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -60,9 +60,6 @@
  */
 #define IXGBE_FC_LO    0x40
 
-/* Default minimum inter-interrupt interval for EITR configuration */
-#define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
-
 /* Timer value included in XOFF frames. */
 #define IXGBE_FC_PAUSE 0x680
 
@@ -5856,7 +5853,7 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
 		break;
 	}
 	IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
-			IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
+			ixgbe_calc_itr_interval(RTE_LIBRTE_IXGBE_ITR_INTERVAL));
 
 	/* set up to autoclear timer, and the vectors */
 	mask = IXGBE_EIMS_ENABLE_MASK;
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9bc8462..cb51f46 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -4695,7 +4695,8 @@ void __attribute__((cold))
 		 * at most 500us latency for a single RSC aggregation.
 		 */
 		eitr &= ~IXGBE_EITR_ITR_INT_MASK;
-		eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
+		eitr |= ixgbe_calc_itr_interval(RTE_LIBRTE_IXGBE_ITR_INTERVAL);
+		eitr |= IXGBE_EITR_CNT_WDIS;
 
 		IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
 		IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
-- 
1.8.3.1

  parent reply	other threads:[~2018-03-22 13:02 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22 13:01 [PATCH v3 0/5] ixgbe: fix bugs or just improve xiangxia.m.yue
2018-03-22 13:01 ` [PATCH v3 1/5] net/ixgbevf: set the inter-interrupt interval for EITR xiangxia.m.yue
2018-04-17 11:00   ` Ferruh Yigit
2018-04-18  1:01     ` Tonghao Zhang
2018-04-18 16:10       ` Ferruh Yigit
2018-04-26 13:14         ` Zhang, Qi Z
2018-04-26 13:54           ` Tonghao Zhang
2018-03-22 13:01 ` xiangxia.m.yue [this message]
2018-03-22 13:01 ` [PATCH v3 3/5] net/ixgbe: write disable to ITR counter xiangxia.m.yue
2018-03-22 13:01 ` [PATCH v3 4/5] net/ixgbevf: save IXGBE_VTEIMS to intr->mask for performance xiangxia.m.yue
2018-03-22 13:01 ` [PATCH v3 5/5] net/ixgbe: remove the unnecessary call rte_intr_enable xiangxia.m.yue
  -- strict thread matches above, loose matches on Subject: below --
2018-02-05  0:51 [PATCH v3 0/5] ixgbe: fix bugs or just improve xiangxia.m.yue
2018-02-05  0:51 ` [PATCH v3 2/5] net/ixgbe: set the ITR via configuration xiangxia.m.yue

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