[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Timur Tabi]

Two data structures are declared as static globals but are intended to
be per-TLMM.  Move them into the msm_pinctrl structure and initialize
them at runtime.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 44 ++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index ad80a17c9990..fa4e94fedb8c 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -58,7 +58,10 @@ struct msm_pinctrl {
 	struct device *dev;
 	struct pinctrl_dev *pctrl;
 	struct gpio_chip chip;
+	struct pinctrl_desc desc;
 	struct notifier_block restart_nb;
+
+	struct irq_chip irq_chip;
 	int irq;
 
 	raw_spinlock_t lock;
@@ -390,13 +393,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
 	.pin_config_group_set	= msm_config_group_set,
 };
 
-static struct pinctrl_desc msm_pinctrl_desc = {
-	.pctlops = &msm_pinctrl_ops,
-	.pmxops = &msm_pinmux_ops,
-	.confops = &msm_pinconf_ops,
-	.owner = THIS_MODULE,
-};
-
 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
 	const struct msm_pingroup *g;
@@ -776,15 +772,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 	return 0;
 }
 
-static struct irq_chip msm_gpio_irq_chip = {
-	.name           = "msmgpio",
-	.irq_mask       = msm_gpio_irq_mask,
-	.irq_unmask     = msm_gpio_irq_unmask,
-	.irq_ack        = msm_gpio_irq_ack,
-	.irq_set_type   = msm_gpio_irq_set_type,
-	.irq_set_wake   = msm_gpio_irq_set_wake,
-};
-
 static void msm_gpio_irq_handler(struct irq_desc *desc)
 {
 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@@ -877,6 +864,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 	chip->of_node = pctrl->dev->of_node;
 	chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
 
+	pctrl->irq_chip.name = "msmgpio";
+	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
+	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
+	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
+	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
+	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
+
 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
 	if (ret) {
 		dev_err(pctrl->dev, "Failed register gpiochip\n");
@@ -898,7 +892,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 	}
 
 	ret = gpiochip_irqchip_add(chip,
-				   &msm_gpio_irq_chip,
+				   &pctrl->irq_chip,
 				   0,
 				   handle_edge_irq,
 				   IRQ_TYPE_NONE);
@@ -908,7 +902,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 		return -ENOSYS;
 	}
 
-	gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
+	gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
 				     msm_gpio_irq_handler);
 
 	return 0;
@@ -979,11 +973,15 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 		return pctrl->irq;
 	}
 
-	msm_pinctrl_desc.name = dev_name(&pdev->dev);
-	msm_pinctrl_desc.pins = pctrl->soc->pins;
-	msm_pinctrl_desc.npins = pctrl->soc->npins;
-	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
-					     pctrl);
+	pctrl->desc.owner = THIS_MODULE;
+	pctrl->desc.pctlops = &msm_pinctrl_ops;
+	pctrl->desc.pmxops = &msm_pinmux_ops;
+	pctrl->desc.confops = &msm_pinconf_ops;
+	pctrl->desc.name = dev_name(&pdev->dev);
+	pctrl->desc.pins = pctrl->soc->pins;
+	pctrl->desc.npins = pctrl->soc->npins;
+
+	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
 	if (IS_ERR(pctrl->pctrl)) {
 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 		return PTR_ERR(pctrl->pctrl);
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Timur Tabi]

Two data structures are declared as static globals but are intended to
be per-TLMM.  Move them into the msm_pinctrl structure and initialize
them at runtime.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 44 ++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index ad80a17c9990..fa4e94fedb8c 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -58,7 +58,10 @@ struct msm_pinctrl {
 	struct device *dev;
 	struct pinctrl_dev *pctrl;
 	struct gpio_chip chip;
+	struct pinctrl_desc desc;
 	struct notifier_block restart_nb;
+
+	struct irq_chip irq_chip;
 	int irq;
 
 	raw_spinlock_t lock;
@@ -390,13 +393,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
 	.pin_config_group_set	= msm_config_group_set,
 };
 
-static struct pinctrl_desc msm_pinctrl_desc = {
-	.pctlops = &msm_pinctrl_ops,
-	.pmxops = &msm_pinmux_ops,
-	.confops = &msm_pinconf_ops,
-	.owner = THIS_MODULE,
-};
-
 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
 	const struct msm_pingroup *g;
@@ -776,15 +772,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 	return 0;
 }
 
-static struct irq_chip msm_gpio_irq_chip = {
-	.name           = "msmgpio",
-	.irq_mask       = msm_gpio_irq_mask,
-	.irq_unmask     = msm_gpio_irq_unmask,
-	.irq_ack        = msm_gpio_irq_ack,
-	.irq_set_type   = msm_gpio_irq_set_type,
-	.irq_set_wake   = msm_gpio_irq_set_wake,
-};
-
 static void msm_gpio_irq_handler(struct irq_desc *desc)
 {
 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@@ -877,6 +864,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 	chip->of_node = pctrl->dev->of_node;
 	chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
 
+	pctrl->irq_chip.name = "msmgpio";
+	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
+	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
+	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
+	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
+	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
+
 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
 	if (ret) {
 		dev_err(pctrl->dev, "Failed register gpiochip\n");
@@ -898,7 +892,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 	}
 
 	ret = gpiochip_irqchip_add(chip,
-				   &msm_gpio_irq_chip,
+				   &pctrl->irq_chip,
 				   0,
 				   handle_edge_irq,
 				   IRQ_TYPE_NONE);
@@ -908,7 +902,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 		return -ENOSYS;
 	}
 
-	gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
+	gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
 				     msm_gpio_irq_handler);
 
 	return 0;
@@ -979,11 +973,15 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 		return pctrl->irq;
 	}
 
-	msm_pinctrl_desc.name = dev_name(&pdev->dev);
-	msm_pinctrl_desc.pins = pctrl->soc->pins;
-	msm_pinctrl_desc.npins = pctrl->soc->npins;
-	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
-					     pctrl);
+	pctrl->desc.owner = THIS_MODULE;
+	pctrl->desc.pctlops = &msm_pinctrl_ops;
+	pctrl->desc.pmxops = &msm_pinmux_ops;
+	pctrl->desc.confops = &msm_pinconf_ops;
+	pctrl->desc.name = dev_name(&pdev->dev);
+	pctrl->desc.pins = pctrl->soc->pins;
+	pctrl->desc.npins = pctrl->soc->npins;
+
+	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
 	if (IS_ERR(pctrl->pctrl)) {
 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 		return PTR_ERR(pctrl->pctrl);
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but
fill in the data only for available GPIOs.  This ensures that the driver
cannot accidentally access an unavailable GPIO.

The pinctrl-msm driver also scans the "gpios" property to determine
which pins are available, and ensure that only those can be registered.

Support for QCOM8001 is removed as there is no longer any firmware that
implements it.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 114 +++++++++++++++++++++------------
 1 file changed, 73 insertions(+), 41 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c3e18b..1dfbe42dd895 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -30,9 +30,7 @@
 
 #include "pinctrl-msm.h"
 
-static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
-
-/* A reasonable limit to the number of GPIOS */
+/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
 #define MAX_GPIOS	256
 
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
@@ -40,77 +38,111 @@
 
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	struct msm_pinctrl_soc_data *pinctrl;
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
 	u32 num_gpios;
+	unsigned int avail_gpios; /* The number of GPIOs we support */
+	u8 gpios[MAX_GPIOS];      /* An array of supported GPIOs */
 	int ret;
 
 	/* Query the number of GPIOs from ACPI */
 	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
 		return ret;
 	}
-
 	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+		return -ENODEV;
+	}
+
+	/* The number of GPIOs in the approved list */
+	ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "missing 'gpios' property\n");
+		return ret;
+	}
+	/*
+	 * The number of available GPIOs should be non-zero, and no
+	 * more than the total number of GPIOS.
+	 */
+	if (!ret || ret > num_gpios) {
+		dev_err(&pdev->dev, "invalid 'gpios' property\n");
 		return -ENODEV;
 	}
+	avail_gpios = ret;
 
+	ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
+					    avail_gpios);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "could not read list of GPIOs\n");
+		return ret;
+	}
+
+	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
 	pins = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
 	groups = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
 
-	if (!pins || !groups || !names)
+	if (!pinctrl || !pins || !groups || !names)
 		return -ENOMEM;
 
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number, but nothing else.
+	 */
 	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposed as GPIOs. */
+	for (i = 0; i < avail_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
-	qdf2xxx_pinctrl.pins = pins;
-	qdf2xxx_pinctrl.groups = groups;
-	qdf2xxx_pinctrl.npins = num_gpios;
-	qdf2xxx_pinctrl.ngroups = num_gpios;
-	qdf2xxx_pinctrl.ngpios = num_gpios;
+	pinctrl->pins = pins;
+	pinctrl->groups = groups;
+	pinctrl->npins = num_gpios;
+	pinctrl->ngroups = num_gpios;
+	pinctrl->ngpios = num_gpios;
 
-	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
+	return msm_pinctrl_probe(pdev, pinctrl);
 }
 
 static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
+	{"QCOM8002"},
 	{},
 };
 MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but
fill in the data only for available GPIOs.  This ensures that the driver
cannot accidentally access an unavailable GPIO.

The pinctrl-msm driver also scans the "gpios" property to determine
which pins are available, and ensure that only those can be registered.

Support for QCOM8001 is removed as there is no longer any firmware that
implements it.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 114 +++++++++++++++++++++------------
 1 file changed, 73 insertions(+), 41 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c3e18b..1dfbe42dd895 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -30,9 +30,7 @@
 
 #include "pinctrl-msm.h"
 
-static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
-
-/* A reasonable limit to the number of GPIOS */
+/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
 #define MAX_GPIOS	256
 
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
@@ -40,77 +38,111 @@
 
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	struct msm_pinctrl_soc_data *pinctrl;
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
 	u32 num_gpios;
+	unsigned int avail_gpios; /* The number of GPIOs we support */
+	u8 gpios[MAX_GPIOS];      /* An array of supported GPIOs */
 	int ret;
 
 	/* Query the number of GPIOs from ACPI */
 	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
 		return ret;
 	}
-
 	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+		return -ENODEV;
+	}
+
+	/* The number of GPIOs in the approved list */
+	ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "missing 'gpios' property\n");
+		return ret;
+	}
+	/*
+	 * The number of available GPIOs should be non-zero, and no
+	 * more than the total number of GPIOS.
+	 */
+	if (!ret || ret > num_gpios) {
+		dev_err(&pdev->dev, "invalid 'gpios' property\n");
 		return -ENODEV;
 	}
+	avail_gpios = ret;
 
+	ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
+					    avail_gpios);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "could not read list of GPIOs\n");
+		return ret;
+	}
+
+	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
 	pins = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
 	groups = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
 
-	if (!pins || !groups || !names)
+	if (!pinctrl || !pins || !groups || !names)
 		return -ENOMEM;
 
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number, but nothing else.
+	 */
 	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposed as GPIOs. */
+	for (i = 0; i < avail_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
-	qdf2xxx_pinctrl.pins = pins;
-	qdf2xxx_pinctrl.groups = groups;
-	qdf2xxx_pinctrl.npins = num_gpios;
-	qdf2xxx_pinctrl.ngroups = num_gpios;
-	qdf2xxx_pinctrl.ngpios = num_gpios;
+	pinctrl->pins = pins;
+	pinctrl->groups = groups;
+	pinctrl->npins = num_gpios;
+	pinctrl->ngroups = num_gpios;
+	pinctrl->ngpios = num_gpios;
 
-	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
+	return msm_pinctrl_probe(pdev, pinctrl);
 }
 
 static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
+	{"QCOM8002"},
 	{},
 };
 MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Linus Walleij]

On Sat, Mar 24, 2018 at 12:44 AM, Timur Tabi <timur@codeaurora.org> wrote:

> Two data structures are declared as static globals but are intended to
> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
> them at runtime.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

Waiting for a review from Stephen or Bjorn on these two
patches.

Yours,
Linus Walleij

[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Linus Walleij]

On Sat, Mar 24, 2018 at 12:44 AM, Timur Tabi <timur@codeaurora.org> wrote:

> Two data structures are declared as static globals but are intended to
> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
> them at runtime.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

Waiting for a review from Stephen or Bjorn on these two
patches.

Yours,
Linus Walleij

Re: [PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Timur Tabi]

On 03/27/2018 08:33 AM, Linus Walleij wrote:
>> Two data structures are declared as static globals but are intended to
>> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
>> them at runtime.
>>
>> Signed-off-by: Timur Tabi <timur@codeaurora.org>

> Waiting for a review from Stephen or Bjorn on these two
> patches.

Stephen? Bjorn?  I really hope I don't miss the 4.17 release.  I've been 
working on these patches for months.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Timur Tabi]

On 03/27/2018 08:33 AM, Linus Walleij wrote:
>> Two data structures are declared as static globals but are intended to
>> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
>> them at runtime.
>>
>> Signed-off-by: Timur Tabi <timur@codeaurora.org>

> Waiting for a review from Stephen or Bjorn on these two
> patches.

Stephen? Bjorn?  I really hope I don't miss the 4.17 release.  I've been 
working on these patches for months.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Bjorn Andersson]

On Fri 23 Mar 16:44 PDT 2018, Timur Tabi wrote:

> Two data structures are declared as static globals but are intended to
> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
> them at runtime.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 44 ++++++++++++++++++--------------------
>  1 file changed, 21 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index ad80a17c9990..fa4e94fedb8c 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -58,7 +58,10 @@ struct msm_pinctrl {
>  	struct device *dev;
>  	struct pinctrl_dev *pctrl;
>  	struct gpio_chip chip;
> +	struct pinctrl_desc desc;
>  	struct notifier_block restart_nb;
> +
> +	struct irq_chip irq_chip;
>  	int irq;
>  
>  	raw_spinlock_t lock;
> @@ -390,13 +393,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
>  	.pin_config_group_set	= msm_config_group_set,
>  };
>  
> -static struct pinctrl_desc msm_pinctrl_desc = {
> -	.pctlops = &msm_pinctrl_ops,
> -	.pmxops = &msm_pinmux_ops,
> -	.confops = &msm_pinconf_ops,
> -	.owner = THIS_MODULE,
> -};
> -
>  static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
>  {
>  	const struct msm_pingroup *g;
> @@ -776,15 +772,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
>  	return 0;
>  }
>  
> -static struct irq_chip msm_gpio_irq_chip = {
> -	.name           = "msmgpio",
> -	.irq_mask       = msm_gpio_irq_mask,
> -	.irq_unmask     = msm_gpio_irq_unmask,
> -	.irq_ack        = msm_gpio_irq_ack,
> -	.irq_set_type   = msm_gpio_irq_set_type,
> -	.irq_set_wake   = msm_gpio_irq_set_wake,
> -};
> -
>  static void msm_gpio_irq_handler(struct irq_desc *desc)
>  {
>  	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
> @@ -877,6 +864,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
>  	chip->of_node = pctrl->dev->of_node;
>  	chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
>  
> +	pctrl->irq_chip.name = "msmgpio";
> +	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
> +	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
> +	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
> +	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
> +	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
> +
>  	ret = gpiochip_add_data(&pctrl->chip, pctrl);
>  	if (ret) {
>  		dev_err(pctrl->dev, "Failed register gpiochip\n");
> @@ -898,7 +892,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
>  	}
>  
>  	ret = gpiochip_irqchip_add(chip,
> -				   &msm_gpio_irq_chip,
> +				   &pctrl->irq_chip,
>  				   0,
>  				   handle_edge_irq,
>  				   IRQ_TYPE_NONE);
> @@ -908,7 +902,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
>  		return -ENOSYS;
>  	}
>  
> -	gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
> +	gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
>  				     msm_gpio_irq_handler);
>  
>  	return 0;
> @@ -979,11 +973,15 @@ int msm_pinctrl_probe(struct platform_device *pdev,
>  		return pctrl->irq;
>  	}
>  
> -	msm_pinctrl_desc.name = dev_name(&pdev->dev);
> -	msm_pinctrl_desc.pins = pctrl->soc->pins;
> -	msm_pinctrl_desc.npins = pctrl->soc->npins;
> -	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
> -					     pctrl);
> +	pctrl->desc.owner = THIS_MODULE;
> +	pctrl->desc.pctlops = &msm_pinctrl_ops;
> +	pctrl->desc.pmxops = &msm_pinmux_ops;
> +	pctrl->desc.confops = &msm_pinconf_ops;
> +	pctrl->desc.name = dev_name(&pdev->dev);
> +	pctrl->desc.pins = pctrl->soc->pins;
> +	pctrl->desc.npins = pctrl->soc->npins;
> +
> +	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
>  	if (IS_ERR(pctrl->pctrl)) {
>  		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
>  		return PTR_ERR(pctrl->pctrl);
> -- 
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
> 

[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Bjorn Andersson]

On Fri 23 Mar 16:44 PDT 2018, Timur Tabi wrote:

> Two data structures are declared as static globals but are intended to
> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
> them at runtime.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 44 ++++++++++++++++++--------------------
>  1 file changed, 21 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index ad80a17c9990..fa4e94fedb8c 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -58,7 +58,10 @@ struct msm_pinctrl {
>  	struct device *dev;
>  	struct pinctrl_dev *pctrl;
>  	struct gpio_chip chip;
> +	struct pinctrl_desc desc;
>  	struct notifier_block restart_nb;
> +
> +	struct irq_chip irq_chip;
>  	int irq;
>  
>  	raw_spinlock_t lock;
> @@ -390,13 +393,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
>  	.pin_config_group_set	= msm_config_group_set,
>  };
>  
> -static struct pinctrl_desc msm_pinctrl_desc = {
> -	.pctlops = &msm_pinctrl_ops,
> -	.pmxops = &msm_pinmux_ops,
> -	.confops = &msm_pinconf_ops,
> -	.owner = THIS_MODULE,
> -};
> -
>  static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
>  {
>  	const struct msm_pingroup *g;
> @@ -776,15 +772,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
>  	return 0;
>  }
>  
> -static struct irq_chip msm_gpio_irq_chip = {
> -	.name           = "msmgpio",
> -	.irq_mask       = msm_gpio_irq_mask,
> -	.irq_unmask     = msm_gpio_irq_unmask,
> -	.irq_ack        = msm_gpio_irq_ack,
> -	.irq_set_type   = msm_gpio_irq_set_type,
> -	.irq_set_wake   = msm_gpio_irq_set_wake,
> -};
> -
>  static void msm_gpio_irq_handler(struct irq_desc *desc)
>  {
>  	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
> @@ -877,6 +864,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
>  	chip->of_node = pctrl->dev->of_node;
>  	chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
>  
> +	pctrl->irq_chip.name = "msmgpio";
> +	pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
> +	pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
> +	pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
> +	pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
> +	pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
> +
>  	ret = gpiochip_add_data(&pctrl->chip, pctrl);
>  	if (ret) {
>  		dev_err(pctrl->dev, "Failed register gpiochip\n");
> @@ -898,7 +892,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
>  	}
>  
>  	ret = gpiochip_irqchip_add(chip,
> -				   &msm_gpio_irq_chip,
> +				   &pctrl->irq_chip,
>  				   0,
>  				   handle_edge_irq,
>  				   IRQ_TYPE_NONE);
> @@ -908,7 +902,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
>  		return -ENOSYS;
>  	}
>  
> -	gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
> +	gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
>  				     msm_gpio_irq_handler);
>  
>  	return 0;
> @@ -979,11 +973,15 @@ int msm_pinctrl_probe(struct platform_device *pdev,
>  		return pctrl->irq;
>  	}
>  
> -	msm_pinctrl_desc.name = dev_name(&pdev->dev);
> -	msm_pinctrl_desc.pins = pctrl->soc->pins;
> -	msm_pinctrl_desc.npins = pctrl->soc->npins;
> -	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
> -					     pctrl);
> +	pctrl->desc.owner = THIS_MODULE;
> +	pctrl->desc.pctlops = &msm_pinctrl_ops;
> +	pctrl->desc.pmxops = &msm_pinmux_ops;
> +	pctrl->desc.confops = &msm_pinconf_ops;
> +	pctrl->desc.name = dev_name(&pdev->dev);
> +	pctrl->desc.pins = pctrl->soc->pins;
> +	pctrl->desc.npins = pctrl->soc->npins;
> +
> +	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
>  	if (IS_ERR(pctrl->pctrl)) {
>  		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
>  		return PTR_ERR(pctrl->pctrl);
> -- 
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
> 

Re: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Bjorn Andersson]

On Fri 23 Mar 16:45 PDT 2018, Timur Tabi wrote:

> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
> 
> To implement the sparse GPIO map, we register all of the GPIOs, but
> fill in the data only for available GPIOs.  This ensures that the driver
> cannot accidentally access an unavailable GPIO.
> 
> The pinctrl-msm driver also scans the "gpios" property to determine
> which pins are available, and ensure that only those can be registered.
> 
> Support for QCOM8001 is removed as there is no longer any firmware that
> implements it.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 114 +++++++++++++++++++++------------
>  1 file changed, 73 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> index bb3ce5c3e18b..1dfbe42dd895 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> @@ -30,9 +30,7 @@
>  
>  #include "pinctrl-msm.h"
>  
> -static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
> -
> -/* A reasonable limit to the number of GPIOS */
> +/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
>  #define MAX_GPIOS	256
>  
>  /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
> @@ -40,77 +38,111 @@
>  
>  static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>  {
> +	struct msm_pinctrl_soc_data *pinctrl;
>  	struct pinctrl_pin_desc *pins;
>  	struct msm_pingroup *groups;
>  	char (*names)[NAME_SIZE];
>  	unsigned int i;
>  	u32 num_gpios;
> +	unsigned int avail_gpios; /* The number of GPIOs we support */
> +	u8 gpios[MAX_GPIOS];      /* An array of supported GPIOs */
>  	int ret;
>  
>  	/* Query the number of GPIOs from ACPI */
>  	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
>  	if (ret < 0) {
> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
> +		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
>  		return ret;
>  	}
> -
>  	if (!num_gpios || num_gpios > MAX_GPIOS) {
> -		dev_warn(&pdev->dev, "invalid num-gpios property\n");
> +		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
> +		return -ENODEV;
> +	}
> +
> +	/* The number of GPIOs in the approved list */
> +	ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "missing 'gpios' property\n");
> +		return ret;
> +	}
> +	/*
> +	 * The number of available GPIOs should be non-zero, and no
> +	 * more than the total number of GPIOS.
> +	 */
> +	if (!ret || ret > num_gpios) {
> +		dev_err(&pdev->dev, "invalid 'gpios' property\n");
>  		return -ENODEV;
>  	}
> +	avail_gpios = ret;
>  
> +	ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
> +					    avail_gpios);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "could not read list of GPIOs\n");
> +		return ret;
> +	}
> +
> +	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
>  	pins = devm_kcalloc(&pdev->dev, num_gpios,
>  		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
>  	groups = devm_kcalloc(&pdev->dev, num_gpios,
>  		sizeof(struct msm_pingroup), GFP_KERNEL);
> -	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
> +	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
>  
> -	if (!pins || !groups || !names)
> +	if (!pinctrl || !pins || !groups || !names)
>  		return -ENOMEM;
>  
> +	/*
> +	 * Initialize the array.  GPIOs not listed in the 'gpios' array
> +	 * still need a number, but nothing else.
> +	 */
>  	for (i = 0; i < num_gpios; i++) {
> -		snprintf(names[i], NAME_SIZE, "gpio%u", i);
> -
>  		pins[i].number = i;
> -		pins[i].name = names[i];
> -
> -		groups[i].npins = 1;
> -		groups[i].name = names[i];
>  		groups[i].pins = &pins[i].number;
> +	}
>  
> -		groups[i].ctl_reg = 0x10000 * i;
> -		groups[i].io_reg = 0x04 + 0x10000 * i;
> -		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
> -		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
> -		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
> -
> -		groups[i].mux_bit = 2;
> -		groups[i].pull_bit = 0;
> -		groups[i].drv_bit = 6;
> -		groups[i].oe_bit = 9;
> -		groups[i].in_bit = 0;
> -		groups[i].out_bit = 1;
> -		groups[i].intr_enable_bit = 0;
> -		groups[i].intr_status_bit = 0;
> -		groups[i].intr_target_bit = 5;
> -		groups[i].intr_target_kpss_val = 1;
> -		groups[i].intr_raw_status_bit = 4;
> -		groups[i].intr_polarity_bit = 1;
> -		groups[i].intr_detection_bit = 2;
> -		groups[i].intr_detection_width = 2;
> +	/* Populate the entries that are meant to be exposed as GPIOs. */
> +	for (i = 0; i < avail_gpios; i++) {
> +		unsigned int gpio = gpios[i];
> +
> +		groups[gpio].npins = 1;
> +		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
> +		pins[gpio].name = names[i];
> +		groups[gpio].name = names[i];
> +
> +		groups[gpio].ctl_reg = 0x10000 * gpio;
> +		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
> +		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
> +		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
> +		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
> +
> +		groups[gpio].mux_bit = 2;
> +		groups[gpio].pull_bit = 0;
> +		groups[gpio].drv_bit = 6;
> +		groups[gpio].oe_bit = 9;
> +		groups[gpio].in_bit = 0;
> +		groups[gpio].out_bit = 1;
> +		groups[gpio].intr_enable_bit = 0;
> +		groups[gpio].intr_status_bit = 0;
> +		groups[gpio].intr_target_bit = 5;
> +		groups[gpio].intr_target_kpss_val = 1;
> +		groups[gpio].intr_raw_status_bit = 4;
> +		groups[gpio].intr_polarity_bit = 1;
> +		groups[gpio].intr_detection_bit = 2;
> +		groups[gpio].intr_detection_width = 2;
>  	}
>  
> -	qdf2xxx_pinctrl.pins = pins;
> -	qdf2xxx_pinctrl.groups = groups;
> -	qdf2xxx_pinctrl.npins = num_gpios;
> -	qdf2xxx_pinctrl.ngroups = num_gpios;
> -	qdf2xxx_pinctrl.ngpios = num_gpios;
> +	pinctrl->pins = pins;
> +	pinctrl->groups = groups;
> +	pinctrl->npins = num_gpios;
> +	pinctrl->ngroups = num_gpios;
> +	pinctrl->ngpios = num_gpios;
>  
> -	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
> +	return msm_pinctrl_probe(pdev, pinctrl);
>  }
>  
>  static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
> -	{"QCOM8001"},
> +	{"QCOM8002"},

I presume you're okay with not being able to run mainline on your old
firmware?

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Bjorn Andersson]

On Fri 23 Mar 16:45 PDT 2018, Timur Tabi wrote:

> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
> 
> To implement the sparse GPIO map, we register all of the GPIOs, but
> fill in the data only for available GPIOs.  This ensures that the driver
> cannot accidentally access an unavailable GPIO.
> 
> The pinctrl-msm driver also scans the "gpios" property to determine
> which pins are available, and ensure that only those can be registered.
> 
> Support for QCOM8001 is removed as there is no longer any firmware that
> implements it.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 114 +++++++++++++++++++++------------
>  1 file changed, 73 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> index bb3ce5c3e18b..1dfbe42dd895 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> @@ -30,9 +30,7 @@
>  
>  #include "pinctrl-msm.h"
>  
> -static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
> -
> -/* A reasonable limit to the number of GPIOS */
> +/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
>  #define MAX_GPIOS	256
>  
>  /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
> @@ -40,77 +38,111 @@
>  
>  static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>  {
> +	struct msm_pinctrl_soc_data *pinctrl;
>  	struct pinctrl_pin_desc *pins;
>  	struct msm_pingroup *groups;
>  	char (*names)[NAME_SIZE];
>  	unsigned int i;
>  	u32 num_gpios;
> +	unsigned int avail_gpios; /* The number of GPIOs we support */
> +	u8 gpios[MAX_GPIOS];      /* An array of supported GPIOs */
>  	int ret;
>  
>  	/* Query the number of GPIOs from ACPI */
>  	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
>  	if (ret < 0) {
> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
> +		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
>  		return ret;
>  	}
> -
>  	if (!num_gpios || num_gpios > MAX_GPIOS) {
> -		dev_warn(&pdev->dev, "invalid num-gpios property\n");
> +		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
> +		return -ENODEV;
> +	}
> +
> +	/* The number of GPIOs in the approved list */
> +	ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "missing 'gpios' property\n");
> +		return ret;
> +	}
> +	/*
> +	 * The number of available GPIOs should be non-zero, and no
> +	 * more than the total number of GPIOS.
> +	 */
> +	if (!ret || ret > num_gpios) {
> +		dev_err(&pdev->dev, "invalid 'gpios' property\n");
>  		return -ENODEV;
>  	}
> +	avail_gpios = ret;
>  
> +	ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
> +					    avail_gpios);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "could not read list of GPIOs\n");
> +		return ret;
> +	}
> +
> +	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
>  	pins = devm_kcalloc(&pdev->dev, num_gpios,
>  		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
>  	groups = devm_kcalloc(&pdev->dev, num_gpios,
>  		sizeof(struct msm_pingroup), GFP_KERNEL);
> -	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
> +	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
>  
> -	if (!pins || !groups || !names)
> +	if (!pinctrl || !pins || !groups || !names)
>  		return -ENOMEM;
>  
> +	/*
> +	 * Initialize the array.  GPIOs not listed in the 'gpios' array
> +	 * still need a number, but nothing else.
> +	 */
>  	for (i = 0; i < num_gpios; i++) {
> -		snprintf(names[i], NAME_SIZE, "gpio%u", i);
> -
>  		pins[i].number = i;
> -		pins[i].name = names[i];
> -
> -		groups[i].npins = 1;
> -		groups[i].name = names[i];
>  		groups[i].pins = &pins[i].number;
> +	}
>  
> -		groups[i].ctl_reg = 0x10000 * i;
> -		groups[i].io_reg = 0x04 + 0x10000 * i;
> -		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
> -		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
> -		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
> -
> -		groups[i].mux_bit = 2;
> -		groups[i].pull_bit = 0;
> -		groups[i].drv_bit = 6;
> -		groups[i].oe_bit = 9;
> -		groups[i].in_bit = 0;
> -		groups[i].out_bit = 1;
> -		groups[i].intr_enable_bit = 0;
> -		groups[i].intr_status_bit = 0;
> -		groups[i].intr_target_bit = 5;
> -		groups[i].intr_target_kpss_val = 1;
> -		groups[i].intr_raw_status_bit = 4;
> -		groups[i].intr_polarity_bit = 1;
> -		groups[i].intr_detection_bit = 2;
> -		groups[i].intr_detection_width = 2;
> +	/* Populate the entries that are meant to be exposed as GPIOs. */
> +	for (i = 0; i < avail_gpios; i++) {
> +		unsigned int gpio = gpios[i];
> +
> +		groups[gpio].npins = 1;
> +		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
> +		pins[gpio].name = names[i];
> +		groups[gpio].name = names[i];
> +
> +		groups[gpio].ctl_reg = 0x10000 * gpio;
> +		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
> +		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
> +		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
> +		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
> +
> +		groups[gpio].mux_bit = 2;
> +		groups[gpio].pull_bit = 0;
> +		groups[gpio].drv_bit = 6;
> +		groups[gpio].oe_bit = 9;
> +		groups[gpio].in_bit = 0;
> +		groups[gpio].out_bit = 1;
> +		groups[gpio].intr_enable_bit = 0;
> +		groups[gpio].intr_status_bit = 0;
> +		groups[gpio].intr_target_bit = 5;
> +		groups[gpio].intr_target_kpss_val = 1;
> +		groups[gpio].intr_raw_status_bit = 4;
> +		groups[gpio].intr_polarity_bit = 1;
> +		groups[gpio].intr_detection_bit = 2;
> +		groups[gpio].intr_detection_width = 2;
>  	}
>  
> -	qdf2xxx_pinctrl.pins = pins;
> -	qdf2xxx_pinctrl.groups = groups;
> -	qdf2xxx_pinctrl.npins = num_gpios;
> -	qdf2xxx_pinctrl.ngroups = num_gpios;
> -	qdf2xxx_pinctrl.ngpios = num_gpios;
> +	pinctrl->pins = pins;
> +	pinctrl->groups = groups;
> +	pinctrl->npins = num_gpios;
> +	pinctrl->ngroups = num_gpios;
> +	pinctrl->ngpios = num_gpios;
>  
> -	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
> +	return msm_pinctrl_probe(pdev, pinctrl);
>  }
>  
>  static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
> -	{"QCOM8001"},
> +	{"QCOM8002"},

I presume you're okay with not being able to run mainline on your old
firmware?

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

Re: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

On 4/2/18 11:07 PM, Bjorn Andersson wrote:
> I presume you're okay with not being able to run mainline on your old
> firmware?

Yes, that firmware is very old now, and it doesn't even support our 
current production silicon.

> 
> Acked-by: Bjorn Andersson<bjorn.andersson@linaro.org>

Thank you.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

On 4/2/18 11:07 PM, Bjorn Andersson wrote:
> I presume you're okay with not being able to run mainline on your old
> firmware?

Yes, that firmware is very old now, and it doesn't even support our 
current production silicon.

> 
> Acked-by: Bjorn Andersson<bjorn.andersson@linaro.org>

Thank you.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Stephen Boyd]

Quoting Timur Tabi (2018-03-23 16:44:59)
> Two data structures are declared as static globals but are intended to
> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
> them at runtime.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

[PATCH 1/2] pinctrl: qcom: remove static globals to allow multiple TLMMs

[Stephen Boyd]

Quoting Timur Tabi (2018-03-23 16:44:59)
> Two data structures are declared as static globals but are intended to
> be per-TLMM.  Move them into the msm_pinctrl structure and initialize
> them at runtime.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Stephen Boyd]

Quoting Timur Tabi (2018-03-23 16:45:00)
> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
> 
> To implement the sparse GPIO map, we register all of the GPIOs, but
> fill in the data only for available GPIOs.  This ensures that the driver
> cannot accidentally access an unavailable GPIO.
> 
> The pinctrl-msm driver also scans the "gpios" property to determine
> which pins are available, and ensure that only those can be registered.
> 
> Support for QCOM8001 is removed as there is no longer any firmware that
> implements it.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Stephen Boyd]

Quoting Timur Tabi (2018-03-23 16:45:00)
> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
> 
> To implement the sparse GPIO map, we register all of the GPIOs, but
> fill in the data only for available GPIOs.  This ensures that the driver
> cannot accidentally access an unavailable GPIO.
> 
> The pinctrl-msm driver also scans the "gpios" property to determine
> which pins are available, and ensure that only those can be registered.
> 
> Support for QCOM8001 is removed as there is no longer any firmware that
> implements it.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>