[U-Boot] [PATCH 00/36] rockchip: clean up board file for rockchip SoCs

[U-Boot] [PATCH 00/36] rockchip: clean up board file for rockchip SoCs

[Kever Yang]

This patch set is to clean code for board related file, after this
patch set, all the Rockchip SoCs will share the same tpl/spl/board
file and very similar boot flow.

tpl.c: target for init DDR sdram, only internal sram available,
       prefer tpl to be as simple as possible and then back to backrom;
spl.c: target for load U-Boot and Trust(option) image and boot into
       next stage, init DDR sdram if no tpl exist;
board.c: use for U-Boot proper for all Rockchip SoCs.

We prefer to reduce boot flow option like RETURN_TO_BROM in SPL/TPL,
and will enable trust(ATF or OPTEE) support for all SoCs with TrustZone,
will share scripts for link and firmware package.

Only rk3399 is using spl+Trust/U-Boot and all other SoCs should go to
tpl+spl_Trust/U-Boot mode now.



Kever Yang (36):
  rockchip: rk3288: move configure_l2ctlr back to rk3288
  rockchip: add common MACRO to enable sys arch timer
  rockchip: enable SYS_NS16550 for all SoCs by default
  rockchip: defconfig: remove CONFIG_SYS_NS16550
  rockchip: add STIMER_BASE for all SoCs
  rockchip: add IRAM_START_ADDR for all SoCs
  rockchip: rk3328: add BOOT_MODE_REG for rk3328
  rockchip: rk322x: remove use rockchip timer as sys timer
  rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay
  rockchip: rk322x: prepare to use common board file
  rockchip: defconfig enable sysreset for rk3229 spl
  rockchip: rk3036: sdram: use udelay instead of rockchip_udelay
  rockchip: rk3036: remove sys timer
  rockchip: rk3036: prepare to use commong board file
  rockchip: declare sdram_init() in common header
  rockchip: sdram-common: add api to pass dram info to trust os
  rockchip: sdram_common: add common dram_init_banksize
  rockchip: rk3188: remove rockchip timer as sys timer
  rockchip: rk3188: prepare to use common board file
  rockchip: rk3128: remove rockchip timer as systimer
  rockchip: rk3128: prepare use common board file
  rockchip: dts: rk3288: update spl-boot-order
  rockchip: rk3288: remove rockchip timer for sys timer
  armv8: add timer_get_boot_us() for generic timer
  rockchip: rk3288: prepare to use common board file
  rockchip: rk1108: remove rockchip timer for sys timer
  rockchip: rv1108: prepare to use common board file
  rockchip: rk3328: prepare to use common board file
  rockchip: rk3368: prepare to use common board file
  rockchip: lion-rk3368: remove rockchip timer
  rockchip: rk3399: prepare to use common board file
  rockchip: remove rk_timer
  rockchip: dts: rk3399-firefly: enable uart2 in spl
  rockchip: spl-boot-order: do not enable with OF_PLATDATA
  rockchip: declear boot_devices in bootrom.h
  rockchip: add common board file for rockchip platform

 arch/arm/Kconfig                                   |   1 +
 arch/arm/cpu/armv8/generic_timer.c                 |   6 +
 arch/arm/dts/rk3288-phycore-rdk.dts                |   6 +-
 arch/arm/dts/rk3288-veyron.dtsi                    |   6 +-
 arch/arm/dts/rk3399-firefly.dts                    |   1 +
 arch/arm/include/asm/arch-rockchip/bootrom.h       |   2 +
 arch/arm/include/asm/arch-rockchip/sdram_common.h  |   4 +
 arch/arm/include/asm/arch-rockchip/sys_proto.h     |  25 +-
 arch/arm/mach-rockchip/Kconfig                     |  38 ++-
 arch/arm/mach-rockchip/Makefile                    |  23 +-
 arch/arm/mach-rockchip/{rk3128-board.c => board.c} |  93 +++---
 arch/arm/mach-rockchip/rk3036-board.c              | 104 -------
 arch/arm/mach-rockchip/rk3036/Makefile             |   2 +-
 .../{rk3036-board-spl.c => rk3036/rk3036.c}        |  41 +--
 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c       |  33 +-
 arch/arm/mach-rockchip/rk3188-board-spl.c          | 226 --------------
 arch/arm/mach-rockchip/rk3188-board.c              |  82 -----
 arch/arm/mach-rockchip/rk3188/Makefile             |   1 +
 arch/arm/mach-rockchip/rk3188/rk3188.c             |  23 ++
 arch/arm/mach-rockchip/rk322x-board.c              | 155 ----------
 arch/arm/mach-rockchip/rk322x/Makefile             |   2 +-
 .../{rk322x-board-spl.c => rk322x/rk322x.c}        |  86 ++----
 arch/arm/mach-rockchip/rk3288-board-spl.c          | 304 ------------------
 arch/arm/mach-rockchip/rk3288-board-tpl.c          |  84 -----
 arch/arm/mach-rockchip/rk3288-board.c              | 338 ---------------------
 arch/arm/mach-rockchip/rk3288/rk3288.c             | 328 +++++++++++++++++++-
 arch/arm/mach-rockchip/rk3328/rk3328.c             |  59 +++-
 arch/arm/mach-rockchip/rk3368-board-spl.c          |  73 -----
 arch/arm/mach-rockchip/rk3368-board-tpl.c          | 157 ----------
 arch/arm/mach-rockchip/rk3368/rk3368.c             | 116 ++++++-
 arch/arm/mach-rockchip/rk3399-board-spl.c          | 179 -----------
 arch/arm/mach-rockchip/rk3399-board.c              |  14 -
 arch/arm/mach-rockchip/rk3399/rk3399.c             |  86 +++++-
 arch/arm/mach-rockchip/rk_timer.c                  |  48 ---
 arch/arm/mach-rockchip/rv1108/rv1108.c             |   8 -
 arch/arm/mach-rockchip/sdram_common.c              |  84 ++++-
 arch/arm/mach-rockchip/spl-boot-order.c            |   2 +-
 arch/arm/mach-rockchip/spl.c                       | 195 ++++++++++++
 arch/arm/mach-rockchip/tpl.c                       | 111 +++++++
 board/chipspark/popmetal_rk3288/popmetal-rk3288.c  |   9 +-
 board/geekbuying/geekbox/geekbox.c                 |   5 -
 board/mqmaker/miqi_rk3288/miqi-rk3288.c            |   7 -
 board/phytec/phycore_rk3288/phycore-rk3288.c       |  45 ++-
 board/rockchip/evb_px5/evb-px5.c                   |   5 -
 board/rockchip/evb_rk3288/evb-rk3288.c             |   7 -
 .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c |   8 +
 board/rockchip/evb_rk3328/evb-rk3328.c             |  66 ----
 board/rockchip/evb_rk3399/evb-rk3399.c             |  56 ++--
 board/rockchip/evb_rv1108/evb_rv1108.c             |   6 -
 board/rockchip/fennec_rk3288/fennec-rk3288.c       |   7 -
 board/rockchip/sheep_rk3368/sheep_rk3368.c         |   5 -
 board/rockchip/tinker_rk3288/tinker-rk3288.c       |   2 +-
 board/theobroma-systems/lion_rk3368/lion_rk3368.c  |   8 -
 board/theobroma-systems/puma_rk3399/puma-rk3399.c  |  17 +-
 configs/evb-rk3128_defconfig                       |   1 -
 configs/evb-rk3229_defconfig                       |   2 +-
 configs/evb-rk3288_defconfig                       |   1 -
 configs/evb-rk3328_defconfig                       |   1 -
 configs/evb-rk3399_defconfig                       |   1 -
 configs/fennec-rk3288_defconfig                    |   1 -
 configs/firefly-rk3288_defconfig                   |   1 -
 configs/firefly-rk3399_defconfig                   |   1 -
 configs/lion-rk3368_defconfig                      |   4 -
 configs/miqi-rk3288_defconfig                      |   1 -
 configs/phycore-rk3288_defconfig                   |   1 -
 configs/popmetal-rk3288_defconfig                  |   1 -
 configs/puma-rk3399_defconfig                      |   1 -
 configs/tinker-rk3288_defconfig                    |   1 -
 configs/vyasa-rk3288_defconfig                     |   1 -
 drivers/ram/rockchip/sdram_rk322x.c                |  29 +-
 include/configs/rk3036_common.h                    |   7 -
 include/configs/rk3128_common.h                    |   6 -
 include/configs/rk3188_common.h                    |   5 -
 include/configs/rk322x_common.h                    |   4 -
 include/configs/rk3288_common.h                    |   6 -
 include/configs/rk3328_common.h                    |   2 -
 include/configs/rk3368_common.h                    |   4 -
 include/configs/rk3399_common.h                    |   4 -
 include/configs/rockchip-common.h                  |   6 +
 include/configs/rv1108_common.h                    |   8 -
 80 files changed, 1248 insertions(+), 2251 deletions(-)
 rename arch/arm/mach-rockchip/{rk3128-board.c => board.c} (63%)
 delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
 rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)
 delete mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3188-board.c
 create mode 100644 arch/arm/mach-rockchip/rk3188/rk3188.c
 delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
 rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c
 delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c
 delete mode 100644 arch/arm/mach-rockchip/rk_timer.c
 create mode 100644 arch/arm/mach-rockchip/spl.c
 create mode 100644 arch/arm/mach-rockchip/tpl.c
 create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c

-- 
1.9.1

[U-Boot] [PATCH 01/36] rockchip: rk3288: move configure_l2ctlr back to rk3288

[Kever Yang]

The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 ----------------------
 arch/arm/mach-rockchip/rk3288/rk3288.c         | 26 +++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index e428d59..3617ac2 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -7,27 +7,5 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
-#ifdef CONFIG_ROCKCHIP_RK3288
-#include <asm/armv7.h>
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-#endif /* CONFIG_ROCKCHIP_RK3288 */
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index acc3b79..1e1c6be 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -3,15 +3,39 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
+#include <asm/armv7.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
 #define GRF_SOC_CON2 0xff77024c
 
+#ifdef CONFIG_SPL_BUILD
+static void configure_l2ctlr(void)
+{
+	u32 l2ctlr;
+
+	l2ctlr = read_l2ctlr();
+	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+	/*
+	 * Data RAM write latency: 2 cycles
+	 * Data RAM read latency: 2 cycles
+	 * Data RAM setup latency: 1 cycle
+	 * Tag RAM write latency: 1 cycle
+	 * Tag RAM read latency: 1 cycle
+	 * Tag RAM setup latency: 1 cycle
+	 */
+	l2ctlr |= (1 << 3 | 1 << 0);
+	write_l2ctlr(l2ctlr);
+}
+#endif
+
 int arch_cpu_init(void)
 {
 	/* We do some SoC one time setting here. */
-
+#ifdef CONFIG_SPL_BUILD
+	configure_l2ctlr();
+#else
 	/* Use rkpwm by default */
 	rk_setreg(GRF_SOC_CON2, 1 << 0);
 
-- 
1.9.1

[U-Boot] [PATCH 02/36] rockchip: add common MACRO to enable sys arch timer

[Kever Yang]

All rockchip SoCs can use ARM arch timer, let's enable it in
common header file

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rk3368_common.h   | 2 --
 include/configs/rk3399_common.h   | 2 --
 include/configs/rockchip-common.h | 4 ++++
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 10f643f..a7fe4ca 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define COUNTER_FREQUENCY               24000000
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index d700bf2..fe8c675 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -17,8 +17,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define COUNTER_FREQUENCY               24000000
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 26d41b5..24651ce 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -8,6 +8,10 @@
 #define _ROCKCHIP_COMMON_H_
 #include <linux/sizes.h>
 
+#define COUNTER_FREQUENCY               24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK	24000000
+
 #ifndef CONFIG_SPL_BUILD
 
 /* First try to boot from SD (index 0), then eMMC (index 1) */
-- 
1.9.1

[U-Boot] [PATCH 03/36] rockchip: enable SYS_NS16550 for all SoCs by default

[Kever Yang]

All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/Kconfig                  | 1 +
 arch/arm/mach-rockchip/Kconfig    | 1 -
 include/configs/rk3036_common.h   | 3 ---
 include/configs/rk3128_common.h   | 2 --
 include/configs/rk3188_common.h   | 2 --
 include/configs/rk322x_common.h   | 1 -
 include/configs/rk3288_common.h   | 2 --
 include/configs/rk3328_common.h   | 2 --
 include/configs/rk3368_common.h   | 2 --
 include/configs/rk3399_common.h   | 2 --
 include/configs/rockchip-common.h | 2 ++
 include/configs/rv1108_common.h   | 3 ---
 12 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2c52ff0..3e9a80d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1167,6 +1167,7 @@ config ARCH_ROCKCHIP
 	select DM_PWM
 	select DM_REGULATOR
 	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select SYS_NS16550
 	imply CMD_FASTBOOT
 	imply FASTBOOT
 	imply FAT_WRITE
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0adaed4..007cb22 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
 	imply SPL_SERIAL_SUPPORT
 	imply TPL_SERIAL_SUPPORT
 	select DEBUG_UART_BOARD_INIT
-	select SYS_NS16550
 	help
 	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
 	  into a big and little cluster with 4 cores each) Cortex-A53 including
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f39a272..c5ec864 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 #define CONFIG_SPL_STACK		0x10081fff
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index bd8019c..c593f18 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -19,8 +19,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 94f8cda..30c150e 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
 #endif
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 7f9c7fb..832f037 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -18,7 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 #define CONFIG_SPL_STACK		0x10088000
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 78595b8..44d5c2a 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -19,8 +19,6 @@
 #define	CONFIG_SYS_TIMER_BASE		0xff810020 /* TIMER7 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #endif
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 7018668..ce650c8 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -13,8 +13,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index a7fe4ca..866383d 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00280000
 
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index fe8c675..53691e5 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -17,8 +17,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff8effff
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 24651ce..4062480 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -12,6 +12,8 @@
 #define CONFIG_SYS_ARCH_TIMER
 #define CONFIG_SYS_HZ_CLOCK	24000000
 
+#define CONFIG_SYS_NS16550_MEM32
+
 #ifndef CONFIG_SPL_BUILD
 
 /* First try to boot from SD (index 0), then eMMC (index 1) */
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 349c53c..cd204e9 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x10350020
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)
-- 
1.9.1

[U-Boot] [PATCH 04/36] rockchip: defconfig: remove CONFIG_SYS_NS16550

[Kever Yang]

We have enable NS16550 in Kconfig, do not need enable at defconfig

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 configs/evb-rk3128_defconfig      | 1 -
 configs/evb-rk3229_defconfig      | 1 -
 configs/evb-rk3288_defconfig      | 1 -
 configs/evb-rk3328_defconfig      | 1 -
 configs/evb-rk3399_defconfig      | 1 -
 configs/fennec-rk3288_defconfig   | 1 -
 configs/firefly-rk3288_defconfig  | 1 -
 configs/firefly-rk3399_defconfig  | 1 -
 configs/miqi-rk3288_defconfig     | 1 -
 configs/phycore-rk3288_defconfig  | 1 -
 configs/popmetal-rk3288_defconfig | 1 -
 configs/puma-rk3399_defconfig     | 1 -
 configs/tinker-rk3288_defconfig   | 1 -
 configs/vyasa-rk3288_defconfig    | 1 -
 14 files changed, 14 deletions(-)

diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index e7414c9..367c654 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -33,7 +33,6 @@ CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 5ec9788..96afda8 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -45,7 +45,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0x11030000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 7ba7178..b8189fd 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 266d699..3fb1cfc 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -43,7 +43,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0xFF130000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index b5ae073..7e3e97d 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -55,7 +55,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 11112ca..0b6e8b9 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index adb6b5d..dc856b0 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 03d0324..ed30652 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -57,7 +57,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index a2e58a7..c62158a 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index bd698f5..8e4e04d 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 0d85349..2beee6e 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index a8b4bac..8ff73be 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -80,7 +80,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xFF180000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index f8ff916..1c28817 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -66,7 +66,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 4c76041..a15c65f 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -60,7 +60,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-- 
1.9.1

[U-Boot] [PATCH 05/36] rockchip: add STIMER_BASE for all SoCs

[Kever Yang]

STIMER is can only access in secure mode if the SoCs supports trust,
and it locate in alive power domain, as the source of ARM arch/generic
timer, we add a base addr for all SoCs so that we can init with a common
function.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 007cb22..5dfe452 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
 	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
 	  according to the value from this register.
 
+config ROCKCHIP_STIMER_BASE
+	hex "Rockchip Secure timer base address"
+	default 0xff220020 if ROCKCHIP_PX30
+	default 0x200440a0 if ROCKCHIP_RK3036
+	default 0x2000e000 if ROCKCHIP_RK3066
+	default 0x20018020 if ROCKCHIP_RK3126
+	default 0x200440a0 if ROCKCHIP_RK3128
+	default 0x2000e000 if ROCKCHIP_RK3188
+	default 0x110d0020 if ROCKCHIP_RK322X
+	default 0xff810020 if ROCKCHIP_RK3288
+	default 0xff1d0020 if ROCKCHIP_RK3328
+	default 0xff830020 if ROCKCHIP_RK3368
+	default 0xff8680a0 if ROCKCHIP_RK3399
+	default 0x10350020 if ROCKCHIP_RV1108
+	default 0
+	help
+	  The secure timer inited in SPL/TPL in secure word, ARM generic timer
+	  works after this timer work.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
 	hex "Size of IRAM reserved in SPL"
 	default 0
-- 
1.9.1

[U-Boot] [PATCH 06/36] rockchip: add IRAM_START_ADDR for all SoCs

[Kever Yang]

We add this for get the location for boot device of bootrom.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 5dfe452..98bf935 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -209,6 +209,23 @@ config ROCKCHIP_STIMER_BASE
 	  The secure timer inited in SPL/TPL in secure word, ARM generic timer
 	  works after this timer work.
 
+config ROCKCHIP_IRAM_START_ADDR
+	hex "Rockchip Secure timer base address"
+	default 0xff0e0000 if ROCKCHIP_PX30
+	default 0x10080000 if ROCKCHIP_RK3036
+	default 0x10080000 if ROCKCHIP_RK3128
+	default 0x10080000 if ROCKCHIP_RK3188
+	default 0x10080000 if ROCKCHIP_RK322X
+	default 0xff700000 if ROCKCHIP_RK3288
+	default 0xff091000 if ROCKCHIP_RK3328
+	default 0xff8c0000 if ROCKCHIP_RK3368
+	default 0xff8c0000 if ROCKCHIP_RK3399
+	default 0x10080000 if ROCKCHIP_RV1108
+	default 0
+	help
+	  The IRAM start addr is to locate variant of the boot device from
+	  bootrom.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
 	hex "Size of IRAM reserved in SPL"
 	default 0
-- 
1.9.1

[U-Boot] [PATCH 07/36] rockchip: rk3328: add BOOT_MODE_REG for rk3328

[Kever Yang]

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 98bf935..892d51e 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -182,6 +182,7 @@ config ROCKCHIP_BOOT_MODE_REG
 	default 0x20004040 if ROCKCHIP_RK3188
 	default 0x110005c8 if ROCKCHIP_RK322X
 	default 0xff730094 if ROCKCHIP_RK3288
+	default 0xff1005c8 if ROCKCHIP_RK3328
 	default 0xff738200 if ROCKCHIP_RK3368
 	default 0xff320300 if ROCKCHIP_RK3399
 	default 0x10300580 if ROCKCHIP_RV1108
-- 
1.9.1

[U-Boot] [PATCH 08/36] rockchip: rk322x: remove use rockchip timer as sys timer

[Kever Yang]

We can use arch timer instead of rockchip timer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rk322x_common.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 832f037..29e222a 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -14,9 +14,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
-- 
1.9.1

[U-Boot] [PATCH 09/36] rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay

[Kever Yang]

Do not need to use rockchip_udelay after we can use systimer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index cc3138b..c4da000 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -17,7 +17,6 @@
 #include <asm/arch/grf_rk322x.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdram_rk322x.h>
-#include <asm/arch/timer.h>
 #include <asm/arch/uart.h>
 #include <asm/arch/sdram_common.h>
 #include <asm/types.h>
@@ -97,26 +96,26 @@ void phy_pctrl_reset(struct rk322x_cru *cru,
 			1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
 			1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
 
-	rockchip_udelay(10);
+	udelay(10);
 
 	rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
 						  1 << DDRPHY_SRST_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 
 	rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
 						  1 << DDRCTRL_SRST_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 
 	clrbits_le32(&ddr_phy->ddrphy_reg[0],
 		     SOFT_RESET_MASK << SOFT_RESET_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 	setbits_le32(&ddr_phy->ddrphy_reg[0],
 		     SOFT_DERESET_ANALOG);
-	rockchip_udelay(5);
+	udelay(5);
 	setbits_le32(&ddr_phy->ddrphy_reg[0],
 		     SOFT_DERESET_DIGITAL);
 
-	rockchip_udelay(1);
+	udelay(1);
 }
 
 void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq)
@@ -155,7 +154,7 @@ static void send_command(struct rk322x_ddr_pctl *pctl,
 			 u32 rank, u32 cmd, u32 arg)
 {
 	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
-	rockchip_udelay(1);
+	udelay(1);
 	while (readl(&pctl->mcmd) & START_CMD)
 		;
 }
@@ -168,7 +167,7 @@ static void memory_init(struct chan_info *chan,
 
 	if (dramtype == DDR3) {
 		send_command(pctl, 3, DESELECT_CMD, 0);
-		rockchip_udelay(1);
+		udelay(1);
 		send_command(pctl, 3, PREA_CMD, 0);
 		send_command(pctl, 3, MRS_CMD,
 			     (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@@ -197,17 +196,17 @@ static void memory_init(struct chan_info *chan,
 			     (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 			     (0 & LPDDR23_OP_MASK) <<
 			     LPDDR23_OP_SHIFT);
-		rockchip_udelay(10);
+		udelay(10);
 		send_command(pctl, 3, MRS_CMD,
 			     (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 			     (0xff & LPDDR23_OP_MASK) <<
 			     LPDDR23_OP_SHIFT);
-		rockchip_udelay(1);
+		udelay(1);
 		send_command(pctl, 3, MRS_CMD,
 			     (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 			     (0xff & LPDDR23_OP_MASK) <<
 			     LPDDR23_OP_SHIFT);
-		rockchip_udelay(1);
+		udelay(1);
 		send_command(pctl, 3, MRS_CMD,
 			     (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 			     (sdram_params->phy_timing.mr[1] &
@@ -244,7 +243,7 @@ static u32 data_training(struct chan_info *chan)
 			DQS_SQU_CAL_SEL_CS0);
 	setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START);
 
-	rockchip_udelay(30);
+	udelay(30);
 	ret = readl(&ddr_phy->ddrphy_reg[0xff]);
 
 	clrbits_le32(&ddr_phy->ddrphy_reg[2],
@@ -368,9 +367,9 @@ static void phy_softreset(struct dram_info *dram)
 
 	writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]);
 	clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2);
-	rockchip_udelay(1);
+	udelay(1);
 	setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2);
-	rockchip_udelay(5);
+	udelay(5);
 	setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3);
 	writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]);
 }
-- 
1.9.1

[U-Boot] [PATCH 10/36] rockchip: rk322x: prepare to use common board file

[Kever Yang]

Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk322x-board.c              | 155 ---------------------
 arch/arm/mach-rockchip/rk322x/Makefile             |   2 +-
 .../{rk322x-board-spl.c => rk322x/rk322x.c}        |  86 ++++--------
 3 files changed, 29 insertions(+), 214 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
 rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)

diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
deleted file mode 100644
index 8642a90..0000000
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/boot_mode.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-#include <asm/arch/grf_rk322x.h>
-	/* Enable early UART2 channel 1 on the RK322x */
-#define GRF_BASE	0x11000000
-	struct rk322x_grf * const grf = (void *)GRF_BASE;
-	enum {
-		GPIO1B2_SHIFT		= 4,
-		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
-		GPIO1B2_GPIO		= 0,
-		GPIO1B2_UART21_SIN,
-
-		GPIO1B1_SHIFT		= 2,
-		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
-		GPIO1B1_GPIO            = 0,
-		GPIO1B1_UART1_SOUT,
-		GPIO1B1_UART21_SOUT,
-	};
-	enum {
-		CON_IOMUX_UART2SEL_SHIFT= 8,
-		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
-		CON_IOMUX_UART2SEL_2	= 0,
-		CON_IOMUX_UART2SEL_21,
-	};
-
-	rk_clrsetreg(&grf->gpio1b_iomux,
-		     GPIO1B1_MASK | GPIO1B2_MASK,
-		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-	/* Set channel C as UART2 input */
-	rk_clrsetreg(&grf->con_iomux,
-		     CON_IOMUX_UART2SEL_MASK,
-		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
-
-	/*
-	* The integrated macphy is enabled by default, disable it
-	* for saving power consuming.
-	*/
-	rk_clrsetreg(&grf->macphy_con[0],
-		     MACPHY_CFG_ENABLE_MASK,
-		     0 << MACPHY_CFG_ENABLE_SHIFT);
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = 0x8400000;
-	/* Reserve 0x200000 for OPTEE */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-				+ gd->bd->bi_dram[0].size + 0x200000;
-	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-				+ gd->ram_size - gd->bd->bi_dram[1].start;
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk322x_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk322x_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
-int fb_set_reboot_flag(void)
-{
-	struct rk322x_grf *grf;
-
-	printf("Setting reboot to fastboot flag ...\n");
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	/* Set boot mode to fastboot */
-	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile
index ecb3e8d..89b0fed 100644
--- a/arch/arm/mach-rockchip/rk322x/Makefile
+++ b/arch/arm/mach-rockchip/rk322x/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-
 obj-y += clk_rk322x.o
+obj-y += rk322x.o
 obj-y += syscon_rk322x.o
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
similarity index 51%
rename from arch/arm/mach-rockchip/rk322x-board-spl.c
rename to arch/arm/mach-rockchip/rk322x/rk322x.c
index 206abfa..98b6ec3 100644
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
@@ -1,32 +1,41 @@
 /*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/bootrom.h>
-#include <asm/arch/cru_rk322x.h>
-#include <asm/arch/grf_rk322x.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
+#include <asm/arch/grf_rk322x.h>
 
-u32 spl_boot_device(void)
+#define GRF_BASE	0x11000000
+#define CRU_MISC_CON	0x110e0134
+#define SGRF_DDR_CON0	0x10150000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
+};
+
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
 {
-	return BOOT_DEVICE_MMC1;
-}
-DECLARE_GLOBAL_DATA_PTR;
+	static struct rk322x_grf * const grf = (void *)GRF_BASE;
+	/* We do some SoC one time setting here. */
 
-#define GRF_BASE	0x11000000
-#define SGRF_BASE	0x10140000
+	/* Disable the ddr secure region setting to make it non-secure */
+	rk_clrreg(SGRF_DDR_CON0, 0x4000);
+
+	/*
+	 * The integrated macphy is enabled by default, disable it
+	 * for saving power consuming.
+	 */
+	rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
+		     0 << MACPHY_CFG_ENABLE_SHIFT);
 
-#define DEBUG_UART_BASE	0x11030000
+	return 0;
+}
+#endif
 
 void board_debug_uart_init(void)
 {
@@ -34,8 +43,7 @@ void board_debug_uart_init(void)
 	enum {
 		GPIO1B2_SHIFT		= 4,
 		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
-		GPIO1B2_GPIO            = 0,
-		GPIO1B2_UART1_SIN,
+		GPIO1B2_GPIO		= 0,
 		GPIO1B2_UART21_SIN,
 
 		GPIO1B1_SHIFT		= 2,
@@ -61,41 +69,3 @@ void board_debug_uart_init(void)
 		     CON_IOMUX_UART2SEL_MASK,
 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
 }
-
-#define SGRF_DDR_CON0 0x10150000
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	printascii("SPL Init");
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-	printf("timer init done\n");
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		printf("DRAM init failed: %d\n", ret);
-		return;
-	}
-
-	/* Disable the ddr secure region setting to make it non-secure */
-	rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-- 
1.9.1

[U-Boot] [PATCH 11/36] rockchip: defconfig enable sysreset for rk3229 spl

[Kever Yang]

We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver,
which will fix missing do_reset() error in SPL build.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 configs/evb-rk3229_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 96afda8..4f1007a 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ROCKCHIP_RK322X=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_EVB_RK3229=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
 CONFIG_DEBUG_UART=y
-- 
1.9.1

[U-Boot] [PATCH 12/36] rockchip: rk3036: sdram: use udelay instead of rockchip_udelay

[Kever Yang]

We are going to remove rockchip_udelay after enable arch timer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index e5393ec..ce3f09a 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -10,7 +10,6 @@
 #include <asm/arch/grf_rk3036.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
 #include <asm/arch/uart.h>
 
 /*
@@ -346,7 +345,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
 
 	/* waiting for pll lock */
 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
-		rockchip_udelay(1);
+		udelay(1);
 
 	/* PLL enter normal-mode */
 	rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
@@ -374,25 +373,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
 			1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
 			1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
 
-	rockchip_udelay(10);
+	udelay(10);
 
 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
 						  1 << DDRPHY_SRST_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 
 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
 						  1 << DDRCTRL_SRST_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 
 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
 			0 << SOFT_RESET_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
 			3 << SOFT_RESET_SHIFT);
 
-	rockchip_udelay(1);
+	udelay(1);
 }
 
 void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
@@ -445,7 +444,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl,
 			 u32 rank, u32 cmd, u32 arg)
 {
 	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
-	rockchip_udelay(1);
+	udelay(1);
 	while (readl(&pctl->mcmd) & START_CMD)
 		;
 }
@@ -455,7 +454,7 @@ static void memory_init(struct rk3036_sdram_priv *priv)
 	struct rk3036_ddr_pctl *pctl = priv->pctl;
 
 	send_command(pctl, 3, DESELECT_CMD, 0);
-	rockchip_udelay(1);
+	udelay(1);
 	send_command(pctl, 3, PREA_CMD, 0);
 	send_command(pctl, 3, MRS_CMD,
 		     (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@@ -493,7 +492,7 @@ static void data_training(struct rk3036_sdram_priv *priv)
 	clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
 			DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
 
-	rockchip_udelay(1);
+	udelay(1);
 	while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
 		(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
 		;
-- 
1.9.1

[U-Boot] [PATCH 13/36] rockchip: rk3036: remove sys timer

[Kever Yang]

Use ARM arch timer instead.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rk3036_common.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index c5ec864..8230373 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -14,10 +14,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 #define CONFIG_SPL_STACK		0x10081fff
-- 
1.9.1

[U-Boot] [PATCH 14/36] rockchip: rk3036: prepare to use commong board file

[Kever Yang]

Move some soc spec setting into rk3036.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3036-board.c              | 104 ---------------------
 arch/arm/mach-rockchip/rk3036/Makefile             |   2 +-
 .../{rk3036-board-spl.c => rk3036/rk3036.c}        |  41 ++------
 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c       |  14 +++
 4 files changed, 24 insertions(+), 137 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
 rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)

diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
deleted file mode 100644
index a5d2571..0000000
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
-#if !CONFIG_IS_ENABLED(RAM)
-/*
- * When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
- */
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile
index 20d28f7..8a144d1 100644
--- a/arch/arm/mach-rockchip/rk3036/Makefile
+++ b/arch/arm/mach-rockchip/rk3036/Makefile
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y += clk_rk3036.o
+obj-y += rk3036.o clk_rk3036.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y += syscon_rk3036.o
diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036/rk3036.c
similarity index 50%
rename from arch/arm/mach-rockchip/rk3036-board-spl.c
rename to arch/arm/mach-rockchip/rk3036/rk3036.c
index 550e3a1..39cc43b 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
@@ -1,28 +1,22 @@
 /*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
-
-#include <common.h>
-#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/bootrom.h>
-#include <asm/arch/grf_rk3036.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
+#include <asm/arch/grf_rk3036.h>
 #define GRF_BASE	0x20008000
 
-#define DEBUG_UART_BASE	0x20068000
-
-void board_init_f(ulong dummy)
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
+{
+	return 0;
+}
+#endif
+void board_debug_uart_init(void)
 {
-#ifdef EARLY_DEBUG
 	struct rk3036_grf * const grf = (void *)GRF_BASE;
 	/*
 	 * NOTE: sd card and debug uart use same iomux in rk3036,
@@ -34,22 +28,5 @@ void board_init_f(ulong dummy)
 		     GPIO1C2_MASK << GPIO1C2_SHIFT,
 		     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
-	debug_uart_init();
-#endif
-	rockchip_timer_init();
-	sdram_init();
-
-	/* return to maskrom */
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
 
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-	/*
-	 * Function attribute is no-return
-	 * This Function never executes
-	 */
-	while (1)
-		;
 }
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index ce3f09a..a4fb3ae 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -11,6 +11,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdram_rk3036.h>
 #include <asm/arch/uart.h>
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * we can not fit the code to access the device tree in SPL
@@ -764,3 +765,16 @@ void sdram_init(void)
 	move_to_access_state(&sdram_priv);
 	dram_cfg_rbc(&sdram_priv);
 }
+
+#if !CONFIG_IS_ENABLED(RAM)
+/*
+ * When CONFIG_RAM is enabled, the dram_init() function is implemented
+ * in sdram_common.c.
+ */
+int dram_init(void)
+{
+	gd->ram_size = sdram_size();
+
+	return 0;
+}
+#endif
-- 
1.9.1

[U-Boot] [PATCH 15/36] rockchip: declare sdram_init() in common header

[Kever Yang]

We need a dedicate sdram_init() function for those SoCS not
using SPL_FRAMEWORK.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 3617ac2..7b7e336 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -7,5 +7,8 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
+#ifndef CONFIG_SPL_FRAMEWORK
+void sdram_init(void);
+#endif
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */
-- 
1.9.1

[U-Boot] [PATCH 16/36] rockchip: sdram-common: add api to pass dram info to trust os

[Kever Yang]

Trust OS decode this info like this:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
We have to set a available value, or else we get error info from
Trust OS like this:
"ERROR:   over or zero region, nr=3145987, max=10"

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 ++++
 arch/arm/mach-rockchip/sdram_common.c             | 21 +++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index fec8586..55c6b81 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg);
 
 /* Called by U-Boot board_init_r for Rockchip SoCs */
 int dram_init(void);
+
+/* Write ddr param to a known place for trustos */
+int rockchip_setup_ddr_param(struct ram_info *info);
+
 #endif
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 76dbdc8..3a71f09 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -12,6 +12,15 @@
 #include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
+struct ddr_param {
+	u32 count;
+	u32 reserved;
+	u64 bank_addr;
+	u64 bank_size;
+};
+
+#define PARAM_DRAM_INFO_OFFSET 0x2000000
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
 	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
@@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size)
 
 	return (gd->ram_top > top) ? top : gd->ram_top;
 }
+
+int rockchip_setup_ddr_param(struct ram_info *info)
+{
+	struct ddr_param *dinfo = (struct ddr_param *)CONFIG_SYS_SDRAM_BASE +
+					PARAM_DRAM_INFO_OFFSET;
+
+	dinfo->count = 1;
+	dinfo->bank_addr = info->base;
+	dinfo->bank_size = info->size;
+
+	return 0;
+}
-- 
1.9.1

[U-Boot] [PATCH 17/36] rockchip: sdram_common: add common dram_init_banksize

[Kever Yang]

dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/sdram_common.c | 63 ++++++++++++++++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 3a71f09..ff86096 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -21,13 +21,74 @@ struct ddr_param {
 
 #define PARAM_DRAM_INFO_OFFSET 0x2000000
 
+#define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
+
+struct tos_parameter_t {
+	u32 version;
+	u32 checksum;
+	struct {
+		char name[8];
+		s64 phy_addr;
+		u32 size;
+		u32 flags;
+	} tee_mem;
+	struct {
+		char name[8];
+		s64 phy_addr;
+		u32 size;
+		u32 flags;
+	} drm_mem;
+	s64 reserve[8];
+};
+
+int dram_init_banksize(void)
+{
+	size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+			 gd->ram_top);
+
+#ifdef CONFIG_ARM64
+	/* Reserve 0x200000 for ATF bl31 */
+	gd->bd->bi_dram[0].start = 0x200000;
+	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#else
+#ifdef CONFIG_SPL_OPTEE
+	struct tos_parameter_t *tos_parameter;
+
+	tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+			TRUST_PARAMETER_OFFSET);
+
+	if (tos_parameter->tee_mem.flags == 1) {
+		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+					- CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+					tos_parameter->tee_mem.size;
+		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+					+ top - gd->bd->bi_dram[1].start;
+	} else {
+		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[0].size = 0x8400000;
+		/* Reserve 32M for OPTEE with TA */
+		gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+					+ gd->bd->bi_dram[0].size + 0x2000000;
+		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+					+ top - gd->bd->bi_dram[1].start;
+	}
+#else
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#endif
+#endif
+
+	return 0;
+}
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
 	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
 	size_t chipsize_mb = 0;
 	size_t size_mb = 0;
 	u32 ch;
-
 	u32 sys_reg = readl(reg);
 	u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
 		       & SYS_REG_NUM_CH_MASK);
-- 
1.9.1

[U-Boot] [PATCH 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Kever Yang]

We use ARM arch timer instead.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rk3188_common.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 30c150e..7dddf11 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -17,9 +17,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE		0x2000e000 /* TIMER3 */
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
-- 
1.9.1

[U-Boot] [PATCH 19/36] rockchip: rk3188: prepare to use common board file

[Kever Yang]

Move SoC spec setting into rk3188.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3188-board-spl.c | 226 ------------------------------
 arch/arm/mach-rockchip/rk3188-board.c     |  82 -----------
 arch/arm/mach-rockchip/rk3188/Makefile    |   1 +
 arch/arm/mach-rockchip/rk3188/rk3188.c    |  23 +++
 4 files changed, 24 insertions(+), 308 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3188-board.c
 create mode 100644 arch/arm/mach-rockchip/rk3188/rk3188.c

diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
deleted file mode 100644
index 74771d3..0000000
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <clk.h>
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3188.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/timer.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-#include <syscon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	const void *blob = gd->fdt_blob;
-	struct udevice *dev;
-	const char *bootdev;
-	int node;
-	int ret;
-
-	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-	debug("Boot device %s\n", bootdev);
-	if (!bootdev)
-		goto fallback;
-
-	node = fdt_path_offset(blob, bootdev);
-	if (node < 0) {
-		debug("node=%d\n", node);
-		goto fallback;
-	}
-	ret = device_get_global_by_of_offset(node, &dev);
-	if (ret) {
-		debug("device@node %s/%d not found: %d\n", bootdev, node,
-		      ret);
-		goto fallback;
-	}
-	debug("Found device %s\n", dev->name);
-	switch (device_get_uclass_id(dev)) {
-	case UCLASS_SPI_FLASH:
-		return BOOT_DEVICE_SPI;
-	case UCLASS_MMC:
-		return BOOT_DEVICE_MMC1;
-	default:
-		debug("Booting from device uclass '%s' not supported\n",
-		      dev_get_uclass_name(dev));
-	}
-
-fallback:
-#endif
-	return BOOT_DEVICE_MMC1;
-}
-
-static int setup_arm_clock(void)
-{
-	struct udevice *dev;
-	struct clk clk;
-	int ret;
-
-	ret = rockchip_get_clk(&dev);
-	if (ret)
-		return ret;
-
-	clk.id = CLK_ARM;
-	ret = clk_request(dev, &clk);
-	if (ret < 0)
-		return ret;
-
-	ret = clk_set_rate(&clk, 600000000);
-
-	clk_free(&clk);
-	return ret;
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *pinctrl, *dev;
-	int ret;
-
-	/* Example code showing how to enable the debug UART on RK3188 */
-#ifdef EARLY_UART
-#include <asm/arch/grf_rk3188.h>
-	/* Enable early UART on the RK3188 */
-#define GRF_BASE	0x20008000
-	struct rk3188_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio1b_iomux,
-		     GPIO1B1_MASK << GPIO1B1_SHIFT |
-		     GPIO1B0_MASK << GPIO1B0_SHIFT,
-		     GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
-		     GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	printch('s');
-	printch('p');
-	printch('l');
-	printch('\n');
-#endif
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("Pinctrl init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-
-	setup_arm_clock();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
-	struct udevice *dev;
-	char *led_name;
-	int ret;
-
-	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
-	if (!led_name)
-		return 0;
-	ret = led_get_by_label(led_name, &dev);
-	if (ret) {
-		debug("%s: get=%d\n", __func__, ret);
-		return ret;
-	}
-	ret = led_set_on(dev, 1);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-
-void spl_board_init(void)
-{
-	struct udevice *pinctrl;
-	int ret;
-
-	ret = setup_led();
-	if (ret) {
-		debug("LED ret=%d\n", ret);
-		hang();
-	}
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-#endif
-
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		goto err;
-	}
-
-	preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-	return;
-
-err:
-	printf("spl_board_init: Error %d\n", ret);
-
-	/* No way to report error here */
-	hang();
-}
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
deleted file mode 100644
index 916d18f..0000000
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_late_init(void)
-{
-	struct rk3188_grf *grf;
-
-	setup_boot_mode();
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	if (IS_ERR(grf)) {
-		pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
-	} else {
-		/* enable noc remap to mimic legacy loaders */
-		rk_clrsetreg(&grf->soc_con0,
-			NOC_REMAP_MASK << NOC_REMAP_SHIFT,
-			NOC_REMAP_MASK << NOC_REMAP_SHIFT);
-	}
-
-	return 0;
-}
-
-int board_init(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	struct udevice *pinctrl;
-	int ret;
-
-	/*
-	 * We need to implement sdcard iomux here for the further
-	 * initialization, otherwise, it'll hit sdcard command sending
-	 * timeout exception.
-	 */
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-
-	return 0;
-err:
-	printf("board_init: Error %d\n", ret);
-
-	/* No way to report error here */
-	hang();
-
-	return -1;
-#else
-	return 0;
-#endif
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile
index 7fa0104..b3b2315 100644
--- a/arch/arm/mach-rockchip/rk3188/Makefile
+++ b/arch/arm/mach-rockchip/rk3188/Makefile
@@ -5,6 +5,7 @@
 #
 
 ifndef CONFIG_TPL_BUILD
+obj-y += rk3188.o
 obj-y += clk_rk3188.o
 obj-y += syscon_rk3188.o
 endif
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c
new file mode 100644
index 0000000..57d2abf
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk3188.h>
+
+#define GRF_BASE	0x20008000
+void board_debug_uart_init(void)
+{
+	struct rk3188_grf * const grf = (void *)GRF_BASE;
+
+	rk_clrsetreg(&grf->gpio1b_iomux,
+		     GPIO1B1_MASK << GPIO1B1_SHIFT |
+		     GPIO1B0_MASK << GPIO1B0_SHIFT,
+		     GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+		     GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+}
-- 
1.9.1

[U-Boot] [PATCH 20/36] rockchip: rk3128: remove rockchip timer as systimer

[Kever Yang]

We use ARM arch timer instead.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rk3128_common.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index c593f18..313a1e2 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -15,10 +15,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 
-- 
1.9.1

[U-Boot] [PATCH 21/36] rockchip: rk3128: prepare use common board file

[Kever Yang]

remoe rk3128 board file and move SoC spec setting into rk3128.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3128-board.c | 127 ----------------------------------
 1 file changed, 127 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3128-board.c

diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
deleted file mode 100644
index 2e8393d..0000000
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk3128.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/arch/timer.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-	int ret = 0;
-
-	rockchip_timer_init();
-
-	ret = regulators_enable_boot_on(false);
-	if (ret) {
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-		return ret;
-	}
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = 0x8400000;
-	/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-				+ gd->bd->bi_dram[0].size + 0xe00000;
-	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-				+ gd->ram_size - gd->bd->bi_dram[1].start;
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3128_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					     "rockchip,rk3128-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-						     "rockchip,rk3128-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3128_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
-int fb_set_reboot_flag(void)
-{
-	struct rk3128_grf *grf;
-
-	printf("Setting reboot to fastboot flag ...\n");
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	/* Set boot mode to fastboot */
-	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
-	return 0;
-}
-#endif
-- 
1.9.1

[U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order

[Kever Yang]

Use "uboot,spl-boot-orde" instead of "uboot,boot0".

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-----
 arch/arm/dts/rk3288-veyron.dtsi     | 6 +-----
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
index f2bb7b5..3bf8efb 100644
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/dts/rk3288-phycore-rdk.dts
@@ -53,11 +53,7 @@
 
 	chosen {
 		stdout-path = &uart2;
-	};
-
-	config {
-		u-boot,dm-pre-reloc;
-		u-boot,boot0 = &emmc;
+		u-boot,spl-boot-order = &emmc;
 	};
 
 	user_buttons: user-buttons {
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index a314058..77b9bf8 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -17,11 +17,7 @@
 
 	chosen {
 		stdout-path = &uart2;
-	};
-
-	config {
-		u-boot,dm-pre-reloc;
-		u-boot,boot0 = &spi_flash;
+		u-boot,spl-boot-order = &spi_flash;
 	};
 
 	firmware {
-- 
1.9.1

[U-Boot] [PATCH 23/36] rockchip: rk3288: remove rockchip timer for sys timer

[Kever Yang]

Use ARM arch timer instead

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rk3288_common.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 44d5c2a..8d0a0f9 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -15,10 +15,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-#define	CONFIG_SYS_TIMER_BASE		0xff810020 /* TIMER7 */
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #endif
-- 
1.9.1

[U-Boot] [PATCH 24/36] armv8: add timer_get_boot_us() for generic timer

[Kever Yang]

We need timer_get_boot_us() for boot stage if we use generic timer only.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/cpu/armv8/generic_timer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index a2dda33..d96217e 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <div64.h>
 #include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +53,11 @@ uint64_t get_ticks(void)
 	return ticks;
 }
 
+ulong timer_get_boot_us(void)
+{
+	return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
+}
+
 unsigned long usec2ticks(unsigned long usec)
 {
 	ulong ticks;
-- 
1.9.1

[U-Boot] [PATCH 25/36] rockchip: rk3288: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3288.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3288-board-spl.c          | 304 ------------------
 arch/arm/mach-rockchip/rk3288-board-tpl.c          |  84 -----
 arch/arm/mach-rockchip/rk3288-board.c              | 338 ---------------------
 arch/arm/mach-rockchip/rk3288/rk3288.c             | 304 +++++++++++++++++-
 board/chipspark/popmetal_rk3288/popmetal-rk3288.c  |   9 +-
 board/mqmaker/miqi_rk3288/miqi-rk3288.c            |   7 -
 board/phytec/phycore_rk3288/phycore-rk3288.c       |  45 ++-
 board/rockchip/evb_rk3288/evb-rk3288.c             |   7 -
 .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c |   8 +
 board/rockchip/fennec_rk3288/fennec-rk3288.c       |   7 -
 board/rockchip/tinker_rk3288/tinker-rk3288.c       |   2 +-
 11 files changed, 357 insertions(+), 758 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c
 create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
deleted file mode 100644
index f3ea624..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-#include <power/rk8xx_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	const void *blob = gd->fdt_blob;
-	struct udevice *dev;
-	const char *bootdev;
-	int node;
-	int ret;
-
-	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-	debug("Boot device %s\n", bootdev);
-	if (!bootdev)
-		goto fallback;
-
-	node = fdt_path_offset(blob, bootdev);
-	if (node < 0) {
-		debug("node=%d\n", node);
-		goto fallback;
-	}
-	ret = device_get_global_by_of_offset(node, &dev);
-	if (ret) {
-		debug("device@node %s/%d not found: %d\n", bootdev, node,
-		      ret);
-		goto fallback;
-	}
-	debug("Found device %s\n", dev->name);
-	switch (device_get_uclass_id(dev)) {
-	case UCLASS_SPI_FLASH:
-		return BOOT_DEVICE_SPI;
-	case UCLASS_MMC:
-		return BOOT_DEVICE_MMC1;
-	default:
-		debug("Booting from device uclass '%s' not supported\n",
-		      dev_get_uclass_name(dev));
-	}
-
-fallback:
-#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
-		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
-		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
-	return BOOT_DEVICE_SPI;
-#endif
-	return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
-	struct gpio_desc desc;
-	int ret;
-
-	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
-	/*
-	 * TODO(sjg at chromium.org): Pick this up from device tree or perhaps
-	 * use the EMMC_PWREN setting.
-	 */
-	ret = dm_gpio_lookup_name("D9", &desc);
-	if (ret) {
-		debug("gpio ret=%d\n", ret);
-		return ret;
-	}
-	ret = dm_gpio_request(&desc, "emmc_pwren");
-	if (ret) {
-		debug("gpio_request ret=%d\n", ret);
-		return ret;
-	}
-	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
-	if (ret) {
-		debug("gpio dir ret=%d\n", ret);
-		return ret;
-	}
-	ret = dm_gpio_set_value(&desc, 1);
-	if (ret) {
-		debug("gpio value ret=%d\n", ret);
-		return ret;
-	}
-#endif
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-static int phycore_init(void)
-{
-	struct udevice *pmic;
-	int ret;
-
-	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
-	if (ret)
-		return ret;
-
-#if defined(CONFIG_SPL_POWER_SUPPORT)
-	/* Increase USB input current to 2A */
-	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
-	if (ret)
-		return ret;
-
-	/* Close charger when USB lower then 3.26V */
-	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-#endif
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	int ret;
-
-	/* Example code showing how to enable the debug UART on RK3288 */
-#include <asm/arch/grf_rk3288.h>
-	/* Enable early UART on the RK3288 */
-#define GRF_BASE	0xff770000
-	struct rk3288_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
-		     GPIO7C6_MASK << GPIO7C6_SHIFT,
-		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
-		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	debug("\nspl:debug uart enabled in %s\n", __func__);
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-	configure_l2ctlr();
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("Pinctrl init failed: %d\n", ret);
-		return;
-	}
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
-		ret = phycore_init();
-		if (ret) {
-			debug("Failed to set up phycore power settings: %d\n",
-			      ret);
-			return;
-		}
-	}
-#endif
-
-#if !defined(CONFIG_SUPPORT_TPL)
-	debug("\nspl:init dram\n");
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-#endif
-
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
-	struct udevice *dev;
-	char *led_name;
-	int ret;
-
-	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
-	if (!led_name)
-		return 0;
-	ret = led_get_by_label(led_name, &dev);
-	if (ret) {
-		debug("%s: get=%d\n", __func__, ret);
-		return ret;
-	}
-	ret = led_set_on(dev, 1);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-
-void spl_board_init(void)
-{
-	struct udevice *pinctrl;
-	int ret;
-
-	ret = setup_led();
-
-	if (ret) {
-		debug("LED ret=%d\n", ret);
-		hang();
-	}
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-	ret = configure_emmc(pinctrl);
-	if (ret) {
-		debug("%s: Failed to set up eMMC\n", __func__);
-		goto err;
-	}
-#endif
-
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		goto err;
-	}
-
-	preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-	return;
-err:
-	printf("spl_board_init: Error %d\n", ret);
-
-	/* No way to report error here */
-	hang();
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-
-#define PMU_BASE		0xff730000
-int dram_init_banksize(void)
-{
-	struct rk3288_pmu *const pmu = (void *)PMU_BASE;
-	size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
-
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = size;
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c
deleted file mode 100644
index 150beea..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-tpl.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (C) 2017 Amarula Solutions
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define GRF_BASE		0xff770000
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-	/* Example code showing how to enable the debug UART on RK3288 */
-	/* Enable early UART on the RK3288 */
-	struct rk3288_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
-		     GPIO7C6_MASK << GPIO7C6_SHIFT,
-		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
-		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-	configure_l2ctlr();
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-void board_return_to_bootrom(void)
-{
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_BOOTROM;
-}
-
-void spl_board_init(void)
-{
-	puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
-				U_BOOT_TIME ")\n");
-}
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
deleted file mode 100644
index 1c53cca..0000000
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/qos_rk3288.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-#include <dt-bindings/clock/rk3288-cru.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int rk3288_qos_init(void)
-{
-	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
-	/* set vop qos to higher priority */
-	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
-	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
-
-	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
-				       "rockchip,rk3288-tinker"))
-	{
-		/* set isp qos to higher priority */
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
-	}
-	return 0;
-}
-
-static void rk3288_detect_reset_reason(void)
-{
-	struct rk3288_cru *cru = rockchip_get_cru();
-	const char *reason;
-
-	if (IS_ERR(cru))
-		return;
-
-	switch (cru->cru_glb_rst_st) {
-	case GLB_POR_RST:
-		reason = "POR";
-		break;
-	case FST_GLB_RST_ST:
-	case SND_GLB_RST_ST:
-		reason = "RST";
-		break;
-	case FST_GLB_TSADC_RST_ST:
-	case SND_GLB_TSADC_RST_ST:
-		reason = "THERMAL";
-		break;
-	case FST_GLB_WDT_RST_ST:
-	case SND_GLB_WDT_RST_ST:
-		reason = "WDOG";
-		break;
-	default:
-		reason = "unknown reset";
-	}
-
-	env_set("reset_reason", reason);
-
-	/*
-	 * Clear cru_glb_rst_st, so we can determine the last reset cause
-	 * for following resets.
-	 */
-	rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-	rk3288_qos_init();
-	rk3288_detect_reset_reason();
-
-	return rk_board_late_init();
-}
-
-#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-static int veyron_init(void)
-{
-	struct udevice *dev;
-	struct clk clk;
-	int ret;
-
-	ret = regulator_get_by_platname("vdd_arm", &dev);
-	if (ret) {
-		debug("Cannot set regulator name\n");
-		return ret;
-	}
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	ret = regulator_set_value(dev, 1200000);
-	if (ret)
-		return ret;
-	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
-	ret = regulator_set_value(dev, 1400000);
-	if (ret)
-		return ret;
-	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
-
-	ret = rockchip_get_clk(&clk.dev);
-	if (ret)
-		return ret;
-	clk.id = PLL_APLL;
-	ret = clk_set_rate(&clk, 1800000000);
-	if (IS_ERR_VALUE(ret))
-		return ret;
-
-	return 0;
-}
-#endif
-
-int board_init(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	struct udevice *pinctrl;
-	int ret;
-
-	/*
-	 * We need to implement sdcard iomux here for the further
-	 * initlization, otherwise, it'll hit sdcard command sending
-	 * timeout exception.
-	 */
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-
-	return 0;
-err:
-	printf("board_init: Error %d\n", ret);
-
-	/* No way to report error here */
-	hang();
-
-	return -1;
-#else
-	int ret;
-
-	/* We do some SoC one time setting here */
-	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
-		ret = veyron_init();
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-#endif
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3288_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node, phy_node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-	u32 grf_phy_offset;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	node = fdtdec_lookup_phandle(blob, node, "phys");
-	if (node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	phy_node = fdt_parent_offset(blob, node);
-	if (phy_node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	rk3288_otg_data.phy_of_node = phy_node;
-	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
-	/* find the grf node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-grf");
-	if (node <= 0) {
-		debug("Not found grf device\n");
-		return -ENODEV;
-	}
-	rk3288_otg_data.regs_phy = grf_phy_offset +
-				fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3288_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	static const struct {
-		char *name;
-		int id;
-	} clks[] = {
-		{ "osc", CLK_OSC },
-		{ "apll", CLK_ARM },
-		{ "dpll", CLK_DDR },
-		{ "cpll", CLK_CODEC },
-		{ "gpll", CLK_GENERAL },
-#ifdef CONFIG_ROCKCHIP_RK3036
-		{ "mpll", CLK_NEW },
-#else
-		{ "npll", CLK_NEW },
-#endif
-	};
-	int ret, i;
-	struct udevice *dev;
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		printf("clk-uclass not found\n");
-		return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(clks); i++) {
-		struct clk clk;
-		ulong rate;
-
-		clk.id = clks[i].id;
-		ret = clk_request(dev, &clk);
-		if (ret < 0)
-			continue;
-
-		rate = clk_get_rate(&clk);
-		printf("%s: %lu\n", clks[i].name, rate);
-
-		clk_free(&clk);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	clock, 2, 1, do_clock,
-	"display information about clocks",
-	""
-);
-
-#define GRF_SOC_CON2 0xff77024c
-
-int board_early_init_f(void)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	int ret;
-
-	/*
-	 * This init is done in SPL, but when chain-loading U-Boot SPL will
-	 * have been skipped. Allow the clock driver to check if it needs
-	 * setting up.
-	 */
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return ret;
-	}
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		return ret;
-	}
-
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		return ret;
-	}
-	rk_setreg(GRF_SOC_CON2, 1 << 0);
-
-	return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 1e1c6be..0212015 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -3,11 +3,30 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
 #include <asm/armv7.h>
 #include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/qos_rk3288.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
 
-#define GRF_SOC_CON2 0xff77024c
+#define GRF_BASE               0xff770000
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/dwmmc at ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc at ff0c0000",
+};
 
 #ifdef CONFIG_SPL_BUILD
 static void configure_l2ctlr(void)
@@ -36,7 +55,290 @@ int arch_cpu_init(void)
 #ifdef CONFIG_SPL_BUILD
 	configure_l2ctlr();
 #else
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
 	/* Use rkpwm by default */
+	rk_setreg(&grf->soc_con2, 1 << 0);
+#endif
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+		     GPIO7C6_MASK << GPIO7C6_SHIFT,
+		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+}
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static int configure_emmc(void)
+{
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
+
+	struct gpio_desc desc;
+	int ret;
+	struct udevice *pinctrl;
+
+	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
+
+	/*
+	 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
+	 * use the EMMC_PWREN setting.
+	 */
+	ret = dm_gpio_lookup_name("D9", &desc);
+	if (ret) {
+		debug("gpio ret=%d\n", ret);
+		return ret;
+	}
+	ret = dm_gpio_request(&desc, "emmc_pwren");
+	if (ret) {
+		debug("gpio_request ret=%d\n", ret);
+		return ret;
+	}
+	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	if (ret) {
+		debug("gpio dir ret=%d\n", ret);
+		return ret;
+	}
+	ret = dm_gpio_set_value(&desc, 1);
+	if (ret) {
+		debug("gpio value ret=%d\n", ret);
+		return ret;
+	}
+#endif
+	return 0;
+}
+
+int rk_spl_board_init(void)
+{
+	struct udevice *pinctrl;
+	int ret = 0;
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto err;
+	}
+	/* TODO: we may need to check boot device first */
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+	if (ret) {
+		debug("%s: Failed to set up SD card\n", __func__);
+		goto err;
+	}
+#endif
+
+	ret = configure_emmc();
+	if (ret)
+		debug("%s: Failed to set up eMMC\n", __func__);
+
+err:
+	return ret;
+}
+#endif
+#endif
+
+int rk3288_qos_init(void)
+{
+	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+	/* set vop qos to higher priority */
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+				       "rockchip,rk3288-tinker")) {
+		/* set isp qos to higher priority */
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+	}
+	return 0;
+}
+
+static void rk3288_detect_reset_reason(void)
+{
+	struct rk3288_cru *cru = rockchip_get_cru();
+	const char *reason;
+
+	if (IS_ERR(cru))
+		return;
+
+	switch (cru->cru_glb_rst_st) {
+	case GLB_POR_RST:
+		reason = "POR";
+		break;
+	case FST_GLB_RST_ST:
+	case SND_GLB_RST_ST:
+		reason = "RST";
+		break;
+	case FST_GLB_TSADC_RST_ST:
+	case SND_GLB_TSADC_RST_ST:
+		reason = "THERMAL";
+		break;
+	case FST_GLB_WDT_RST_ST:
+	case SND_GLB_WDT_RST_ST:
+		reason = "WDOG";
+		break;
+	default:
+		reason = "unknown reset";
+	}
+
+	env_set("reset_reason", reason);
+
+	/*
+	 * Clear cru_glb_rst_st, so we can determine the last reset cause
+	 * for following resets.
+	 */
+	rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
+}
+
+__weak int rk3288_board_late_init(void)
+{
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	rk3288_qos_init();
+	rk3288_detect_reset_reason();
+
+	return rk3288_board_late_init();
+}
+
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+static int veyron_init(void)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	ret = regulator_get_by_platname("vdd_arm", &dev);
+	if (ret) {
+		debug("Cannot set regulator name\n");
+		return ret;
+	}
+
+	/* Slowly raise to max CPU voltage to prevent overshoot */
+	ret = regulator_set_value(dev, 1200000);
+	if (ret)
+		return ret;
+	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+	ret = regulator_set_value(dev, 1400000);
+	if (ret)
+		return ret;
+	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+	ret = rockchip_get_clk(&clk.dev);
+	if (ret)
+		return ret;
+	clk.id = PLL_APLL;
+	ret = clk_set_rate(&clk, 1800000000);
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	return 0;
+}
+
+int rk_board_init(void)
+{
+	int ret;
+
+	/* We do some SoC one time setting here */
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+		ret = veyron_init();
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
+		    char * const argv[])
+{
+	static const struct {
+		char *name;
+		int id;
+	} clks[] = {
+		{ "osc", CLK_OSC },
+		{ "apll", CLK_ARM },
+		{ "dpll", CLK_DDR },
+		{ "cpll", CLK_CODEC },
+		{ "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+		{ "mpll", CLK_NEW },
+#else
+		{ "npll", CLK_NEW },
+#endif
+	};
+	int ret, i;
+	struct udevice *dev;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		printf("clk-uclass not found\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		struct clk clk;
+		ulong rate;
+
+		clk.id = clks[i].id;
+		ret = clk_request(dev, &clk);
+		if (ret < 0)
+			continue;
+
+		rate = clk_get_rate(&clk);
+		printf("%s: %lu\n", clks[i].name, rate);
+
+		clk_free(&clk);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clock, 2, 1, do_clock,
+	"display information about clocks",
+	""
+);
+
+#define GRF_SOC_CON2 0xff77024c
+
+int board_early_init_f(void)
+{
+	struct udevice *pinctrl;
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * This init is done in SPL, but when chain-loading U-Boot SPL will
+	 * have been skipped. Allow the clock driver to check if it needs
+	 * setting up.
+	 */
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		debug("CLK init failed: %d\n", ret);
+		return ret;
+	}
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		return ret;
+	}
+
+	/* Enable debug UART */
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+	if (ret) {
+		debug("%s: Failed to set up console UART\n", __func__);
+		return ret;
+	}
 	rk_setreg(GRF_SOC_CON2, 1 << 0);
 
 	return 0;
diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
index ed82b2b..9945f97 100644
--- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -8,16 +8,9 @@
 #include <spl.h>
 #include <asm/gpio.h>
 
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
-
 #define GPIO7A3_HUB_RST	227
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	int ret;
 
diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
index a82f0ae..846dedd 100644
--- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c
+++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
@@ -6,10 +6,3 @@
 
 #include <common.h>
 #include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard. */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
index 47b069e..175c017 100644
--- a/board/phytec/phycore_rk3288/phycore-rk3288.c
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -12,6 +12,7 @@
 #include <i2c_eeprom.h>
 #include <netdev.h>
 #include "som.h"
+#include <power/rk8xx_pmic.h>
 
 static int valid_rk3288_som(struct rk3288_som *som)
 {
@@ -27,7 +28,49 @@ static int valid_rk3288_som(struct rk3288_som *som)
 	return hw == som->bs;
 }
 
-int rk_board_late_init(void)
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_PLATDATA)
+static int phycore_init(void)
+{
+	struct udevice *pmic;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
+	if (ret)
+		return ret;
+
+#if defined(CONFIG_SPL_POWER_SUPPORT)
+	/* Increase USB input current to 2A */
+	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
+	if (ret)
+		return ret;
+
+	/* Close charger when USB lower then 3.26V */
+	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+int rk_board_init_f(void)
+{
+	int ret = 0;
+
+	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
+		ret = phycore_init();
+		if (ret) {
+			debug("Failed to set up phycore power settings: %d\n",
+			      ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+int rk3288_board_late_init(void)
 {
 	int ret;
 	struct udevice *dev;
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c
index a82f0ae..846dedd 100644
--- a/board/rockchip/evb_rk3288/evb-rk3288.c
+++ b/board/rockchip/evb_rk3288/evb-rk3288.c
@@ -6,10 +6,3 @@
 
 #include <common.h>
 #include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard. */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c b/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c
new file mode 100644
index 0000000..88b6327
--- /dev/null
+++ b/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c
@@ -0,0 +1,8 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c
index aad74ef..846dedd 100644
--- a/board/rockchip/fennec_rk3288/fennec-rk3288.c
+++ b/board/rockchip/fennec_rk3288/fennec-rk3288.c
@@ -6,10 +6,3 @@
 
 #include <common.h>
 #include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
index 790a921..5681ef1 100644
--- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -21,7 +21,7 @@ static int get_ethaddr_from_eeprom(u8 *addr)
 	return i2c_eeprom_read(dev, 0, addr, 6);
 }
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	u8 ethaddr[6];
 
-- 
1.9.1

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Kever Yang]

We use ARM arch timer instead.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/rv1108_common.h | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index cd204e9..7a9ec7b 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -13,11 +13,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-/* TIMER1,initialized by ddr initialize code */
-#define CONFIG_SYS_TIMER_BASE		0x10350020
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
-
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)
-- 
1.9.1

[U-Boot] [PATCH 27/36] rockchip: rv1108: prepare to use common board file

[Kever Yang]

Remove functions will present at common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rv1108/rv1108.c | 8 --------
 board/rockchip/evb_rv1108/evb_rv1108.c | 6 ------
 2 files changed, 14 deletions(-)

diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 868cdd5..3b6b21d 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -5,11 +5,3 @@
  */
 
 #include <common.h>
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c
index 54bd08b..0160f42 100644
--- a/board/rockchip/evb_rv1108/evb_rv1108.c
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -47,12 +47,6 @@ int mach_cpu_init(void)
 	return 0;
 }
 
-
-int board_init(void)
-{
-	return 0;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = 0x8000000;
-- 
1.9.1

[U-Boot] [PATCH 28/36] rockchip: rk3328: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3328.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3328/rk3328.c | 59 +++++++++++++++++++++++++-----
 board/rockchip/evb_rk3328/evb-rk3328.c | 66 ----------------------------------
 2 files changed, 51 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index 6764494..ddf53d5 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -5,12 +5,22 @@
  */
 
 #include <common.h>
+#include <asm/arch/bootrom.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3328.h>
+#include <asm/arch/uart.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CRU_BASE		0xFF440000
+#define GRF_BASE		0xFF100000
+#define UART2_BASE		0xFF130000
+
+#define CRU_MISC_CON		0xff440084
+#define FW_DDR_CON_REG		0xff7c0040
+
 static struct mm_region rk3328_mem_map[] = {
 	{
 		.virt = 0x0UL,
@@ -33,20 +43,53 @@ static struct mm_region rk3328_mem_map[] = {
 
 struct mm_region *mem_map = rk3328_mem_map;
 
-int dram_init_banksize(void)
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/rksdmmc at ff520000",
+	[BROM_BOOTSOURCE_SD] = "/rksdmmc at ff500000",
+};
+
+int arch_cpu_init(void)
 {
-	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
+#ifdef CONFIG_TPL_BUILD
+	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+	/* We do some SoC one time setting here. */
+
+	/* Disable the ddr secure region setting to make it non-secure */
+	rk_setreg(FW_DDR_CON_REG, 0x200);
 
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+	/* HDMI phy clock source select HDMIPHY clock out */
+	rk_clrreg(CRU_MISC_CON, 1 << 13);
 
+#endif
 	return 0;
 }
 
-int arch_cpu_init(void)
+void board_debug_uart_init(void)
 {
-	/* We do some SoC one time setting here. */
+#ifdef CONFIG_TPL_BUILD
+	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+	struct rk_uart * const uart = (void *)UART2_BASE;
 
-	return 0;
+	/* uart_sel_clk default select 24MHz */
+	writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
+
+	/* init uart baud rate 1500000 */
+	writel(0x83, &uart->lcr);
+	writel(0x1, &uart->rbr);
+	writel(0x3, &uart->lcr);
+
+	/* Enable early UART2 */
+	rk_clrsetreg(&grf->com_iomux,
+		     IOMUX_SEL_UART2_MASK,
+		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A0_SEL_MASK,
+		     GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A1_SEL_MASK,
+		     GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
+	/* enable FIFO */
+	writel(0x1, &uart->sfe);
+#endif
 }
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
index 99a73da..c8e7a3a 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -3,69 +3,3 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-#include <dwc3-uboot.h>
-#include <power/regulator.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	int ret;
-
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
-	return ret;
-}
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3328_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3328-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3328-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-
-	rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3328_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-- 
1.9.1

[U-Boot] [PATCH 29/36] rockchip: rk3368: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3368.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3368-board-spl.c         |  73 ----------
 arch/arm/mach-rockchip/rk3368-board-tpl.c         | 157 ----------------------
 arch/arm/mach-rockchip/rk3368/rk3368.c            | 116 ++++++++++++++--
 board/geekbuying/geekbox/geekbox.c                |   5 -
 board/rockchip/evb_px5/evb-px5.c                  |   5 -
 board/rockchip/sheep_rk3368/sheep_rk3368.c        |   5 -
 board/theobroma-systems/lion_rk3368/lion_rk3368.c |   8 --
 7 files changed, 106 insertions(+), 263 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c

diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
deleted file mode 100644
index 8055ae5..0000000
--- a/arch/arm/mach-rockchip/rk3368-board-spl.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/timer.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_debug_uart_init(void)
-{
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	int ret;
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	/* Set up our preloader console */
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
-		hang();
-	}
-
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
-	if (ret) {
-		pr_err("%s: failed to set up console UART\n", __func__);
-		hang();
-	}
-
-	preloader_console_init();
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c
deleted file mode 100644
index 60d5aea..0000000
--- a/arch/arm/mach-rockchip/rk3368-board-tpl.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-#include <syscon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The SPL (and also the full U-Boot stage on the RK3368) will run in
- * secure mode (i.e. EL3) and an ATF will eventually be booted before
- * starting up the operating system... so we can initialize the SGRF
- * here and rely on the ATF installing the final (secure) policy
- * later.
- */
-static inline uintptr_t sgrf_soc_con_addr(unsigned no)
-{
-	const uintptr_t SGRF_BASE =
-		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
-
-	return SGRF_BASE + sizeof(u32) * no;
-}
-
-static inline uintptr_t sgrf_busdmac_addr(unsigned no)
-{
-	const uintptr_t SGRF_BASE =
-		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
-	const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
-	const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
-
-	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
-}
-
-static void sgrf_init(void)
-{
-	struct rk3368_cru * const cru =
-		(struct rk3368_cru * const)rockchip_get_cru();
-	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
-	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
-	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
-
-	/* Set all configurable IP to 'non secure'-mode */
-	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
-	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
-	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
-
-	/*
-	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
-	 * Original comment: "ddr space set no secure mode"
-	 */
-	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
-	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
-	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
-
-	/* Set 'secure dma' to 'non secure'-mode */
-	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
-	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
-
-	dsb();  /* barrier */
-
-	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
-	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
-
-	dsb();  /* barrier */
-	udelay(10);
-
-	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
-	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
-}
-
-void board_debug_uart_init(void)
-{
-	/*
-	 * N.B.: This is called before the device-model has been
-	 *       initialised. For this reason, we can not access
-	 *       the GRF address range using the syscon API.
-	 */
-	struct rk3368_grf * const grf =
-		(struct rk3368_grf * const)0xff770000;
-
-	enum {
-		GPIO2D1_MASK            = GENMASK(3, 2),
-		GPIO2D1_GPIO            = 0,
-		GPIO2D1_UART0_SOUT      = (1 << 2),
-
-		GPIO2D0_MASK            = GENMASK(1, 0),
-		GPIO2D0_GPIO            = 0,
-		GPIO2D0_UART0_SIN       = (1 << 0),
-	};
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
-	/* Enable early UART0 on the RK3368 */
-	rk_clrsetreg(&grf->gpio2d_iomux,
-		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
-	rk_clrsetreg(&grf->gpio2d_iomux,
-		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-#define EARLY_UART
-#ifdef EARLY_UART
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	printascii("U-Boot TPL board init\n");
-#endif
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	/* Reset security, so we can use DMA in the MMC drivers */
-	sgrf_init();
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-void board_return_to_bootrom(void)
-{
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_BOOTROM;
-}
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index f62d91d..8c0b370 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <asm/armv8/mmu.h>
+#include <asm/arch/bootrom.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3368.h>
@@ -52,16 +53,10 @@ static struct mm_region rk3368_mem_map[] = {
 
 struct mm_region *mem_map = rk3368_mem_map;
 
-int dram_init_banksize(void)
-{
-	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
-	return 0;
-}
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/dwmmc at ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc at ff0c0000",
+};
 
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 static int mcu_init(void)
@@ -97,3 +92,104 @@ int arch_early_init_r(void)
 	return mcu_init();
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(u32 no)
+{
+	const uintptr_t SGRF_BASE =
+		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+
+	return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(u32 no)
+{
+	const uintptr_t SGRF_BASE =
+		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+	const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
+	const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
+
+	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+	struct rk3368_cru * const cru =
+		(struct rk3368_cru * const)rockchip_get_cru();
+	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+	/* Set all configurable IP to 'non secure'-mode */
+	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+	/*
+	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+	 * Original comment: "ddr space set no secure mode"
+	 */
+	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+	/* Set 'secure dma' to 'non secure'-mode */
+	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+	dsb();  /* barrier */
+
+	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+	dsb();  /* barrier */
+	udelay(10);
+
+	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+void board_debug_uart_init(void)
+{
+	/*
+	 * N.B.: This is called before the device-model has been
+	 *       initialised. For this reason, we can not access
+	 *       the GRF address range using the syscon API.
+	 */
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2D1_MASK            = GENMASK(3, 2),
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART0_SOUT      = (1 << 2),
+
+		GPIO2D0_MASK            = GENMASK(1, 0),
+		GPIO2D0_GPIO            = 0,
+		GPIO2D0_UART0_SIN       = (1 << 0),
+	};
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	/* Enable early UART0 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#endif
+}
+
+int arch_cpu_init(void)
+{
+	/* Reset security, so we can use DMA in the MMC drivers */
+	sgrf_init();
+
+	return 0;
+}
+#endif
diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
index 88b67f9..d682349 100644
--- a/board/geekbuying/geekbox/geekbox.c
+++ b/board/geekbuying/geekbox/geekbox.c
@@ -7,8 +7,3 @@
 #include <common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
index 6a47642..ec3d27e 100644
--- a/board/rockchip/evb_px5/evb-px5.c
+++ b/board/rockchip/evb_px5/evb-px5.c
@@ -4,8 +4,3 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #include <common.h>
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
index 17adb02..ff2d2d2 100644
--- a/board/rockchip/sheep_rk3368/sheep_rk3368.c
+++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c
@@ -15,8 +15,3 @@ int mach_cpu_init(void)
 {
 	return 0;
 }
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
index 73b1488..025692b 100644
--- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c
+++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
@@ -7,9 +7,6 @@
 #include <dm.h>
 #include <ram.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/timer.h>
 #include <syscon.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -18,8 +15,3 @@ int mach_cpu_init(void)
 {
 	return 0;
 }
-
-int board_init(void)
-{
-	return 0;
-}
-- 
1.9.1

[U-Boot] [PATCH 30/36] rockchip: lion-rk3368: remove rockchip timer

[Kever Yang]

We use ARM generic timer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 configs/lion-rk3368_defconfig | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 8a95ce3..89c4d76 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -88,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_TPL_TIMER=y
-CONFIG_ROCKCHIP_TIMER=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_LZO=y
-- 
1.9.1

[U-Boot] [PATCH 31/36] rockchip: rk3399: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3399.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3399-board-spl.c         | 179 ----------------------
 arch/arm/mach-rockchip/rk3399-board.c             |  14 --
 arch/arm/mach-rockchip/rk3399/rk3399.c            |  86 +++++++++--
 board/rockchip/evb_rk3399/evb-rk3399.c            |  56 ++++---
 board/theobroma-systems/puma_rk3399/puma-rk3399.c |  17 +-
 5 files changed, 103 insertions(+), 249 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
deleted file mode 100644
index d35990e..0000000
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/io.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-#include <ram.h>
-#include <spl.h>
-#include <syscon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_return_to_bootrom(void)
-{
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
-	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
-	[BROM_BOOTSOURCE_SPINOR] = "/spi at ff1d0000",
-	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
-};
-
-const char *board_spl_was_booted_from(void)
-{
-	u32  bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
-	const char *bootdevice_ofpath = NULL;
-
-	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
-		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
-
-	if (bootdevice_ofpath)
-		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
-		      __func__, bootdevice_brom_id, bootdevice_ofpath);
-	else
-		debug("%s: failed to resolve brom_bootdevice_id %x\n",
-		      __func__, bootdevice_brom_id);
-
-	return bootdevice_ofpath;
-}
-
-u32 spl_boot_device(void)
-{
-	u32 boot_device = BOOT_DEVICE_MMC1;
-
-	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
-		return BOOT_DEVICE_BOOTROM;
-
-	return boot_device;
-}
-
-#define TIMER_CHN10_BASE	0xff8680a0
-#define TIMER_END_COUNT_L	0x00
-#define TIMER_END_COUNT_H	0x04
-#define TIMER_INIT_COUNT_L	0x10
-#define TIMER_INIT_COUNT_H	0x14
-#define TIMER_CONTROL_REG	0x1c
-
-#define TIMER_EN	0x1
-#define	TIMER_FMODE	(0 << 1)
-#define	TIMER_RMODE	(1 << 1)
-
-void secure_timer_init(void)
-{
-	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
-	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
-	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
-	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
-	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
-}
-
-void board_debug_uart_init(void)
-{
-#define GRF_BASE	0xff770000
-	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
-	/* Enable early UART0 on the RK3399 */
-	rk_clrsetreg(&grf->gpio2c_iomux,
-		     GRF_GPIO2C0_SEL_MASK,
-		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
-	rk_clrsetreg(&grf->gpio2c_iomux,
-		     GRF_GPIO2C1_SEL_MASK,
-		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
-#else
-	/* Enable early UART2 channel C on the RK3399 */
-	rk_clrsetreg(&grf->gpio4c_iomux,
-		     GRF_GPIO4C3_SEL_MASK,
-		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
-	rk_clrsetreg(&grf->gpio4c_iomux,
-		     GRF_GPIO4C4_SEL_MASK,
-		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
-	/* Set channel C as UART2 input */
-	rk_clrsetreg(&grf->soc_con7,
-		     GRF_UART_DBG_SEL_MASK,
-		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	struct rk3399_pmusgrf_regs *sgrf;
-	struct rk3399_grf_regs *grf;
-	int ret;
-
-#define EARLY_UART
-#ifdef EARLY_UART
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	printascii("U-Boot SPL board init");
-#endif
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	/*
-	 * Disable DDR and SRAM security regions.
-	 *
-	 * As we are entered from the BootROM, the region from
-	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
-	 * be protected. This will cause issues with the DW_MMC
-	 * driver, which tries to DMA from/to the stack (likely)
-	 * located in this range.
-	 */
-	sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
-	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
-	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
-
-	/*  eMMC clock generator: disable the clock multipilier */
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
-
-	secure_timer_init();
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("Pinctrl init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c
deleted file mode 100644
index 9293843..0000000
--- a/arch/arm/mach-rockchip/rk3399-board.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2017 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/boot_mode.h>
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-	return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index dbc248f..6c89f25 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -6,8 +6,11 @@
 
 #include <common.h>
 #include <asm/armv8/mmu.h>
-#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/grf_rk3399.h>
 #include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <syscon.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -35,23 +38,86 @@ static struct mm_region rk3399_mem_map[] = {
 
 struct mm_region *mem_map = rk3399_mem_map;
 
-int dram_init_banksize(void)
-{
-	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
+	[BROM_BOOTSOURCE_SPINOR] = "/spi at ff1d0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
+};
 
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+#ifdef CONFIG_SPL_BUILD
 
-	return 0;
+#define TIMER_CHN10_BASE	0xff8680a0
+#define TIMER_END_COUNT_L	0x00
+#define TIMER_END_COUNT_H	0x04
+#define TIMER_INIT_COUNT_L	0x10
+#define TIMER_INIT_COUNT_H	0x14
+#define TIMER_CONTROL_REG	0x1c
+
+#define TIMER_EN	0x1
+#define	TIMER_FMODE	(0 << 1)
+#define	TIMER_RMODE	(1 << 1)
+
+void rockchip_stimer_init(void)
+{
+	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
+	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
+	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
+	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
+	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
+	printf("%s\n", __func__);
 }
 
+#define GRF_BASE	0xff770000
+#define PMUSGRF_BASE	0xff330000
 int arch_cpu_init(void)
 {
+	struct rk3399_pmusgrf_regs *sgrf = (void *)PMUSGRF_BASE;
+	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+
 	/* We do some SoC one time setting here. */
+	/*
+	 * Disable DDR and SRAM security regions.
+	 *
+	 * As we are entered from the BootROM, the region from
+	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
+	 * be protected. This will cause issues with the DW_MMC
+	 * driver, which tries to DMA from/to the stack (likely)
+	 * located in this range.
+	 */
+	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
+	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
 
-	/* Emmc clock generator: disable the clock multipilier */
-	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
+	/*  eMMC clock generator: disable the clock multipilier */
+	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
 
 	return 0;
 }
+#endif
+
+void board_debug_uart_init(void)
+{
+#define GRF_BASE	0xff770000
+	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	/* Enable early UART0 on the RK3399 */
+	rk_clrsetreg(&grf->gpio2c_iomux,
+		     GRF_GPIO2C0_SEL_MASK,
+		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio2c_iomux,
+		     GRF_GPIO2C1_SEL_MASK,
+		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+	/* Enable early UART2 channel C on the RK3399 */
+	rk_clrsetreg(&grf->gpio4c_iomux,
+		     GRF_GPIO4C3_SEL_MASK,
+		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio4c_iomux,
+		     GRF_GPIO4C4_SEL_MASK,
+		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
+	/* Set channel C as UART2 input */
+	rk_clrsetreg(&grf->soc_con7,
+		     GRF_UART_DBG_SEL_MASK,
+		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index 502dec3..79b7436 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -6,23 +6,29 @@
 
 #include <common.h>
 #include <dm.h>
+#include <ram.h>
 #include <dm/pinctrl.h>
 #include <dm/uclass-internal.h>
 #include <asm/arch/periph.h>
 #include <power/regulator.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
 #include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
+#define RK3399_CPUID_OFF  0x7
+#define RK3399_CPUID_LEN  0x10
+
+int rk_board_init(void)
 {
 	struct udevice *pinctrl, *regulator;
 	int ret;
 
 	/*
-	 * The PWM do not have decicated interrupt number in dts and can
+	 * The PWM does not have decicated interrupt number in dts and can
 	 * not get periph_id by pinctrl framework, so let's init them here.
-	 * The PWM2 and PWM3 are for pwm regulater.
+	 * The PWM2 and PWM3 are for pwm regulators.
 	 */
 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 	if (ret) {
@@ -49,10 +55,6 @@ int board_init(void)
 		goto out;
 	}
 
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
 	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
 	if (ret) {
 		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
@@ -69,29 +71,23 @@ out:
 	return 0;
 }
 
-void spl_board_init(void)
-{
-	struct udevice *pinctrl;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		goto err;
-	}
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = 0xfe800000,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.dis_u2_susphy_quirk = 1,
+};
 
-	preloader_console_init();
-	return;
-err:
-	printf("%s: Error %d\n", __func__, ret);
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
 
-	/* No way to report error here */
-	hang();
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return dwc3_uboot_init(&dwc3_device_data);
 }
+#endif
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index c6690fa..9946311 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -25,21 +25,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
-{
-	int ret;
-
-	/*
-	 * We need to call into regulators_enable_boot_on() again, as the call
-	 * during SPL may have not included all regulators.
-	 */
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
-	return 0;
-}
-
 static void rk3399_force_power_on_reset(void)
 {
 	ofnode node;
@@ -62,7 +47,7 @@ static void rk3399_force_power_on_reset(void)
 	dm_gpio_set_value(&sysreset_gpio, 1);
 }
 
-void spl_board_init(void)
+void rk_spl_board_init(void)
 {
 	int  ret;
 	struct rk3399_cru *cru = rockchip_get_cru();
-- 
1.9.1

[U-Boot] [PATCH 32/36] rockchip: remove rk_timer

[Kever Yang]

We do not use rk_timer.c now, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk_timer.c | 48 ---------------------------------------
 1 file changed, 48 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk_timer.c

diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c
deleted file mode 100644
index 853b986..0000000
--- a/arch/arm/mach-rockchip/rk_timer.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/timer.h>
-#include <asm/io.h>
-#include <linux/types.h>
-
-struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
-
-static uint64_t rockchip_get_ticks(void)
-{
-	uint64_t timebase_h, timebase_l;
-
-	timebase_l = readl(&timer_ptr->timer_curr_value0);
-	timebase_h = readl(&timer_ptr->timer_curr_value1);
-
-	return timebase_h << 32 | timebase_l;
-}
-
-static uint64_t usec_to_tick(unsigned int usec)
-{
-	uint64_t tick = usec;
-	tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
-	return tick;
-}
-
-void rockchip_udelay(unsigned int usec)
-{
-	uint64_t tmp;
-
-	/* get timestamp */
-	tmp = rockchip_get_ticks() + usec_to_tick(usec);
-
-	/* loop till event */
-	while (rockchip_get_ticks() < tmp+1)
-		;
-}
-
-void rockchip_timer_init(void)
-{
-	writel(0xffffffff, &timer_ptr->timer_load_count0);
-	writel(0xffffffff, &timer_ptr->timer_load_count1);
-	writel(1, &timer_ptr->timer_ctrl_reg);
-}
-- 
1.9.1

[U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Kever Yang]

pre-loader console in SPL needs UART.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/dts/rk3399-firefly.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index f134c00..a007fa1 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -648,6 +648,7 @@
 };
 
 &uart2 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
-- 
1.9.1

[U-Boot] [PATCH 34/36] rockchip: spl-boot-order: do not enable with OF_PLATDATA

[Kever Yang]

The "fdt_*" functions may not enable even if the OF_CONTROL is enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/spl-boot-order.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 843998d..cf4cc77 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -9,7 +9,7 @@
 #include <mmc.h>
 #include <spl.h>
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 /**
  * spl_node_to_boot_device() - maps from a DT-node to a SPL boot device
  * @node:	of_offset of the node
-- 
1.9.1

[U-Boot] [PATCH 35/36] rockchip: declear boot_devices in bootrom.h

[Kever Yang]

boot_devices may defined in soc file, and used in board file,
we need to delear it in header file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 103b799..ac2f370 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -53,6 +53,8 @@ enum {
 	BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
 };
 
+extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
+
 /**
  * Locations of the boot-device identifier in SRAM
  */
-- 
1.9.1

[U-Boot] [PATCH 36/36] rockchip: add common board file for rockchip platform

[Kever Yang]

We use common board/spl/tpl file for all rockchip SoCs,
- all the SoC spec setting should move into SoC file like rk3288.c;
- tpl is option and only purpose to init DRAM, clock, uart(option);
- spl do secure relate one time init, boot device select, boot into
  U-Boot or trust or OS in falcon mode;
- board do boot mode detect, enable regulator, usb init and so on.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/Makefile |  23 +----
 arch/arm/mach-rockchip/board.c  | 136 ++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/spl.c    | 195 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/tpl.c    | 111 +++++++++++++++++++++++
 4 files changed, 445 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/board.c
 create mode 100644 arch/arm/mach-rockchip/spl.c
 create mode 100644 arch/arm/mach-rockchip/tpl.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index e1b0519..3aba66c 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,15 +11,8 @@
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 
-obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
-obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
-
-obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
+obj-tpl-y += tpl.o
+obj-spl-y += spl.o spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 
@@ -28,21 +21,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 # we can have the preprocessor correctly recognise both 0x0 and 0
 # meaning "turn it off".
 obj-y += boot_mode.o
-
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
-obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
+obj-y += board.o
 endif
 
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
 
-ifndef CONFIG_ARM64
-obj-y += rk_timer.o
-endif
-
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
 ifndef CONFIG_TPL_BUILD
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
new file mode 100644
index 0000000..52c6f66
--- /dev/null
+++ b/arch/arm/mach-rockchip/board.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <debug_uart.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/boot_mode.h>
+#ifdef CONFIG_DM_REGULATOR
+#include <power/regulator.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+int fb_set_reboot_flag(void)
+{
+	printf("Setting reboot to fastboot flag ...\n");
+	/* Set boot mode to fastboot */
+	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+
+	return 0;
+}
+
+#define FASTBOOT_KEY_GPIO 43 /* GPIO1_B3 */
+static int fastboot_key_pressed(void)
+{
+	gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
+	gpio_direction_input(FASTBOOT_KEY_GPIO);
+	return !gpio_get_value(FASTBOOT_KEY_GPIO);
+}
+#endif
+
+__weak int rk_board_init(void)
+{
+	return 0;
+}
+
+__weak int rk_board_late_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+	if (fastboot_key_pressed()) {
+		printf("fastboot key pressed!\n");
+		fb_set_reboot_flag();
+	}
+#endif
+
+#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
+	setup_boot_mode();
+#endif
+
+	return rk_board_late_init();
+}
+
+int board_init(void)
+{
+	int ret;
+
+#if !defined(CONFIG_SUPPORT_SPL)
+	board_debug_uart_init();
+#endif
+#ifdef CONFIG_DM_REGULATOR
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+	return rk_board_init();
+}
+
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					     "snps,dwc2");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+						     "snps,dwc2");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
new file mode 100644
index 0000000..3c10b63
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_ROCKCHIP_IRAM_START_ADDR + 0x10)
+void board_return_to_bootrom(void)
+{
+	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+};
+
+const char *board_spl_was_booted_from(void)
+{
+	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+	const char *bootdevice_ofpath = NULL;
+
+	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
+		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
+
+	if (bootdevice_ofpath)
+		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
+		      __func__, bootdevice_brom_id, bootdevice_ofpath);
+	else
+		debug("%s: failed to resolve brom_bootdevice_id %x\n",
+		      __func__, bootdevice_brom_id);
+
+	return bootdevice_ofpath;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 boot_device = BOOT_DEVICE_MMC1;
+
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
+		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
+		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+	return BOOT_DEVICE_SPI;
+#endif
+	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
+		return BOOT_DEVICE_BOOTROM;
+
+	return boot_device;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	return MMCSD_MODE_RAW;
+}
+
+__weak void rockchip_stimer_init(void)
+{
+#ifndef CONFIG_ARM64
+	asm volatile("mcr p15, 0, %0, c14, c0, 0"
+		     : : "r"(COUNTER_FREQUENCY));
+#endif
+	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
+	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
+}
+
+__weak int arch_cpu_init(void)
+{
+	return 0;
+}
+
+__weak int rk_board_init_f(void)
+{
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_SPL_FRAMEWORK
+	int ret;
+#if !defined(CONFIG_SUPPORT_TPL)
+	struct udevice *dev;
+#endif
+#endif
+
+#if !defined(CONFIG_SUPPORT_TPL)
+	rockchip_stimer_init();
+	arch_cpu_init();
+#endif
+#define EARLY_UART
+#if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+	debug_uart_init();
+	printascii("U-Boot SPL board init");
+#endif
+
+#ifdef CONFIG_SPL_FRAMEWORK
+	ret = spl_early_init();
+	if (ret) {
+		printf("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+#if !defined(CONFIG_SUPPORT_TPL)
+	debug("\nspl:init dram\n");
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		printf("DRAM init failed: %d\n", ret);
+		return;
+	}
+#endif
+	preloader_console_init();
+#else
+	/* Some SoCs like rk3036 does not use any frame work */
+	sdram_init();
+#endif
+
+	rk_board_init_f();
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+#endif
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BOARD_INIT
+__weak int rk_spl_board_init(void)
+{
+	return 0;
+}
+
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+	struct udevice *dev;
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+	if (!led_name)
+		return 0;
+	ret = led_get_by_label(led_name, &dev);
+	if (ret) {
+		debug("%s: get=%d\n", __func__, ret);
+		return ret;
+	}
+	ret = led_set_on(dev, 1);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = setup_led();
+
+	if (ret) {
+		debug("LED ret=%d\n", ret);
+		hang();
+	}
+
+	rk_spl_board_init();
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+#endif
+}
+#endif
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
new file mode 100644
index 0000000..6f9fbaf
--- /dev/null
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <ram.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/uart.h>
+
+#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+__weak void rockchip_stimer_init(void)
+{
+#ifndef CONFIG_ARM64
+	asm volatile("mcr p15, 0, %0, c14, c0, 0"
+		     : : "r"(COUNTER_FREQUENCY));
+#endif
+	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
+	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
+}
+
+__weak int arch_cpu_init(void)
+{
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * Init the timer at the very beginning so that we can get more
+	 * accurate value from timer_get_boot_us()
+	 */
+	rockchip_stimer_init();
+	arch_cpu_init();
+#define EARLY_DEBUG
+#ifdef EARLY_DEBUG
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+	debug_uart_init();
+	printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
+		   U_BOOT_TIME ")\n");
+#endif
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	/* Init ARM arch timer */
+	timer_init();
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		printf("DRAM init failed: %d\n", ret);
+		return;
+	}
+
+#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT)
+	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+#endif
+}
+
+#ifndef CONFIG_SPL_FRAMEWORK
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	/*
+	 * Function attribute is no-return
+	 * This Function never executes
+	 */
+	while (1)
+		;
+}
+#endif
-- 
1.9.1

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Andy Yan]

hi Kever:

     s/rk1108/rv1108


On 2018年03月27日 17:29, Kever Yang wrote:
> We use ARM arch timer instead.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>   include/configs/rv1108_common.h | 5 -----
>   1 file changed, 5 deletions(-)
>
> diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
> index cd204e9..7a9ec7b 100644
> --- a/include/configs/rv1108_common.h
> +++ b/include/configs/rv1108_common.h
> @@ -13,11 +13,6 @@
>   #define CONFIG_SYS_CBSIZE		1024
>   #define CONFIG_SKIP_LOWLEVEL_INIT
>   
> -#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
> -/* TIMER1,initialized by ddr initialize code */
> -#define CONFIG_SYS_TIMER_BASE		0x10350020
> -#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
> -
>   #define CONFIG_SYS_SDRAM_BASE		0x60000000
>   #define CONFIG_NR_DRAM_BANKS		1
>   #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)

[U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Peter Robinson]

On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
> pre-loader console in SPL needs UART.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/dts/rk3399-firefly.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
> index f134c00..a007fa1 100644
> --- a/arch/arm/dts/rk3399-firefly.dts
> +++ b/arch/arm/dts/rk3399-firefly.dts
> @@ -648,6 +648,7 @@
>  };
>
>  &uart2 {
> +       u-boot,dm-pre-reloc;

if this is u-boot specific shouldn't it be in a rk3399-firefly-u-boot.dtsi ?

>         status = "okay";
>  };
>
> --
> 1.9.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order

[Peter Robinson]

On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
> Use "uboot,spl-boot-orde" instead of "uboot,boot0".

I think these should be in *-u-boot.dtsi files, that enables easy sync
between the linux kernel dts files and u-boot like done on a number of
other configs, a couple of the rk3368 devices seem to already use this
as does devices like AllWinner

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-----
>  arch/arm/dts/rk3288-veyron.dtsi     | 6 +-----
>  2 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
> index f2bb7b5..3bf8efb 100644
> --- a/arch/arm/dts/rk3288-phycore-rdk.dts
> +++ b/arch/arm/dts/rk3288-phycore-rdk.dts
> @@ -53,11 +53,7 @@
>
>         chosen {
>                 stdout-path = &uart2;
> -       };
> -
> -       config {
> -               u-boot,dm-pre-reloc;
> -               u-boot,boot0 = &emmc;
> +               u-boot,spl-boot-order = &emmc;
>         };
>
>         user_buttons: user-buttons {
> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
> index a314058..77b9bf8 100644
> --- a/arch/arm/dts/rk3288-veyron.dtsi
> +++ b/arch/arm/dts/rk3288-veyron.dtsi
> @@ -17,11 +17,7 @@
>
>         chosen {
>                 stdout-path = &uart2;
> -       };
> -
> -       config {
> -               u-boot,dm-pre-reloc;
> -               u-boot,boot0 = &spi_flash;
> +               u-boot,spl-boot-order = &spi_flash;
>         };
>
>         firmware {
> --
> 1.9.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Dr. Philipp Tomsich]

> On 27 Mar 2018, at 11:29, Kever Yang <kever.yang@rock-chips.com> wrote:
> 
> We use ARM arch timer instead.

Could you please provide a more useful commit message.
Please consider that most people that look through the GIT log are
not familiar with our platform.

Thanks,
Philipp.

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Alexander Kochetkov]

> 27 марта 2018 г., в 12:29, Kever Yang <kever.yang@rock-chips.com> написал(а):
> 
> We use ARM arch timer instead.

Hi, Kever!

Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU frequency.
I’ve made patch[1] for fixing that in kernel.
If u-boot do arm clock changes after timer initialization, timer can provide inaccurate delays.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297

Alexander.

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Alexander Kochetkov]

The question is: does rk3066 and rk3188 have arch timer? If no, than removing rk_timer
will break u-boot for these chips.

And my comment was about global timer, not arch timer. And I failed to enable arch
timer for rk3188 in the kernel.

Alexander.

> 27 марта 2018 г., в 19:07, Alexander Kochetkov <al.kochet@gmail.com> написал(а):
> 
>> 
>> 27 марта 2018 г., в 12:29, Kever Yang <kever.yang@rock-chips.com> написал(а):
>> 
>> We use ARM arch timer instead.
> 
> Hi, Kever!
> 
> Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU frequency.
> I’ve made patch[1] for fixing that in kernel.
> If u-boot do arm clock changes after timer initialization, timer can provide inaccurate delays.
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297
> 
> Alexander.

[U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Kever Yang]

Hi Peter,


On 03/27/2018 07:49 PM, Peter Robinson wrote:
> On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
>> pre-loader console in SPL needs UART.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  arch/arm/dts/rk3399-firefly.dts | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
>> index f134c00..a007fa1 100644
>> --- a/arch/arm/dts/rk3399-firefly.dts
>> +++ b/arch/arm/dts/rk3399-firefly.dts
>> @@ -648,6 +648,7 @@
>>  };
>>
>>  &uart2 {
>> +       u-boot,dm-pre-reloc;
> if this is u-boot specific shouldn't it be in a rk3399-firefly-u-boot.dtsi ?

Yes, this should go to rk3399-firefly-u-boot.dtsi.

Thanks,
- Kever
>
>>         status = "okay";
>>  };
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Kever Yang]

Hi Alexander,


On 03/28/2018 12:21 AM, Alexander Kochetkov wrote:
> The question is: does rk3066 and rk3188 have arch timer? If no, than removing rk_timer
> will break u-boot for these chips.

Thanks for your comment, I will double check about if this two chips
have arch
timer, I think it should be, but I don't have boards now.

Thanks,
- Kever
>
> And my comment was about global timer, not arch timer. And I failed to enable arch
> timer for rk3188 in the kernel.
>
> Alexander.
>
>> 27 марта 2018 г., в 19:07, Alexander Kochetkov <al.kochet@gmail.com> написал(а):
>>
>>> 27 марта 2018 г., в 12:29, Kever Yang <kever.yang@rock-chips.com> написал(а):
>>>
>>> We use ARM arch timer instead.
>> Hi, Kever!
>>
>> Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU frequency.
>> I’ve made patch[1] for fixing that in kernel.
>> If u-boot do arm clock changes after timer initialization, timer can provide inaccurate delays.
>>
>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297
>>
>> Alexander.
>

[U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order

[Kever Yang]

Hi Peter,


On 03/27/2018 07:55 PM, Peter Robinson wrote:
> On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang <kever.yang@rock-chips.com> wrote:
>> Use "uboot,spl-boot-orde" instead of "uboot,boot0".
> I think these should be in *-u-boot.dtsi files, 

Yes, you are right about this, and move all this u-boot configs into
*-u-boot.dtsi files is also one of my TODO clean up jobs.

I didn't do this now because of the frame work do not fit what we
already have now.

@Simon, @Philipp,
Here is what I want to do:
- I think in most case, all the boards with same SoC shares the U-Boot
configs,
  eg. it's better to have one rk3288-u-boot.dtsi instead of 12
rk3288-xxboard-u-boot.dtsi
- The build system supports to automatic add x-u-boot.dtsi(feature add
by Simon),
    the x could be:
   <dts>-u-boot.dtsi where <dts> is the base name of the .dts
file             
  
<CONFIG_SYS_SOC>-u-boot.dtsi                                                

  
<CONFIG_SYS_CPU>-u-boot.dtsi                                                   

  
<CONFIG_SYS_VENDOR>-u-boot.dtsi                                                

So use CONFIG_SYS_SOC-u-boot.dtsi should be the best choice.
- But we can't use it because the value is always "rockchip"
- we can not change this into a real soc name because:
   There is a symbolic link "arch/${ARCH}/include/asm/arch" for header
file pointing to
   the SoC/CPU specific header directory; and all rockchip headers are
locate at
    arch/arm/include/asm/arch-rockchip/, including many common header
files and
    soc specific files.
- Are we going to add arch-rk3xxx folder for each soc like arch-mxx and
arch-tegraxxx,
  and copy the common header files into each soc directory? Is there
other solution?

Thanks,
- Kever
> that enables easy sync
> between the linux kernel dts files and u-boot like done on a number of
> other configs, a couple of the rk3368 devices seem to already use this
> as does devices like AllWinner
>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-----
>>  arch/arm/dts/rk3288-veyron.dtsi     | 6 +-----
>>  2 files changed, 2 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
>> index f2bb7b5..3bf8efb 100644
>> --- a/arch/arm/dts/rk3288-phycore-rdk.dts
>> +++ b/arch/arm/dts/rk3288-phycore-rdk.dts
>> @@ -53,11 +53,7 @@
>>
>>         chosen {
>>                 stdout-path = &uart2;
>> -       };
>> -
>> -       config {
>> -               u-boot,dm-pre-reloc;
>> -               u-boot,boot0 = &emmc;
>> +               u-boot,spl-boot-order = &emmc;
>>         };
>>
>>         user_buttons: user-buttons {
>> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
>> index a314058..77b9bf8 100644
>> --- a/arch/arm/dts/rk3288-veyron.dtsi
>> +++ b/arch/arm/dts/rk3288-veyron.dtsi
>> @@ -17,11 +17,7 @@
>>
>>         chosen {
>>                 stdout-path = &uart2;
>> -       };
>> -
>> -       config {
>> -               u-boot,dm-pre-reloc;
>> -               u-boot,boot0 = &spi_flash;
>> +               u-boot,spl-boot-order = &spi_flash;
>>         };
>>
>>         firmware {
>> --
>> 1.9.1
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Alexander Kochetkov]

Hello, Kevel!

I can confirm, that rk3188 doesn’t have arch timer. I made test, see below.

By the way, could you tell what git head to use to apply your patch series?
I want to test other changes as well.

I failed to apply to this one head:

commit eef11acebaa48e241e9187c717dc92d3e175c119
Author: Tom Rini <trini@konsulko.com>
Date:   Mon Jan 29 20:12:33 2018 -0500

    Prepare v2018.03-rc1
    
    Signed-off-by: Tom Rini <trini@konsulko.com>

I took get_ticks() code from arch_timer.c into board file and tried to
execute it:

diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index fc58aeb..b5d0984 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -25,9 +25,28 @@ __weak int rk_board_late_init(void)
 	return 0;
 }
 
+#define CONFIG_SYS_HZ_CLOCK    24000000
+
+ulong arch_tbl = 0;
+ulong arch_tbu = 0;
+ulong arch_timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
+unsigned long long arch_get_ticks(void)
+{
+	ulong nowl, nowu;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu));
+
+	arch_tbl = nowl;
+	arch_tbu = nowu;
+
+	return (((unsigned long long)arch_tbu) << 32) | arch_tbl;
+}
+
 int board_late_init(void)
 {
 	struct rk3188_grf *grf;
+	ulong val0, val1;
 
 	setup_boot_mode();
 	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
@@ -40,6 +59,12 @@ int board_late_init(void)
 			NOC_REMAP_MASK << NOC_REMAP_SHIFT);
 	}
 
+	val0 = arch_get_ticks();
+	udelay(100);
+	val1 = arch_get_ticks();
+
+	pr_err("val0 %lu; val1 %lu\n", val0, val1);
+
 	return rk_board_late_init();
 }

And I get undefined instruction error on rk3188 board:

undefined instruction
pc : [<9ff760d6>]	   lr : [<9ff76129>]
reloc pc : [<600010d6>]	   lr : [<60001129>]
sp : 9df669d8  ip : 9df66918	 fp : 00000017
r10: 6003d648  r9 : 9df6cee8	 r8 : 10080228
r7 : 9ffb0654  r6 : 9ffb05e4	 r5 : 9ffb0658  r4 : 3ff75000
r3 : 10001000  r2 : 80000000	 r1 : 20008000  r0 : 20008000
Flags: nzcv  IRQs off  FIQs off  Mode SVC_32

Regards,
Alexander.

> 28 марта 2018 г., в 5:33, Kever Yang <kever.yang@rock-chips.com> написал(а):
> 
> Hi Alexander,
> 
> 
> On 03/28/2018 12:21 AM, Alexander Kochetkov wrote:
>> The question is: does rk3066 and rk3188 have arch timer? If no, than removing rk_timer
>> will break u-boot for these chips.
> 
> Thanks for your comment, I will double check about if this two chips
> have arch
> timer, I think it should be, but I don't have boards now.
> 
> Thanks,
> - Kever
>> 
>> And my comment was about global timer, not arch timer. And I failed to enable arch
>> timer for rk3188 in the kernel.
>> 
>> Alexander.
>> 
>>> 27 марта 2018 г., в 19:07, Alexander Kochetkov <al.kochet@gmail.com> написал(а):
>>> 
>>>> 27 марта 2018 г., в 12:29, Kever Yang <kever.yang@rock-chips.com> написал(а):
>>>> 
>>>> We use ARM arch timer instead.
>>> Hi, Kever!
>>> 
>>> Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU frequency.
>>> I’ve made patch[1] for fixing that in kernel.
>>> If u-boot do arm clock changes after timer initialization, timer can provide inaccurate delays.
>>> 
>>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297
>>> 
>>> Alexander.
>> 
> 
> 

[U-Boot] [U-Boot, 01/36] rockchip: rk3288: move configure_l2ctlr back to rk3288

[Philipp Tomsich]

> The configure_l2ctlr() is used only by rk3288, do not need to
> locate in sys_proto.h
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 ----------------------
>  arch/arm/mach-rockchip/rk3288/rk3288.c         | 26 +++++++++++++++++++++++++-
>  2 files changed, 25 insertions(+), 23 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 02/36] rockchip: add common MACRO to enable sys arch timer

[Philipp Tomsich]

> All rockchip SoCs can use ARM arch timer, let's enable it in
> common header file
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk3368_common.h   | 2 --
>  include/configs/rk3399_common.h   | 2 --
>  include/configs/rockchip-common.h | 4 ++++
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 03/36] rockchip: enable SYS_NS16550 for all SoCs by default

[Philipp Tomsich]

> All rockchip SoCs can use ns16550 driver, enable it for all
> and set SYS_NS16550_MEM32 for all SoCs.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/Kconfig                  | 1 +
>  arch/arm/mach-rockchip/Kconfig    | 1 -
>  include/configs/rk3036_common.h   | 3 ---
>  include/configs/rk3128_common.h   | 2 --
>  include/configs/rk3188_common.h   | 2 --
>  include/configs/rk322x_common.h   | 1 -
>  include/configs/rk3288_common.h   | 2 --
>  include/configs/rk3328_common.h   | 2 --
>  include/configs/rk3368_common.h   | 2 --
>  include/configs/rk3399_common.h   | 2 --
>  include/configs/rockchip-common.h | 2 ++
>  include/configs/rv1108_common.h   | 3 ---
>  12 files changed, 3 insertions(+), 20 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 04/36] rockchip: defconfig: remove CONFIG_SYS_NS16550

[Philipp Tomsich]

> We have enable NS16550 in Kconfig, do not need enable at defconfig
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  configs/evb-rk3128_defconfig      | 1 -
>  configs/evb-rk3229_defconfig      | 1 -
>  configs/evb-rk3288_defconfig      | 1 -
>  configs/evb-rk3328_defconfig      | 1 -
>  configs/evb-rk3399_defconfig      | 1 -
>  configs/fennec-rk3288_defconfig   | 1 -
>  configs/firefly-rk3288_defconfig  | 1 -
>  configs/firefly-rk3399_defconfig  | 1 -
>  configs/miqi-rk3288_defconfig     | 1 -
>  configs/phycore-rk3288_defconfig  | 1 -
>  configs/popmetal-rk3288_defconfig | 1 -
>  configs/puma-rk3399_defconfig     | 1 -
>  configs/tinker-rk3288_defconfig   | 1 -
>  configs/vyasa-rk3288_defconfig    | 1 -
>  14 files changed, 14 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot,05/36] rockchip: add STIMER_BASE for all SoCs

[Philipp Tomsich]

> STIMER is can only access in secure mode if the SoCs supports trust,
> and it locate in alive power domain, as the source of ARM arch/generic
> timer, we add a base addr for all SoCs so that we can init with a common
> function.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 08/36] rockchip: rk322x: remove use rockchip timer as sys timer

[Philipp Tomsich]

> We can use arch timer instead of rockchip timer.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk322x_common.h | 3 ---
>  1 file changed, 3 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 06/36] rockchip: add IRAM_START_ADDR for all SoCs

[Philipp Tomsich]

> We add this for get the location for boot device of bootrom.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 09/36] rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay

[Philipp Tomsich]

> Do not need to use rockchip_udelay after we can use systimer.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++---------------
>  1 file changed, 14 insertions(+), 15 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot,32/36] rockchip: remove rk_timer

[Philipp Tomsich]

> We do not use rk_timer.c now, remove it.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk_timer.c | 48 ---------------------------------------
>  1 file changed, 48 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk_timer.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 11/36] rockchip: defconfig enable sysreset for rk3229 spl

[Philipp Tomsich]

> We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver,
> which will fix missing do_reset() error in SPL build.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  configs/evb-rk3229_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 12/36] rockchip: rk3036: sdram: use udelay instead of rockchip_udelay

[Philipp Tomsich]

> We are going to remove rockchip_udelay after enable arch timer.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++----------
>  1 file changed, 9 insertions(+), 10 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 07/36] rockchip: rk3328: add BOOT_MODE_REG for rk3328

[Philipp Tomsich]

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 10/36] rockchip: rk322x: prepare to use common board file

[Philipp Tomsich]

> Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk322x-board.c              | 155 ---------------------
>  arch/arm/mach-rockchip/rk322x/Makefile             |   2 +-
>  .../{rk322x-board-spl.c => rk322x/rk322x.c}        |  86 ++++--------
>  3 files changed, 29 insertions(+), 214 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
>  rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 14/36] rockchip: rk3036: prepare to use commong board file

[Philipp Tomsich]

> Move some soc spec setting into rk3036.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3036-board.c              | 104 ---------------------
>  arch/arm/mach-rockchip/rk3036/Makefile             |   2 +-
>  .../{rk3036-board-spl.c => rk3036/rk3036.c}        |  41 ++------
>  arch/arm/mach-rockchip/rk3036/sdram_rk3036.c       |  14 +++
>  4 files changed, 24 insertions(+), 137 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
>  rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot,13/36] rockchip: rk3036: remove sys timer

[Philipp Tomsich]

> Use ARM arch timer instead.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk3036_common.h | 4 ----
>  1 file changed, 4 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 15/36] rockchip: declare sdram_init() in common header

[Philipp Tomsich]

> We need a dedicate sdram_init() function for those SoCS not
> using SPL_FRAMEWORK.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 16/36] rockchip: sdram-common: add api to pass dram info to trust os

[Philipp Tomsich]

> Trust OS decode this info like this:
> https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
> We have to set a available value, or else we get error info from
> Trust OS like this:
> "ERROR:   over or zero region, nr=3145987, max=10"
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 ++++
>  arch/arm/mach-rockchip/sdram_common.c             | 21 +++++++++++++++++++++
>  2 files changed, 25 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 17/36] rockchip: sdram_common: add common dram_init_banksize

[Philipp Tomsich]

> dram_init_banksize() can be common used by all SoCs, move it into
> sdram_common.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/sdram_common.c | 63 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 62 insertions(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 19/36] rockchip: rk3188: prepare to use common board file

[Philipp Tomsich]

> Move SoC spec setting into rk3188.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3188-board-spl.c | 226 ------------------------------
>  arch/arm/mach-rockchip/rk3188-board.c     |  82 -----------
>  arch/arm/mach-rockchip/rk3188/Makefile    |   1 +
>  arch/arm/mach-rockchip/rk3188/rk3188.c    |  23 +++
>  4 files changed, 24 insertions(+), 308 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3188-board.c
>  create mode 100644 arch/arm/mach-rockchip/rk3188/rk3188.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Philipp Tomsich]

> We use ARM arch timer instead.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk3188_common.h | 3 ---
>  1 file changed, 3 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 20/36] rockchip: rk3128: remove rockchip timer as systimer

[Philipp Tomsich]

> We use ARM arch timer instead.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk3128_common.h | 4 ----
>  1 file changed, 4 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 22/36] rockchip: dts: rk3288: update spl-boot-order

[Philipp Tomsich]

> Use "uboot,spl-boot-orde" instead of "uboot,boot0".
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-----
>  arch/arm/dts/rk3288-veyron.dtsi     | 6 +-----
>  2 files changed, 2 insertions(+), 10 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 21/36] rockchip: rk3128: prepare use common board file

[Philipp Tomsich]

> remoe rk3128 board file and move SoC spec setting into rk3128.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3128-board.c | 127 ----------------------------------
>  1 file changed, 127 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3128-board.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 24/36] armv8: add timer_get_boot_us() for generic timer

[Philipp Tomsich]

> We need timer_get_boot_us() for boot stage if we use generic timer only.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/cpu/armv8/generic_timer.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 23/36] rockchip: rk3288: remove rockchip timer for sys timer

[Philipp Tomsich]

> Use ARM arch timer instead
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk3288_common.h | 4 ----
>  1 file changed, 4 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Philipp Tomsich]

> We use ARM arch timer instead.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rv1108_common.h | 5 -----
>  1 file changed, 5 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 25/36] rockchip: rk3288: prepare to use common board file

[Philipp Tomsich]

> Use common board file and move SoC spec setting into rk3288.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3288-board-spl.c          | 304 ------------------
>  arch/arm/mach-rockchip/rk3288-board-tpl.c          |  84 -----
>  arch/arm/mach-rockchip/rk3288-board.c              | 338 ---------------------
>  arch/arm/mach-rockchip/rk3288/rk3288.c             | 304 +++++++++++++++++-
>  board/chipspark/popmetal_rk3288/popmetal-rk3288.c  |   9 +-
>  board/mqmaker/miqi_rk3288/miqi-rk3288.c            |   7 -
>  board/phytec/phycore_rk3288/phycore-rk3288.c       |  45 ++-
>  board/rockchip/evb_rk3288/evb-rk3288.c             |   7 -
>  .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c |   8 +
>  board/rockchip/fennec_rk3288/fennec-rk3288.c       |   7 -
>  board/rockchip/tinker_rk3288/tinker-rk3288.c       |   2 +-
>  11 files changed, 357 insertions(+), 758 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c
>  create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 27/36] rockchip: rv1108: prepare to use common board file

[Philipp Tomsich]

> Remove functions will present at common board file.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rv1108/rv1108.c | 8 --------
>  board/rockchip/evb_rv1108/evb_rv1108.c | 6 ------
>  2 files changed, 14 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 28/36] rockchip: rk3328: prepare to use common board file

[Philipp Tomsich]

> Use common board file and move SoC spec setting into rk3328.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3328/rk3328.c | 59 +++++++++++++++++++++++++-----
>  board/rockchip/evb_rk3328/evb-rk3328.c | 66 ----------------------------------
>  2 files changed, 51 insertions(+), 74 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 29/36] rockchip: rk3368: prepare to use common board file

[Philipp Tomsich]

> Use common board file and move SoC spec setting into rk3368.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3368-board-spl.c         |  73 ----------
>  arch/arm/mach-rockchip/rk3368-board-tpl.c         | 157 ----------------------
>  arch/arm/mach-rockchip/rk3368/rk3368.c            | 116 ++++++++++++++--
>  board/geekbuying/geekbox/geekbox.c                |   5 -
>  board/rockchip/evb_px5/evb-px5.c                  |   5 -
>  board/rockchip/sheep_rk3368/sheep_rk3368.c        |   5 -
>  board/theobroma-systems/lion_rk3368/lion_rk3368.c |   8 --
>  7 files changed, 106 insertions(+), 263 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 30/36] rockchip: lion-rk3368: remove rockchip timer

[Philipp Tomsich]

> We use ARM generic timer.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  configs/lion-rk3368_defconfig | 4 ----
>  1 file changed, 4 deletions(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 31/36] rockchip: rk3399: prepare to use common board file

[Philipp Tomsich]

> Use common board file and move SoC spec setting into rk3399.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3399-board-spl.c         | 179 ----------------------
>  arch/arm/mach-rockchip/rk3399-board.c             |  14 --
>  arch/arm/mach-rockchip/rk3399/rk3399.c            |  86 +++++++++--
>  board/rockchip/evb_rk3399/evb-rk3399.c            |  56 ++++---
>  board/theobroma-systems/puma_rk3399/puma-rk3399.c |  17 +-
>  5 files changed, 103 insertions(+), 249 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Philipp Tomsich]

> pre-loader console in SPL needs UART.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/dts/rk3399-firefly.dts | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 34/36] rockchip: spl-boot-order: do not enable with OF_PLATDATA

[Philipp Tomsich]

> The "fdt_*" functions may not enable even if the OF_CONTROL is enabled.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/spl-boot-order.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 35/36] rockchip: declear boot_devices in bootrom.h

[Philipp Tomsich]

> boot_devices may defined in soc file, and used in board file,
> we need to delear it in header file.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Philipp Tomsich]

> We use common board/spl/tpl file for all rockchip SoCs,
> - all the SoC spec setting should move into SoC file like rk3288.c;
> - tpl is option and only purpose to init DRAM, clock, uart(option);
> - spl do secure relate one time init, boot device select, boot into
>   U-Boot or trust or OS in falcon mode;
> - board do boot mode detect, enable regulator, usb init and so on.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/Makefile |  23 +----
>  arch/arm/mach-rockchip/board.c  | 136 ++++++++++++++++++++++++++++
>  arch/arm/mach-rockchip/spl.c    | 195 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-rockchip/tpl.c    | 111 +++++++++++++++++++++++
>  4 files changed, 445 insertions(+), 20 deletions(-)
>  create mode 100644 arch/arm/mach-rockchip/board.c
>  create mode 100644 arch/arm/mach-rockchip/spl.c
>  create mode 100644 arch/arm/mach-rockchip/tpl.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 09/36] rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay

[Philipp Tomsich]

> Do not need to use rockchip_udelay after we can use systimer.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> 
>  drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++---------------
>  1 file changed, 14 insertions(+), 15 deletions(-)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot,32/36] rockchip: remove rk_timer

[Philipp Tomsich]

> We do not use rk_timer.c now, remove it.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> 
>  arch/arm/mach-rockchip/rk_timer.c | 48 ---------------------------------------
>  1 file changed, 48 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk_timer.c
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 11/36] rockchip: defconfig enable sysreset for rk3229 spl

[Philipp Tomsich]

> We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver,
> which will fix missing do_reset() error in SPL build.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> 
>  configs/evb-rk3229_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot,13/36] rockchip: rk3036: remove sys timer

[Philipp Tomsich]

> Use ARM arch timer instead.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  include/configs/rk3036_common.h | 4 ----
>  1 file changed, 4 deletions(-)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 22/36] rockchip: dts: rk3288: update spl-boot-order

[Philipp Tomsich]

> Use "uboot,spl-boot-orde" instead of "uboot,boot0".
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-----
>  arch/arm/dts/rk3288-veyron.dtsi     | 6 +-----
>  2 files changed, 2 insertions(+), 10 deletions(-)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 34/36] rockchip: spl-boot-order: do not enable with OF_PLATDATA

[Philipp Tomsich]

> The "fdt_*" functions may not enable even if the OF_CONTROL is enabled.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/spl-boot-order.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot, 01/36] rockchip: rk3288: move configure_l2ctlr back to rk3288

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> The configure_l2ctlr() is used only by rk3288, do not need to
> locate in sys_proto.h

Please elaborate on what the function does and why it is not needed by any 
of the other SOCs (after all: it has been available to all SOCs so far).

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

This should be a standalone patch and doesn't need to be part of the
series it is in.  This series has way too many different things happening 
at once and needs to be broken up into individual series that do one 
well-defined thing each.

See below for requested changes.

> ---
>
> arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 ----------------------
> arch/arm/mach-rockchip/rk3288/rk3288.c         | 26 +++++++++++++++++++++++++-
> 2 files changed, 25 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
> index e428d59..3617ac2 100644
> --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
> +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
> @@ -7,27 +7,5 @@
> #ifndef _ASM_ARCH_SYS_PROTO_H
> #define _ASM_ARCH_SYS_PROTO_H
>
> -#ifdef CONFIG_ROCKCHIP_RK3288
> -#include <asm/armv7.h>
> -
> -static void configure_l2ctlr(void)
> -{
> -	uint32_t l2ctlr;
> -
> -	l2ctlr = read_l2ctlr();
> -	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
> -
> -	/*
> -	* Data RAM write latency: 2 cycles
> -	* Data RAM read latency: 2 cycles
> -	* Data RAM setup latency: 1 cycle
> -	* Tag RAM write latency: 1 cycle
> -	* Tag RAM read latency: 1 cycle
> -	* Tag RAM setup latency: 1 cycle
> -	*/
> -	l2ctlr |= (1 << 3 | 1 << 0);
> -	write_l2ctlr(l2ctlr);
> -}
> -#endif /* CONFIG_ROCKCHIP_RK3288 */
>
> #endif /* _ASM_ARCH_SYS_PROTO_H */
> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
> index acc3b79..1e1c6be 100644
> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
> @@ -3,15 +3,39 @@
>  *
>  * SPDX-License-Identifier:     GPL-2.0+
>  */
> +#include <asm/armv7.h>
> #include <asm/io.h>
> #include <asm/arch/hardware.h>
>
> #define GRF_SOC_CON2 0xff77024c

Please make this a const-declaration in the function it is needed in.

>
> +#ifdef CONFIG_SPL_BUILD

Should this really happen both for TPL and SPL?

> +static void configure_l2ctlr(void)
> +{
> +	u32 l2ctlr;
> +
> +	l2ctlr = read_l2ctlr();
> +	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */

What are bits 0...17?

> +
> +	/*
> +	 * Data RAM write latency: 2 cycles
> +	 * Data RAM read latency: 2 cycles
> +	 * Data RAM setup latency: 1 cycle
> +	 * Tag RAM write latency: 1 cycle
> +	 * Tag RAM read latency: 1 cycle
> +	 * Tag RAM setup latency: 1 cycle
> +	 */

Please add a symbolic way to assemble these (i.e. something that makes it 
easy for the casual reader to see what values you are writing to which 
bitfields).

> +	l2ctlr |= (1 << 3 | 1 << 0);

From the "clear bit0 ~ bit17" and this, I assume you actually want to do a 
clrsetbits_le32...

> +	write_l2ctlr(l2ctlr);
> +}
> +#endif
> +
> int arch_cpu_init(void)
> {
> 	/* We do some SoC one time setting here. */
> -
> +#ifdef CONFIG_SPL_BUILD
> +	configure_l2ctlr();
> +#else
> 	/* Use rkpwm by default */
> 	rk_setreg(GRF_SOC_CON2, 1 << 0);

Please use a symbolic way to write the (1 << 0), wo it is easy for the 
casual reader to see what gets enabled/disabled here.

>
>

[U-Boot] [U-Boot, 02/36] rockchip: add common MACRO to enable sys arch timer

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> All rockchip SoCs can use ARM arch timer, let's enable it in
> common header file

Please provide a commit message that is more descriptive of what actually 
happens... i.e. that COUNTER_FREQUENCY gets moved to a common header.  It 
would be great to document why this will always remain 24M.

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

See below for requested changes.

> ---
>
> include/configs/rk3368_common.h   | 2 --
> include/configs/rk3399_common.h   | 2 --
> include/configs/rockchip-common.h | 4 ++++
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
> index 10f643f..a7fe4ca 100644
> --- a/include/configs/rk3368_common.h
> +++ b/include/configs/rk3368_common.h
> @@ -22,8 +22,6 @@
> #define CONFIG_SYS_CBSIZE		1024
> #define CONFIG_SKIP_LOWLEVEL_INIT
>
> -#define COUNTER_FREQUENCY               24000000
> -
> #define CONFIG_SYS_NS16550_MEM32
>
> #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
> index d700bf2..fe8c675 100644
> --- a/include/configs/rk3399_common.h
> +++ b/include/configs/rk3399_common.h
> @@ -17,8 +17,6 @@
> #define CONFIG_SPL_SPI_LOAD
> #endif
>
> -#define COUNTER_FREQUENCY               24000000
> -
> #define CONFIG_SYS_NS16550_MEM32
>
> #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
> diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
> index 26d41b5..24651ce 100644
> --- a/include/configs/rockchip-common.h
> +++ b/include/configs/rockchip-common.h
> @@ -8,6 +8,10 @@
> #define _ROCKCHIP_COMMON_H_
> #include <linux/sizes.h>
>
> +#define COUNTER_FREQUENCY               24000000

Is this really safe for all past, current and future SOCs (after all: you 
are putting this into 'rockchip-common.h'?

> +#define CONFIG_SYS_ARCH_TIMER

I don't agree with putting this here, as the CONFIG_SYS_ARCH_TIMER 
definition is only used on ARMv7, but this file is also included by ARMv8 
SOCs.

> +#define CONFIG_SYS_HZ_CLOCK	24000000

You might want to have this refer back to COUNTER_FREQUENCY.

> +
> #ifndef CONFIG_SPL_BUILD
>
> /* First try to boot from SD (index 0), then eMMC (index 1) */
>

[U-Boot] [U-Boot, 03/36] rockchip: enable SYS_NS16550 for all SoCs by default

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> All rockchip SoCs can use ns16550 driver, enable it for all
> and set SYS_NS16550_MEM32 for all SoCs.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

See below for a question.

Note that I believe that the NS16550 changes should go into a separate 
series and be split off this huge series (which honestly is trying to do 
too many things at once).

>
> arch/arm/Kconfig                  | 1 +
> arch/arm/mach-rockchip/Kconfig    | 1 -
> include/configs/rk3036_common.h   | 3 ---
> include/configs/rk3128_common.h   | 2 --
> include/configs/rk3188_common.h   | 2 --
> include/configs/rk322x_common.h   | 1 -
> include/configs/rk3288_common.h   | 2 --
> include/configs/rk3328_common.h   | 2 --
> include/configs/rk3368_common.h   | 2 --
> include/configs/rk3399_common.h   | 2 --
> include/configs/rockchip-common.h | 2 ++
> include/configs/rv1108_common.h   | 3 ---
> 12 files changed, 3 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2c52ff0..3e9a80d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1167,6 +1167,7 @@ config ARCH_ROCKCHIP
> 	select DM_PWM
> 	select DM_REGULATOR
> 	select ENABLE_ARM_SOC_BOOT0_HOOK
> +	select SYS_NS16550

Just wondering: shouldn't this be an 'imply'?

> 	imply CMD_FASTBOOT
> 	imply FASTBOOT
> 	imply FAT_WRITE
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 0adaed4..007cb22 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
> 	imply SPL_SERIAL_SUPPORT
> 	imply TPL_SERIAL_SUPPORT
> 	select DEBUG_UART_BOARD_INIT
> -	select SYS_NS16550
> 	help
> 	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
> 	  into a big and little cluster with 4 cores each) Cortex-A53 including
> diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
> index f39a272..c5ec864 100644
> --- a/include/configs/rk3036_common.h
> +++ b/include/configs/rk3036_common.h
> @@ -18,9 +18,6 @@
> #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
> #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
>
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
> #define CONFIG_SYS_LOAD_ADDR		0x60800800
> #define CONFIG_SPL_STACK		0x10081fff
> diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
> index bd8019c..c593f18 100644
> --- a/include/configs/rk3128_common.h
> +++ b/include/configs/rk3128_common.h
> @@ -19,8 +19,6 @@
> #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
> #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
>
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
> #define CONFIG_SYS_LOAD_ADDR		0x60800800
>
> diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
> index 94f8cda..30c150e 100644
> --- a/include/configs/rk3188_common.h
> +++ b/include/configs/rk3188_common.h
> @@ -22,8 +22,6 @@
> #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
> #define CONFIG_SYS_TIMER_COUNTS_DOWN
>
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
> /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
> #endif
> diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
> index 7f9c7fb..832f037 100644
> --- a/include/configs/rk322x_common.h
> +++ b/include/configs/rk322x_common.h
> @@ -18,7 +18,6 @@
> #define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
> #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
>
> -#define CONFIG_SYS_NS16550_MEM32
> #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
> #define CONFIG_SYS_LOAD_ADDR		0x60800800
> #define CONFIG_SPL_STACK		0x10088000
> diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
> index 78595b8..44d5c2a 100644
> --- a/include/configs/rk3288_common.h
> +++ b/include/configs/rk3288_common.h
> @@ -19,8 +19,6 @@
> #define	CONFIG_SYS_TIMER_BASE		0xff810020 /* TIMER7 */
> #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
>
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
> /* Bootrom will load u-boot binary to 0x0 once return from SPL */
> #endif
> diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
> index 7018668..ce650c8 100644
> --- a/include/configs/rk3328_common.h
> +++ b/include/configs/rk3328_common.h
> @@ -13,8 +13,6 @@
> #define CONFIG_SYS_CBSIZE		1024
> #define CONFIG_SKIP_LOWLEVEL_INIT
>
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
> #define CONFIG_SYS_LOAD_ADDR		0x00800800
>
> diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
> index a7fe4ca..866383d 100644
> --- a/include/configs/rk3368_common.h
> +++ b/include/configs/rk3368_common.h
> @@ -22,8 +22,6 @@
> #define CONFIG_SYS_CBSIZE		1024
> #define CONFIG_SKIP_LOWLEVEL_INIT
>
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
> #define CONFIG_SYS_LOAD_ADDR		0x00280000
>
> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
> index fe8c675..53691e5 100644
> --- a/include/configs/rk3399_common.h
> +++ b/include/configs/rk3399_common.h
> @@ -17,8 +17,6 @@
> #define CONFIG_SPL_SPI_LOAD
> #endif
>
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
> #define CONFIG_SYS_LOAD_ADDR		0x00800800
> #define CONFIG_SPL_STACK		0xff8effff
> diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
> index 24651ce..4062480 100644
> --- a/include/configs/rockchip-common.h
> +++ b/include/configs/rockchip-common.h
> @@ -12,6 +12,8 @@
> #define CONFIG_SYS_ARCH_TIMER
> #define CONFIG_SYS_HZ_CLOCK	24000000
>
> +#define CONFIG_SYS_NS16550_MEM32
> +
> #ifndef CONFIG_SPL_BUILD
>
> /* First try to boot from SD (index 0), then eMMC (index 1) */
> diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
> index 349c53c..cd204e9 100644
> --- a/include/configs/rv1108_common.h
> +++ b/include/configs/rv1108_common.h
> @@ -18,9 +18,6 @@
> #define CONFIG_SYS_TIMER_BASE		0x10350020
> #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
>
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_MEM32
> -
> #define CONFIG_SYS_SDRAM_BASE		0x60000000
> #define CONFIG_NR_DRAM_BANKS		1
> #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)
>

[U-Boot] [U-Boot, 04/36] rockchip: defconfig: remove CONFIG_SYS_NS16550

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We have enable NS16550 in Kconfig, do not need enable at defconfig

Did you generate this with moveconfig.py?

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

[U-Boot] [U-Boot,05/36] rockchip: add STIMER_BASE for all SoCs

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> STIMER is can only access in secure mode if the SoCs supports trust,
> and it locate in alive power domain, as the source of ARM arch/generic
> timer, we add a base addr for all SoCs so that we can init with a common
> function.

The commit message does not really tell what the source changes are 
(although it seems to describe part of the motivation for this change).

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

See below for requested changes.

> ---
>
> arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 007cb22..5dfe452 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
> 	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
> 	  according to the value from this register.
>
> +config ROCKCHIP_STIMER_BASE
> +	hex "Rockchip Secure timer base address"
> +	default 0xff220020 if ROCKCHIP_PX30

We don't have support for the PX30 in the U-Boot code base yet.
Until a series to add support for the PX30 comes in, you should not have 
this here yet (and then add this specific case when the PX30 support is 
added).

> +	default 0x200440a0 if ROCKCHIP_RK3036
> +	default 0x2000e000 if ROCKCHIP_RK3066
> +	default 0x20018020 if ROCKCHIP_RK3126
> +	default 0x200440a0 if ROCKCHIP_RK3128
> +	default 0x2000e000 if ROCKCHIP_RK3188
> +	default 0x110d0020 if ROCKCHIP_RK322X
> +	default 0xff810020 if ROCKCHIP_RK3288
> +	default 0xff1d0020 if ROCKCHIP_RK3328
> +	default 0xff830020 if ROCKCHIP_RK3368
> +	default 0xff8680a0 if ROCKCHIP_RK3399
> +	default 0x10350020 if ROCKCHIP_RV1108
> +	default 0
> +	help
> +	  The secure timer inited in SPL/TPL in secure word, ARM generic timer
> +	  works after this timer work.

This should not be in Kconfig and rather in a header-file.
With what you do here, a user (e.g. via 'make menuconfig') or a defconfig 
file (e.g. due to a typo) could accidentially change overwrite this.

> +
> config ROCKCHIP_SPL_RESERVE_IRAM
> 	hex "Size of IRAM reserved in SPL"
> 	default 0
>

[U-Boot] [U-Boot, 06/36] rockchip: add IRAM_START_ADDR for all SoCs

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We add this for get the location for boot device of bootrom.

Your commit message should be specific enough, so the motivation for the 
change, where it fits into the overall architecture and what is changed 
are apparent.

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

See below for requested changes.

> ---
>
> arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 5dfe452..98bf935 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -209,6 +209,23 @@ config ROCKCHIP_STIMER_BASE
> 	  The secure timer inited in SPL/TPL in secure word, ARM generic timer
> 	  works after this timer work.
>
> +config ROCKCHIP_IRAM_START_ADDR
> +	hex "Rockchip Secure timer base address"

Huh: copy-and-paste?

> +	default 0xff0e0000 if ROCKCHIP_PX30

See my earlier comment regarding changes specific to the PX30.

> +	default 0x10080000 if ROCKCHIP_RK3036
> +	default 0x10080000 if ROCKCHIP_RK3128
> +	default 0x10080000 if ROCKCHIP_RK3188
> +	default 0x10080000 if ROCKCHIP_RK322X
> +	default 0xff700000 if ROCKCHIP_RK3288
> +	default 0xff091000 if ROCKCHIP_RK3328
> +	default 0xff8c0000 if ROCKCHIP_RK3368
> +	default 0xff8c0000 if ROCKCHIP_RK3399
> +	default 0x10080000 if ROCKCHIP_RV1108
> +	default 0
> +	help
> +	  The IRAM start addr is to locate variant of the boot device from
> +	  bootrom.

The same comment as for the secure timer-base applies here.
This is way to important to have it in Kconfig, where a user can easily 
override.

> +
> config ROCKCHIP_SPL_RESERVE_IRAM
> 	hex "Size of IRAM reserved in SPL"
> 	default 0
>

[U-Boot] [U-Boot, 07/36] rockchip: rk3328: add BOOT_MODE_REG for rk3328

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Commit message is missing.

> ---
>
> arch/arm/mach-rockchip/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 98bf935..892d51e 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -182,6 +182,7 @@ config ROCKCHIP_BOOT_MODE_REG
> 	default 0x20004040 if ROCKCHIP_RK3188
> 	default 0x110005c8 if ROCKCHIP_RK322X
> 	default 0xff730094 if ROCKCHIP_RK3288
> +	default 0xff1005c8 if ROCKCHIP_RK3328
> 	default 0xff738200 if ROCKCHIP_RK3368
> 	default 0xff320300 if ROCKCHIP_RK3399
> 	default 0x10300580 if ROCKCHIP_RV1108
>

[U-Boot] [U-Boot, 08/36] rockchip: rk322x: remove use rockchip timer as sys timer

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We can use arch timer instead of rockchip timer.

A slightly more enlightening commit message would be great.

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

These changes for (for the timer) should go into a separate series.
Also: you should refactor these patches in such a way that the tree (after 
every patch that is applied) this builds.  A good way to do so is to do 
one device after another per patch.

> ---
>
> include/configs/rk322x_common.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
> index 832f037..29e222a 100644
> --- a/include/configs/rk322x_common.h
> +++ b/include/configs/rk322x_common.h
> @@ -14,9 +14,6 @@
> #define CONFIG_SYS_CBSIZE		1024
> #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
>
> -#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
> -#define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
> -#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
>
> #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
> #define CONFIG_SYS_LOAD_ADDR		0x60800800
>

[U-Boot] [U-Boot, 10/36] rockchip: rk322x: prepare to use common board file

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c

A clear description of what the patch is attempting to achieve.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for requested changes.

> ---
>
> arch/arm/mach-rockchip/rk322x-board.c              | 155 ---------------------
> arch/arm/mach-rockchip/rk322x/Makefile             |   2 +-
> .../{rk322x-board-spl.c => rk322x/rk322x.c}        |  86 ++++--------
> 3 files changed, 29 insertions(+), 214 deletions(-)
> delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
> rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)
>
> diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
> deleted file mode 100644
> index 8642a90..0000000
> --- a/arch/arm/mach-rockchip/rk322x-board.c
> +++ /dev/null
> @@ -1,155 +0,0 @@
> -/*
> - * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -#include <common.h>
> -#include <clk.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <syscon.h>
> -#include <asm/io.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/periph.h>
> -#include <asm/arch/grf_rk322x.h>
> -#include <asm/arch/boot_mode.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -__weak int rk_board_late_init(void)
> -{
> -	return 0;
> -}
> -
> -int board_late_init(void)
> -{
> -	setup_boot_mode();
> -
> -	return rk_board_late_init();
> -}
> -
> -int board_init(void)
> -{
> -#include <asm/arch/grf_rk322x.h>
> -	/* Enable early UART2 channel 1 on the RK322x */
> -#define GRF_BASE	0x11000000
> -	struct rk322x_grf * const grf = (void *)GRF_BASE;
> -	enum {
> -		GPIO1B2_SHIFT		= 4,
> -		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
> -		GPIO1B2_GPIO		= 0,
> -		GPIO1B2_UART21_SIN,
> -
> -		GPIO1B1_SHIFT		= 2,
> -		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
> -		GPIO1B1_GPIO            = 0,
> -		GPIO1B1_UART1_SOUT,
> -		GPIO1B1_UART21_SOUT,
> -	};
> -	enum {
> -		CON_IOMUX_UART2SEL_SHIFT= 8,
> -		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
> -		CON_IOMUX_UART2SEL_2	= 0,
> -		CON_IOMUX_UART2SEL_21,
> -	};
> -
> -	rk_clrsetreg(&grf->gpio1b_iomux,
> -		     GPIO1B1_MASK | GPIO1B2_MASK,
> -		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
> -		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
> -	/* Set channel C as UART2 input */
> -	rk_clrsetreg(&grf->con_iomux,
> -		     CON_IOMUX_UART2SEL_MASK,
> -		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
> -
> -	/*
> -	* The integrated macphy is enabled by default, disable it
> -	* for saving power consuming.
> -	*/
> -	rk_clrsetreg(&grf->macphy_con[0],
> -		     MACPHY_CFG_ENABLE_MASK,
> -		     0 << MACPHY_CFG_ENABLE_SHIFT);
> -
> -	return 0;
> -}
> -
> -int dram_init_banksize(void)
> -{
> -	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> -	gd->bd->bi_dram[0].size = 0x8400000;
> -	/* Reserve 0x200000 for OPTEE */
> -	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
> -				+ gd->bd->bi_dram[0].size + 0x200000;
> -	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
> -				+ gd->ram_size - gd->bd->bi_dram[1].start;
> -
> -	return 0;
> -}
> -
> -#ifndef CONFIG_SYS_DCACHE_OFF
> -void enable_caches(void)
> -{
> -	/* Enable D-cache. I-cache is already enabled in start.S */
> -	dcache_enable();
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> -#include <usb.h>
> -#include <usb/dwc2_udc.h>
> -
> -static struct dwc2_plat_otg_data rk322x_otg_data = {
> -	.rx_fifo_sz	= 512,
> -	.np_tx_fifo_sz	= 16,
> -	.tx_fifo_sz	= 128,
> -};
> -
> -int board_usb_init(int index, enum usb_init_type init)
> -{
> -	int node;
> -	const char *mode;
> -	bool matched = false;
> -	const void *blob = gd->fdt_blob;
> -
> -	/* find the usb_otg node */
> -	node = fdt_node_offset_by_compatible(blob, -1,
> -					"rockchip,rk3288-usb");
> -
> -	while (node > 0) {
> -		mode = fdt_getprop(blob, node, "dr_mode", NULL);
> -		if (mode && strcmp(mode, "otg") == 0) {
> -			matched = true;
> -			break;
> -		}
> -
> -		node = fdt_node_offset_by_compatible(blob, node,
> -					"rockchip,rk3288-usb");
> -	}
> -	if (!matched) {
> -		debug("Not found usb_otg device\n");
> -		return -ENODEV;
> -	}
> -	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> -
> -	return dwc2_udc_probe(&rk322x_otg_data);
> -}
> -
> -int board_usb_cleanup(int index, enum usb_init_type init)
> -{
> -	return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
> -int fb_set_reboot_flag(void)
> -{
> -	struct rk322x_grf *grf;
> -
> -	printf("Setting reboot to fastboot flag ...\n");
> -	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> -	/* Set boot mode to fastboot */
> -	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
> -
> -	return 0;
> -}
> -#endif
> diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile
> index ecb3e8d..89b0fed 100644
> --- a/arch/arm/mach-rockchip/rk322x/Makefile
> +++ b/arch/arm/mach-rockchip/rk322x/Makefile
> @@ -4,6 +4,6 @@
> # SPDX-License-Identifier:     GPL-2.0+
> #
>
> -
> obj-y += clk_rk322x.o
> +obj-y += rk322x.o
> obj-y += syscon_rk322x.o
> diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
> similarity index 51%
> rename from arch/arm/mach-rockchip/rk322x-board-spl.c
> rename to arch/arm/mach-rockchip/rk322x/rk322x.c
> index 206abfa..98b6ec3 100644
> --- a/arch/arm/mach-rockchip/rk322x-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
> @@ -1,32 +1,41 @@
> /*
> - * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2017 Rockchip Electronics Co., Ltd
>  *
>  * SPDX-License-Identifier:     GPL-2.0+
>  */
> -
> -#include <common.h>
> -#include <debug_uart.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <spl.h>
> #include <asm/io.h>
> #include <asm/arch/bootrom.h>
> -#include <asm/arch/cru_rk322x.h>
> -#include <asm/arch/grf_rk322x.h>
> #include <asm/arch/hardware.h>
> -#include <asm/arch/timer.h>
> -#include <asm/arch/uart.h>
> +#include <asm/arch/grf_rk322x.h>
>
> -u32 spl_boot_device(void)
> +#define GRF_BASE	0x11000000
> +#define CRU_MISC_CON	0x110e0134
> +#define SGRF_DDR_CON0	0x10150000

Please use 'const' and declare within functions, if used only by a single 
function.

> +
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> +	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
> +	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
> +};
> +
> +#ifdef CONFIG_SPL_BUILD
> +int arch_cpu_init(void)
> {
> -	return BOOT_DEVICE_MMC1;
> -}
> -DECLARE_GLOBAL_DATA_PTR;
> +	static struct rk322x_grf * const grf = (void *)GRF_BASE;
> +	/* We do some SoC one time setting here. */
>
> -#define GRF_BASE	0x11000000
> -#define SGRF_BASE	0x10140000
> +	/* Disable the ddr secure region setting to make it non-secure */
> +	rk_clrreg(SGRF_DDR_CON0, 0x4000);
> +
> +	/*
> +	 * The integrated macphy is enabled by default, disable it
> +	 * for saving power consuming.
> +	 */
> +	rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
> +		     0 << MACPHY_CFG_ENABLE_SHIFT);
>
> -#define DEBUG_UART_BASE	0x11030000
> +	return 0;
> +}
> +#endif
>
> void board_debug_uart_init(void)
> {
> @@ -34,8 +43,7 @@ void board_debug_uart_init(void)
> 	enum {
> 		GPIO1B2_SHIFT		= 4,
> 		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
> -		GPIO1B2_GPIO            = 0,
> -		GPIO1B2_UART1_SIN,
> +		GPIO1B2_GPIO		= 0,
> 		GPIO1B2_UART21_SIN,

This looks odd: are you shure this is 'GPIO1B2_UART21_SIN'?

>
> 		GPIO1B1_SHIFT		= 2,
> @@ -61,41 +69,3 @@ void board_debug_uart_init(void)
> 		     CON_IOMUX_UART2SEL_MASK,
> 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
> }
> -
> -#define SGRF_DDR_CON0 0x10150000
> -void board_init_f(ulong dummy)
> -{
> -	struct udevice *dev;
> -	int ret;
> -
> -	/*
> -	 * Debug UART can be used from here if required:
> -	 *
> -	 * debug_uart_init();
> -	 * printch('a');
> -	 * printhex8(0x1234);
> -	 * printascii("string");
> -	 */
> -	debug_uart_init();
> -	printascii("SPL Init");
> -
> -	ret = spl_early_init();
> -	if (ret) {
> -		debug("spl_early_init() failed: %d\n", ret);
> -		hang();
> -	}
> -
> -	rockchip_timer_init();
> -	printf("timer init done\n");
> -	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> -	if (ret) {
> -		printf("DRAM init failed: %d\n", ret);
> -		return;
> -	}
> -
> -	/* Disable the ddr secure region setting to make it non-secure */
> -	rk_clrreg(SGRF_DDR_CON0, 0x4000);
> -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
> -	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> -#endif
> -}
>

[U-Boot] [U-Boot, 35/36] rockchip: declear boot_devices in bootrom.h

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> boot_devices may defined in soc file, and used in board file,
> we need to delear it in header file.

I think you meant to write 'declare'.
Again: a bit more context from the commit message might be useful (e.g. 
what is 'boot_devices'?

If 'boot_devices' suddenly becomes visible across multiple files, we may 
need to rethink its naming... 'boot_devices' is too similar to names used 
in SPL (e.g. 'boot_device') and could easily be confused.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for requested changes.

> ---
>
> arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
> index 103b799..ac2f370 100644
> --- a/arch/arm/include/asm/arch-rockchip/bootrom.h
> +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
> @@ -53,6 +53,8 @@ enum {
> 	BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
> };
>
> +extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];

If you make this visible outside of a single board file and move it to a 
header file, this needs some documentation (and naming will need to be 
rethought as well, as described above).

> +
> /**
>  * Locations of the boot-device identifier in SRAM
>  */
>

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We use common board/spl/tpl file for all rockchip SoCs,
> - all the SoC spec setting should move into SoC file like rk3288.c;
> - tpl is option and only purpose to init DRAM, clock, uart(option);
> - spl do secure relate one time init, boot device select, boot into
>  U-Boot or trust or OS in falcon mode;
> - board do boot mode detect, enable regulator, usb init and so on.

There's too much going on in a single commit/single series.
This needs to be split up into multiple, independent steps (e.g. one for 
the timer changes, another one for the UART changes)...

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for requested changes (beyond splitting this up).
Reviewing this in this state is a real chore, so I'll probably have more 
comments, once I see this presented in more manageable parcels.

> ---
>
> arch/arm/mach-rockchip/Makefile |  23 +----
> arch/arm/mach-rockchip/board.c  | 136 ++++++++++++++++++++++++++++
> arch/arm/mach-rockchip/spl.c    | 195 ++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-rockchip/tpl.c    | 111 +++++++++++++++++++++++
> 4 files changed, 445 insertions(+), 20 deletions(-)
> create mode 100644 arch/arm/mach-rockchip/board.c
> create mode 100644 arch/arm/mach-rockchip/spl.c
> create mode 100644 arch/arm/mach-rockchip/tpl.c
>
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index e1b0519..3aba66c 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -11,15 +11,8 @@
> obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
> obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>
> -obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
> -obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
> -
> -obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
> -obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
> -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
> -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
> -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
> -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
> +obj-tpl-y += tpl.o
> +obj-spl-y += spl.o spl-boot-order.o
>
> ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
>
> @@ -28,21 +21,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
> # we can have the preprocessor correctly recognise both 0x0 and 0
> # meaning "turn it off".
> obj-y += boot_mode.o
> -
> -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
> -obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
> -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
> -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
> -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
> -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
> +obj-y += board.o
> endif
>
> obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
>
> -ifndef CONFIG_ARM64
> -obj-y += rk_timer.o
> -endif

This would need to have gone with the rk_timer.c removal.
Otherwise things don't build between the earlier patch and here.

> -
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
> obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
> ifndef CONFIG_TPL_BUILD
> diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
> new file mode 100644
> index 0000000..52c6f66
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/board.c
> @@ -0,0 +1,136 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <debug_uart.h>
> +#include <ram.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/boot_mode.h>
> +#ifdef CONFIG_DM_REGULATOR
> +#include <power/regulator.h>
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
> +int fb_set_reboot_flag(void)
> +{
> +	printf("Setting reboot to fastboot flag ...\n");
> +	/* Set boot mode to fastboot */
> +	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
> +
> +	return 0;
> +}
> +
> +#define FASTBOOT_KEY_GPIO 43 /* GPIO1_B3 */
> +static int fastboot_key_pressed(void)
> +{
> +	gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
> +	gpio_direction_input(FASTBOOT_KEY_GPIO);
> +	return !gpio_get_value(FASTBOOT_KEY_GPIO);
> +}
> +#endif
> +
> +__weak int rk_board_init(void)
> +{
> +	return 0;
> +}
> +
> +__weak int rk_board_late_init(void)
> +{
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
> +	if (fastboot_key_pressed()) {
> +		printf("fastboot key pressed!\n");
> +		fb_set_reboot_flag();
> +	}
> +#endif
> +
> +#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
> +	setup_boot_mode();
> +#endif
> +
> +	return rk_board_late_init();
> +}
> +
> +int board_init(void)
> +{
> +	int ret;
> +
> +#if !defined(CONFIG_SUPPORT_SPL)
> +	board_debug_uart_init();
> +#endif
> +#ifdef CONFIG_DM_REGULATOR
> +	ret = regulators_enable_boot_on(false);
> +	if (ret)
> +		debug("%s: Cannot enable boot on regulator\n", __func__);
> +#endif
> +
> +	return rk_board_init();
> +}
> +
> +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
> +void enable_caches(void)
> +{
> +	/* Enable D-cache. I-cache is already enabled in start.S */
> +	dcache_enable();
> +}
> +#endif
> +
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data otg_data = {
> +	.rx_fifo_sz	= 512,
> +	.np_tx_fifo_sz	= 16,
> +	.tx_fifo_sz	= 128,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	int node;
> +	const char *mode;
> +	bool matched = false;
> +	const void *blob = gd->fdt_blob;
> +
> +	/* find the usb_otg node */
> +	node = fdt_node_offset_by_compatible(blob, -1,
> +					     "snps,dwc2");
> +
> +	while (node > 0) {
> +		mode = fdt_getprop(blob, node, "dr_mode", NULL);
> +		if (mode && strcmp(mode, "otg") == 0) {
> +			matched = true;
> +			break;
> +		}
> +
> +		node = fdt_node_offset_by_compatible(blob, node,
> +						     "snps,dwc2");
> +	}
> +	if (!matched) {
> +		debug("Not found usb_otg device\n");
> +		return -ENODEV;
> +	}
> +	otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> +
> +	return dwc2_udc_probe(&otg_data);
> +}

This function is already caught in review in another thread (where both I 
and Simon had complained about the way the device-tree is traversed from 
here).

Now this change would suddenly adds this code to all our SOCs instead of 
cleaning this up... in other words, this is our last change to clean it up 
w/o people depending on it: please do so.

Could we do something similar to
 	https://patchwork.ozlabs.org/patch/890968/
here?

> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> +	return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
> new file mode 100644
> index 0000000..3c10b63
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/spl.c
> @@ -0,0 +1,195 @@
> +/*
> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd

Given that there's quite a bit of code that we contributed (e.g. the 
entire spl_was_booted_from logic), I'd expect you to also (additionally) 
retain the Theobroma Systems copyright.

> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch-rockchip/sys_proto.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_ROCKCHIP_IRAM_START_ADDR + 0x10)

This should be a const-variable down where it's needed.
Plus, you'll need to document somewhere that you expect this at offset 
0x10 from the start of the IRAM on every SOC.

> +void board_return_to_bootrom(void)
> +{
> +	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> +}
> +
> +__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> +};

Having this defined as __weak here is an invitation for future trouble.
Someone will eventually forget to define it.  Better to rely on a 
link-time error to stop people from abusing this.

> +
> +const char *board_spl_was_booted_from(void)
> +{
> +	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
> +	const char *bootdevice_ofpath = NULL;
> +
> +	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
> +		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
> +
> +	if (bootdevice_ofpath)
> +		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
> +		      __func__, bootdevice_brom_id, bootdevice_ofpath);
> +	else
> +		debug("%s: failed to resolve brom_bootdevice_id %x\n",
> +		      __func__, bootdevice_brom_id);
> +
> +	return bootdevice_ofpath;
> +}
> +
> +u32 spl_boot_device(void)
> +{
> +	u32 boot_device = BOOT_DEVICE_MMC1;
> +
> +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
> +		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
> +		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
> +	return BOOT_DEVICE_SPI;
> +#endif

This is not how it should be: if this is a common file, then there should 
be a common way to do this instead of having target-specific #ifdefs in 
here.

> +	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
> +		return BOOT_DEVICE_BOOTROM;
> +
> +	return boot_device;
> +}
> +
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> +	return MMCSD_MODE_RAW;
> +}
> +
> +__weak void rockchip_stimer_init(void)
> +{
> +#ifndef CONFIG_ARM64
> +	asm volatile("mcr p15, 0, %0, c14, c0, 0"
> +		     : : "r"(COUNTER_FREQUENCY));
> +#endif
> +	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
> +	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
> +	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
> +	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
> +}
> +
> +__weak int arch_cpu_init(void)
> +{
> +	return 0;
> +}
> +
> +__weak int rk_board_init_f(void)
> +{
> +	return 0;
> +}

This doesn't really help in modularising our board-support and I am not a 
fan of adding something like 'rk_board_init_f' in the first place.

Instead this should be implemented in a way that actually makes the code 
structure easier and more resilient for the future (having __weak 
functions at the architecture-level doesn't really help)... in fact the 
only other uses of __weak in the U-Boot source-base are within SPL, as 
there's no other way to provide hooks there.

> +
> +void board_init_f(ulong dummy)
> +{
> +#ifdef CONFIG_SPL_FRAMEWORK
> +	int ret;
> +#if !defined(CONFIG_SUPPORT_TPL)
> +	struct udevice *dev;
> +#endif
> +#endif
> +
> +#if !defined(CONFIG_SUPPORT_TPL)
> +	rockchip_stimer_init();
> +	arch_cpu_init();
> +#endif
> +#define EARLY_UART
> +#if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
> +	/*
> +	 * Debug UART can be used from here if required:
> +	 *
> +	 * debug_uart_init();
> +	 * printch('a');
> +	 * printhex8(0x1234);
> +	 * printascii("string");
> +	 */
> +	debug_uart_init();
> +	printascii("U-Boot SPL board init");
> +#endif
> +
> +#ifdef CONFIG_SPL_FRAMEWORK
> +	ret = spl_early_init();
> +	if (ret) {
> +		printf("spl_early_init() failed: %d\n", ret);
> +		hang();
> +	}
> +#if !defined(CONFIG_SUPPORT_TPL)
> +	debug("\nspl:init dram\n");
> +	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> +	if (ret) {
> +		printf("DRAM init failed: %d\n", ret);
> +		return;
> +	}
> +#endif
> +	preloader_console_init();
> +#else
> +	/* Some SoCs like rk3036 does not use any frame work */
> +	sdram_init();
> +#endif

This doesn't improve things at all, compared to having multiple files.
In fact, it makes things worse, now that we have to have support for the 
(legacy) sdram_init and the other code.

> +
> +	rk_board_init_f();
> +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
> +	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> +#endif
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_SPL_BOARD_INIT
> +__weak int rk_spl_board_init(void)
> +{
> +	return 0;
> +}
> +
> +static int setup_led(void)
> +{
> +#ifdef CONFIG_SPL_LED
> +	struct udevice *dev;
> +	char *led_name;
> +	int ret;
> +
> +	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
> +	if (!led_name)
> +		return 0;
> +	ret = led_get_by_label(led_name, &dev);
> +	if (ret) {
> +		debug("%s: get=%d\n", __func__, ret);
> +		return ret;
> +	}
> +	ret = led_set_on(dev, 1);
> +	if (ret)
> +		return ret;
> +#endif
> +
> +	return 0;
> +}

Please move this to a separate file, that gets compiled in for 
CONFIG_SPL_LED only.

> +
> +void spl_board_init(void)
> +{
> +	int ret;
> +
> +	ret = setup_led();
> +
> +	if (ret) {
> +		debug("LED ret=%d\n", ret);
> +		hang();
> +	}
> +
> +	rk_spl_board_init();
> +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
> +	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> +#endif
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
> new file mode 100644
> index 0000000..6f9fbaf
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/tpl.c
> @@ -0,0 +1,111 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <ns16550.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <version.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/uart.h>
> +
> +#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
> +void puts(const char *str)
> +{
> +	while (*str)
> +		putc(*str++);
> +}
> +
> +void putc(char c)
> +{
> +	if (c == '\n')
> +		NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
> +
> +	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
> +}
> +#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
> +
> +u32 spl_boot_device(void)
> +{
> +	return BOOT_DEVICE_BOOTROM;
> +}
> +
> +__weak void rockchip_stimer_init(void)
> +{
> +#ifndef CONFIG_ARM64
> +	asm volatile("mcr p15, 0, %0, c14, c0, 0"
> +		     : : "r"(COUNTER_FREQUENCY));
> +#endif
> +	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
> +	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
> +	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
> +	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
> +}
> +
> +__weak int arch_cpu_init(void)
> +{
> +	return 0;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> +	struct udevice *dev;
> +	int ret;
> +
> +	/*
> +	 * Init the timer at the very beginning so that we can get more
> +	 * accurate value from timer_get_boot_us()
> +	 */
> +	rockchip_stimer_init();
> +	arch_cpu_init();
> +#define EARLY_DEBUG
> +#ifdef EARLY_DEBUG
> +	/*
> +	 * Debug UART can be used from here if required:
> +	 *
> +	 * debug_uart_init();
> +	 * printch('a');
> +	 * printhex8(0x1234);
> +	 * printascii("string");
> +	 */
> +	debug_uart_init();
> +	printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
> +		   U_BOOT_TIME ")\n");
> +#endif
> +	ret = spl_early_init();
> +	if (ret) {
> +		debug("spl_early_init() failed: %d\n", ret);
> +		hang();
> +	}
> +
> +	/* Init ARM arch timer */
> +	timer_init();
> +	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> +	if (ret) {
> +		printf("DRAM init failed: %d\n", ret);
> +		return;
> +	}
> +
> +#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT)
> +	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> +#endif
> +}
> +
> +#ifndef CONFIG_SPL_FRAMEWORK
> +/* Place Holders */
> +void board_init_r(gd_t *id, ulong dest_addr)
> +{
> +	/*
> +	 * Function attribute is no-return
> +	 * This Function never executes
> +	 */
> +	while (1)
> +		;
> +}
> +#endif
>

[U-Boot] [U-Boot, 30/36] rockchip: lion-rk3368: remove rockchip timer

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We use ARM generic timer.

A more enlightening commit message, please.

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for comments.

> ---
>
> configs/lion-rk3368_defconfig | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
> index 8a95ce3..89c4d76 100644
> --- a/configs/lion-rk3368_defconfig
> +++ b/configs/lion-rk3368_defconfig
> @@ -88,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
> CONFIG_DEBUG_UART_SKIP_INIT=y
> CONFIG_ROCKCHIP_SPI=y
> CONFIG_SYSRESET=y
> -CONFIG_TIMER=y
> -CONFIG_SPL_TIMER=y
> -CONFIG_TPL_TIMER=y
> -CONFIG_ROCKCHIP_TIMER=y

NAK: The reason to not do this (and to have a DM time for the RK3368) has 
been discussed, when we originally added this: SPL should not be specific 
on the software stack.

Consider the following cases:
1. Boot to Linux (or U-Boot in EL2): this always includes an ATF as the
    next-stage... so no need to setup the secure time here, as ATF will
    take care of this anyway.
2. Boot to U-Boot in EL3 (e.g. from the Miniloader): we shouldn't rely on
    the secure time having been set up (but U-Boot can't do it either, as
    the same binary could either run at EL3 or at EL2).

So the consensus was to not have U-Boot rely on the secure timer to be 
initialised... especially, as it doesn't have to rely on this.

Note that this is also true for the RK3399, but I need to finish up 
further changes to the DRAM init code, as that currently relies on having 
a timebase before the DM timer is available.

> CONFIG_USE_TINY_PRINTF=y
> CONFIG_SPL_TINY_MEMSET=y
> CONFIG_LZO=y
>

[U-Boot] [U-Boot, 29/36] rockchip: rk3368: prepare to use common board file

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> Use common board file and move SoC spec setting into rk3368.c

Please improve the commit message, so the casual reader knows what is 
changed it this patch and why.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for some requested changes.

> ---
>
> arch/arm/mach-rockchip/rk3368-board-spl.c         |  73 ----------
> arch/arm/mach-rockchip/rk3368-board-tpl.c         | 157 ----------------------
> arch/arm/mach-rockchip/rk3368/rk3368.c            | 116 ++++++++++++++--
> board/geekbuying/geekbox/geekbox.c                |   5 -
> board/rockchip/evb_px5/evb-px5.c                  |   5 -
> board/rockchip/sheep_rk3368/sheep_rk3368.c        |   5 -
> board/theobroma-systems/lion_rk3368/lion_rk3368.c |   8 --
> 7 files changed, 106 insertions(+), 263 deletions(-)
> delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
> delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
>
> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
> deleted file mode 100644
> index 8055ae5..0000000
> --- a/arch/arm/mach-rockchip/rk3368-board-spl.c
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/*
> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <debug_uart.h>
> -#include <dm.h>
> -#include <dm/pinctrl.h>
> -#include <ram.h>
> -#include <spl.h>
> -#include <asm/io.h>
> -#include <asm/arch/cru_rk3368.h>
> -#include <asm/arch/grf_rk3368.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/periph.h>
> -#include <asm/arch/timer.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -void board_debug_uart_init(void)
> -{
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> -	struct udevice *pinctrl;
> -	struct udevice *dev;
> -	int ret;
> -
> -	ret = spl_early_init();
> -	if (ret) {
> -		debug("spl_early_init() failed: %d\n", ret);
> -		hang();
> -	}
> -
> -	/* Set up our preloader console */
> -	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> -	if (ret) {
> -		pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
> -		hang();
> -	}
> -
> -	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
> -	if (ret) {
> -		pr_err("%s: failed to set up console UART\n", __func__);
> -		hang();
> -	}
> -
> -	preloader_console_init();
> -
> -	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> -	if (ret) {
> -		debug("DRAM init failed: %d\n", ret);
> -		return;
> -	}
> -}
> -
> -u32 spl_boot_device(void)
> -{
> -	return BOOT_DEVICE_MMC1;
> -}
> -
> -#ifdef CONFIG_SPL_LOAD_FIT
> -int board_fit_config_name_match(const char *name)
> -{
> -	/* Just empty function now - can't decide what to choose */
> -	debug("%s: %s\n", __func__, name);
> -
> -	return 0;
> -}
> -#endif
> diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c
> deleted file mode 100644
> index 60d5aea..0000000
> --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -/*
> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH

If you move all of this code, please make sure that our copyright is 
reflected in the new file.

> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <asm/arch/clock.h>
> -#include <debug_uart.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <spl.h>
> -#include <asm/io.h>
> -#include <asm/arch/bootrom.h>
> -#include <asm/arch/cru_rk3368.h>
> -#include <asm/arch/grf_rk3368.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/timer.h>
> -#include <syscon.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/*
> - * The SPL (and also the full U-Boot stage on the RK3368) will run in
> - * secure mode (i.e. EL3) and an ATF will eventually be booted before
> - * starting up the operating system... so we can initialize the SGRF
> - * here and rely on the ATF installing the final (secure) policy
> - * later.
> - */
> -static inline uintptr_t sgrf_soc_con_addr(unsigned no)
> -{
> -	const uintptr_t SGRF_BASE =
> -		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
> -
> -	return SGRF_BASE + sizeof(u32) * no;
> -}
> -
> -static inline uintptr_t sgrf_busdmac_addr(unsigned no)
> -{
> -	const uintptr_t SGRF_BASE =
> -		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
> -	const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
> -	const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
> -
> -	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
> -}
> -
> -static void sgrf_init(void)
> -{
> -	struct rk3368_cru * const cru =
> -		(struct rk3368_cru * const)rockchip_get_cru();
> -	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
> -	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
> -	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
> -
> -	/* Set all configurable IP to 'non secure'-mode */
> -	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
> -	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
> -	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
> -
> -	/*
> -	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
> -	 * Original comment: "ddr space set no secure mode"
> -	 */
> -	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
> -	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
> -	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
> -
> -	/* Set 'secure dma' to 'non secure'-mode */
> -	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
> -	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
> -
> -	dsb();  /* barrier */
> -
> -	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
> -	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
> -
> -	dsb();  /* barrier */
> -	udelay(10);
> -
> -	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
> -	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
> -}
> -
> -void board_debug_uart_init(void)
> -{
> -	/*
> -	 * N.B.: This is called before the device-model has been
> -	 *       initialised. For this reason, we can not access
> -	 *       the GRF address range using the syscon API.
> -	 */
> -	struct rk3368_grf * const grf =
> -		(struct rk3368_grf * const)0xff770000;
> -
> -	enum {
> -		GPIO2D1_MASK            = GENMASK(3, 2),
> -		GPIO2D1_GPIO            = 0,
> -		GPIO2D1_UART0_SOUT      = (1 << 2),
> -
> -		GPIO2D0_MASK            = GENMASK(1, 0),
> -		GPIO2D0_GPIO            = 0,
> -		GPIO2D0_UART0_SIN       = (1 << 0),
> -	};
> -
> -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> -	/* Enable early UART0 on the RK3368 */
> -	rk_clrsetreg(&grf->gpio2d_iomux,
> -		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
> -	rk_clrsetreg(&grf->gpio2d_iomux,
> -		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
> -#endif
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> -	struct udevice *dev;
> -	int ret;
> -
> -#define EARLY_UART
> -#ifdef EARLY_UART
> -	/*
> -	 * Debug UART can be used from here if required:
> -	 *
> -	 * debug_uart_init();
> -	 * printch('a');
> -	 * printhex8(0x1234);
> -	 * printascii("string");
> -	 */
> -	debug_uart_init();
> -	printascii("U-Boot TPL board init\n");
> -#endif
> -
> -	ret = spl_early_init();
> -	if (ret) {
> -		debug("spl_early_init() failed: %d\n", ret);
> -		hang();
> -	}
> -
> -	/* Reset security, so we can use DMA in the MMC drivers */
> -	sgrf_init();
> -
> -	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> -	if (ret) {
> -		debug("DRAM init failed: %d\n", ret);
> -		return;
> -	}
> -}
> -
> -void board_return_to_bootrom(void)
> -{
> -	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> -}
> -
> -u32 spl_boot_device(void)
> -{
> -	return BOOT_DEVICE_BOOTROM;
> -}
> diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
> index f62d91d..8c0b370 100644
> --- a/arch/arm/mach-rockchip/rk3368/rk3368.c
> +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
> @@ -7,6 +7,7 @@
>
> #include <common.h>
> #include <asm/armv8/mmu.h>
> +#include <asm/arch/bootrom.h>
> #include <asm/io.h>
> #include <asm/arch/clock.h>
> #include <asm/arch/cru_rk3368.h>
> @@ -52,16 +53,10 @@ static struct mm_region rk3368_mem_map[] = {
>
> struct mm_region *mem_map = rk3368_mem_map;
>
> -int dram_init_banksize(void)
> -{
> -	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
> -
> -	/* Reserve 0x200000 for ATF bl31 */
> -	gd->bd->bi_dram[0].start = 0x200000;
> -	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
> -
> -	return 0;
> -}
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> +	[BROM_BOOTSOURCE_EMMC] = "/dwmmc at ff0f0000",
> +	[BROM_BOOTSOURCE_SD] = "/dwmmc at ff0c0000",
> +};
>
> #ifdef CONFIG_ARCH_EARLY_INIT_R
> static int mcu_init(void)
> @@ -97,3 +92,104 @@ int arch_early_init_r(void)
> 	return mcu_init();
> }
> #endif
> +
> +#ifdef CONFIG_SPL_BUILD
> +/*
> + * The SPL (and also the full U-Boot stage on the RK3368) will run in
> + * secure mode (i.e. EL3) and an ATF will eventually be booted before
> + * starting up the operating system... so we can initialize the SGRF
> + * here and rely on the ATF installing the final (secure) policy
> + * later.
> + */
> +static inline uintptr_t sgrf_soc_con_addr(u32 no)
> +{
> +	const uintptr_t SGRF_BASE =
> +		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
> +
> +	return SGRF_BASE + sizeof(u32) * no;
> +}
> +
> +static inline uintptr_t sgrf_busdmac_addr(u32 no)
> +{
> +	const uintptr_t SGRF_BASE =
> +		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
> +	const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
> +	const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
> +
> +	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
> +}
> +
> +static void sgrf_init(void)
> +{
> +	struct rk3368_cru * const cru =
> +		(struct rk3368_cru * const)rockchip_get_cru();
> +	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
> +	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
> +	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
> +
> +	/* Set all configurable IP to 'non secure'-mode */
> +	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
> +	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
> +	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
> +
> +	/*
> +	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
> +	 * Original comment: "ddr space set no secure mode"
> +	 */
> +	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
> +	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
> +	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
> +
> +	/* Set 'secure dma' to 'non secure'-mode */
> +	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
> +	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
> +
> +	dsb();  /* barrier */
> +
> +	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
> +	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
> +
> +	dsb();  /* barrier */
> +	udelay(10);
> +
> +	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
> +	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
> +}
> +
> +void board_debug_uart_init(void)
> +{
> +	/*
> +	 * N.B.: This is called before the device-model has been
> +	 *       initialised. For this reason, we can not access
> +	 *       the GRF address range using the syscon API.
> +	 */
> +	struct rk3368_grf * const grf =
> +		(struct rk3368_grf * const)0xff770000;
> +
> +	enum {
> +		GPIO2D1_MASK            = GENMASK(3, 2),
> +		GPIO2D1_GPIO            = 0,
> +		GPIO2D1_UART0_SOUT      = (1 << 2),
> +
> +		GPIO2D0_MASK            = GENMASK(1, 0),
> +		GPIO2D0_GPIO            = 0,
> +		GPIO2D0_UART0_SIN       = (1 << 0),
> +	};
> +
> +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> +	/* Enable early UART0 on the RK3368 */
> +	rk_clrsetreg(&grf->gpio2d_iomux,
> +		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
> +	rk_clrsetreg(&grf->gpio2d_iomux,
> +		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
> +#endif
> +}
> +
> +int arch_cpu_init(void)
> +{
> +	/* Reset security, so we can use DMA in the MMC drivers */
> +	sgrf_init();
> +
> +	return 0;
> +}
> +#endif
> diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
> index 88b67f9..d682349 100644
> --- a/board/geekbuying/geekbox/geekbox.c
> +++ b/board/geekbuying/geekbox/geekbox.c
> @@ -7,8 +7,3 @@
> #include <common.h>
>
> DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_init(void)
> -{
> -	return 0;
> -}

Why even keep this file around?

> diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
> index 6a47642..ec3d27e 100644
> --- a/board/rockchip/evb_px5/evb-px5.c
> +++ b/board/rockchip/evb_px5/evb-px5.c
> @@ -4,8 +4,3 @@
>  * SPDX-License-Identifier:     GPL-2.0+
>  */
> #include <common.h>
> -
> -int board_init(void)
> -{
> -	return 0;
> -}

Why even keep this file around?

> diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
> index 17adb02..ff2d2d2 100644
> --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c
> +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c
> @@ -15,8 +15,3 @@ int mach_cpu_init(void)
> {
> 	return 0;
> }
> -
> -int board_init(void)
> -{
> -	return 0;
> -}
> diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
> index 73b1488..025692b 100644
> --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c
> +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
> @@ -7,9 +7,6 @@
> #include <dm.h>
> #include <ram.h>
> #include <asm/io.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/grf_rk3368.h>
> -#include <asm/arch/timer.h>
> #include <syscon.h>
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -18,8 +15,3 @@ int mach_cpu_init(void)
> {
> 	return 0;
> }
> -
> -int board_init(void)
> -{
> -	return 0;
> -}
>

[U-Boot] [U-Boot, 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> pre-loader console in SPL needs UART.

Please describe what the change is (with this I still need to look at the 
diff).

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Just make this a separate patch, as I can apply this without the remainder 
of the series.

> ---
>
> arch/arm/dts/rk3399-firefly.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
> index f134c00..a007fa1 100644
> --- a/arch/arm/dts/rk3399-firefly.dts
> +++ b/arch/arm/dts/rk3399-firefly.dts
> @@ -648,6 +648,7 @@
> };
>
> &uart2 {
> +	u-boot,dm-pre-reloc;
> 	status = "okay";
> };

This should go to *-u-boot.dtsi.

>
>

[U-Boot] [U-Boot, 16/36] rockchip: sdram-common: add api to pass dram info to trust os

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> Trust OS decode this info like this:
> https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
> We have to set a available value, or else we get error info from
> Trust OS like this:
> "ERROR:   over or zero region, nr=3145987, max=10"

Please describe what changes the patch makes.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for requested changes.

> ---
>
> arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 ++++
> arch/arm/mach-rockchip/sdram_common.c             | 21 +++++++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
> index fec8586..55c6b81 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
> @@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg);
>
> /* Called by U-Boot board_init_r for Rockchip SoCs */
> int dram_init(void);
> +
> +/* Write ddr param to a known place for trustos */
> +int rockchip_setup_ddr_param(struct ram_info *info);
> +
> #endif
> diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> index 76dbdc8..3a71f09 100644
> --- a/arch/arm/mach-rockchip/sdram_common.c
> +++ b/arch/arm/mach-rockchip/sdram_common.c
> @@ -12,6 +12,15 @@
> #include <dm/uclass-internal.h>
>
> DECLARE_GLOBAL_DATA_PTR;
> +struct ddr_param {
> +	u32 count;
> +	u32 reserved;
> +	u64 bank_addr;
> +	u64 bank_size;
> +};
> +
> +#define PARAM_DRAM_INFO_OFFSET 0x2000000

Having this a fixed offset feels a bit hackish... especially as this is 
now implemented for all SOCs.

> +
> size_t rockchip_sdram_size(phys_addr_t reg)
> {
> 	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
> @@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size)
>
> 	return (gd->ram_top > top) ? top : gd->ram_top;
> }
> +
> +int rockchip_setup_ddr_param(struct ram_info *info)
> +{
> +	struct ddr_param *dinfo = (struct ddr_param *)CONFIG_SYS_SDRAM_BASE +
> +					PARAM_DRAM_INFO_OFFSET;
> +
> +	dinfo->count = 1;
> +	dinfo->bank_addr = info->base;
> +	dinfo->bank_size = info->size;
> +
> +	return 0;
> +}

This setup should only be performed when preparing the system to enter the 
ATF.  So you will need to hook it into path where the ATF is prepared for 
being jumped into.

I would further prefer (but this is a personal preference) to eventually 
move to using the FDT we inject into the ATF to convey this information.

>

[U-Boot] [U-Boot, 12/36] rockchip: rk3036: sdram: use udelay instead of rockchip_udelay

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We are going to remove rockchip_udelay after enable arch timer.

Please use commit message that better describes what this commit is 
changing.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> index e5393ec..ce3f09a 100644
> --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> @@ -10,7 +10,6 @@
> #include <asm/arch/grf_rk3036.h>
> #include <asm/arch/hardware.h>
> #include <asm/arch/sdram_rk3036.h>
> -#include <asm/arch/timer.h>
> #include <asm/arch/uart.h>
>
> /*
> @@ -346,7 +345,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
>
> 	/* waiting for pll lock */
> 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
> -		rockchip_udelay(1);
> +		udelay(1);
>
> 	/* PLL enter normal-mode */
> 	rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
> @@ -374,25 +373,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
> 			1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
> 			1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
>
> -	rockchip_udelay(10);
> +	udelay(10);
>
> 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
> 						  1 << DDRPHY_SRST_SHIFT);
> -	rockchip_udelay(10);
> +	udelay(10);
>
> 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
> 						  1 << DDRCTRL_SRST_SHIFT);
> -	rockchip_udelay(10);
> +	udelay(10);
>
> 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
> 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
> 			0 << SOFT_RESET_SHIFT);
> -	rockchip_udelay(10);
> +	udelay(10);
> 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
> 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
> 			3 << SOFT_RESET_SHIFT);
>
> -	rockchip_udelay(1);
> +	udelay(1);
> }
>
> void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
> @@ -445,7 +444,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl,
> 			 u32 rank, u32 cmd, u32 arg)
> {
> 	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
> -	rockchip_udelay(1);
> +	udelay(1);
> 	while (readl(&pctl->mcmd) & START_CMD)
> 		;
> }
> @@ -455,7 +454,7 @@ static void memory_init(struct rk3036_sdram_priv *priv)
> 	struct rk3036_ddr_pctl *pctl = priv->pctl;
>
> 	send_command(pctl, 3, DESELECT_CMD, 0);
> -	rockchip_udelay(1);
> +	udelay(1);
> 	send_command(pctl, 3, PREA_CMD, 0);
> 	send_command(pctl, 3, MRS_CMD,
> 		     (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
> @@ -493,7 +492,7 @@ static void data_training(struct rk3036_sdram_priv *priv)
> 	clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
> 			DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
>
> -	rockchip_udelay(1);
> +	udelay(1);
> 	while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
> 		(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
> 		;
>

[U-Boot] [U-Boot, 14/36] rockchip: rk3036: prepare to use commong board file

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> Move some soc spec setting into rk3036.c

Please provide a summary of the changes in your commit message.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3036-board.c              | 104 ---------------------
> arch/arm/mach-rockchip/rk3036/Makefile             |   2 +-
> .../{rk3036-board-spl.c => rk3036/rk3036.c}        |  41 ++------
> arch/arm/mach-rockchip/rk3036/sdram_rk3036.c       |  14 +++
> 4 files changed, 24 insertions(+), 137 deletions(-)
> delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
> rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)
>
> diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
> deleted file mode 100644
> index a5d2571..0000000
> --- a/arch/arm/mach-rockchip/rk3036-board.c
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -/*
> - * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <clk.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <asm/io.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/periph.h>
> -#include <asm/arch/grf_rk3036.h>
> -#include <asm/arch/boot_mode.h>
> -#include <asm/arch/sdram_rk3036.h>
> -#include <asm/gpio.h>
> -#include <dm/pinctrl.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -__weak int rk_board_late_init(void)
> -{
> -	return 0;
> -}
> -
> -int board_late_init(void)
> -{
> -	setup_boot_mode();
> -
> -	return rk_board_late_init();
> -}
> -
> -int board_init(void)
> -{
> -	return 0;
> -}
> -
> -#if !CONFIG_IS_ENABLED(RAM)
> -/*
> - * When CONFIG_RAM is enabled, the dram_init() function is implemented
> - * in sdram_common.c.
> - */
> -int dram_init(void)
> -{
> -	gd->ram_size = sdram_size();
> -
> -	return 0;
> -}
> -#endif
> -
> -#ifndef CONFIG_SYS_DCACHE_OFF
> -void enable_caches(void)
> -{
> -	/* Enable D-cache. I-cache is already enabled in start.S */
> -	dcache_enable();
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> -#include <usb.h>
> -#include <usb/dwc2_udc.h>
> -
> -static struct dwc2_plat_otg_data rk3036_otg_data = {
> -	.rx_fifo_sz	= 512,
> -	.np_tx_fifo_sz	= 16,
> -	.tx_fifo_sz	= 128,
> -};
> -
> -int board_usb_init(int index, enum usb_init_type init)
> -{
> -	int node;
> -	const char *mode;
> -	bool matched = false;
> -	const void *blob = gd->fdt_blob;
> -
> -	/* find the usb_otg node */
> -	node = fdt_node_offset_by_compatible(blob, -1,
> -					"rockchip,rk3288-usb");
> -
> -	while (node > 0) {
> -		mode = fdt_getprop(blob, node, "dr_mode", NULL);
> -		if (mode && strcmp(mode, "otg") == 0) {
> -			matched = true;
> -			break;
> -		}
> -
> -		node = fdt_node_offset_by_compatible(blob, node,
> -					"rockchip,rk3288-usb");
> -	}
> -	if (!matched) {
> -		debug("Not found usb_otg device\n");
> -		return -ENODEV;
> -	}
> -	rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> -
> -	return dwc2_udc_probe(&rk3036_otg_data);
> -}
> -
> -int board_usb_cleanup(int index, enum usb_init_type init)
> -{
> -	return 0;
> -}
> -#endif
> diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile
> index 20d28f7..8a144d1 100644
> --- a/arch/arm/mach-rockchip/rk3036/Makefile
> +++ b/arch/arm/mach-rockchip/rk3036/Makefile
> @@ -4,7 +4,7 @@
> # SPDX-License-Identifier:     GPL-2.0+
> #
>
> -obj-y += clk_rk3036.o
> +obj-y += rk3036.o clk_rk3036.o
>
> ifndef CONFIG_SPL_BUILD
> obj-y += syscon_rk3036.o
> diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036/rk3036.c
> similarity index 50%
> rename from arch/arm/mach-rockchip/rk3036-board-spl.c
> rename to arch/arm/mach-rockchip/rk3036/rk3036.c
> index 550e3a1..39cc43b 100644
> --- a/arch/arm/mach-rockchip/rk3036-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
> @@ -1,28 +1,22 @@
> /*
> - * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2017 Rockchip Electronics Co., Ltd
>  *
>  * SPDX-License-Identifier:     GPL-2.0+
>  */
> -
> -#include <common.h>
> -#include <debug_uart.h>
> #include <asm/io.h>
> #include <asm/arch/bootrom.h>
> -#include <asm/arch/grf_rk3036.h>
> #include <asm/arch/hardware.h>
> -#include <asm/arch/sdram_rk3036.h>
> -#include <asm/arch/timer.h>
> -#include <asm/arch/uart.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> +#include <asm/arch/grf_rk3036.h>
> #define GRF_BASE	0x20008000
>
> -#define DEBUG_UART_BASE	0x20068000
> -
> -void board_init_f(ulong dummy)
> +#ifdef CONFIG_SPL_BUILD
> +int arch_cpu_init(void)
> +{
> +	return 0;
> +}
> +#endif
> +void board_debug_uart_init(void)
> {
> -#ifdef EARLY_DEBUG
> 	struct rk3036_grf * const grf = (void *)GRF_BASE;
> 	/*
> 	 * NOTE: sd card and debug uart use same iomux in rk3036,
> @@ -34,22 +28,5 @@ void board_init_f(ulong dummy)
> 		     GPIO1C2_MASK << GPIO1C2_SHIFT,
> 		     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
> 		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
> -	debug_uart_init();
> -#endif
> -	rockchip_timer_init();
> -	sdram_init();
> -
> -	/* return to maskrom */
> -	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> -}
>
> -/* Place Holders */
> -void board_init_r(gd_t *id, ulong dest_addr)
> -{
> -	/*
> -	 * Function attribute is no-return
> -	 * This Function never executes
> -	 */
> -	while (1)
> -		;
> }
> diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> index ce3f09a..a4fb3ae 100644
> --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
> @@ -11,6 +11,7 @@
> #include <asm/arch/hardware.h>
> #include <asm/arch/sdram_rk3036.h>
> #include <asm/arch/uart.h>
> +DECLARE_GLOBAL_DATA_PTR;
>
> /*
>  * we can not fit the code to access the device tree in SPL
> @@ -764,3 +765,16 @@ void sdram_init(void)
> 	move_to_access_state(&sdram_priv);
> 	dram_cfg_rbc(&sdram_priv);
> }
> +
> +#if !CONFIG_IS_ENABLED(RAM)
> +/*
> + * When CONFIG_RAM is enabled, the dram_init() function is implemented
> + * in sdram_common.c.
> + */
> +int dram_init(void)
> +{
> +	gd->ram_size = sdram_size();
> +
> +	return 0;
> +}
> +#endif
>

[U-Boot] [U-Boot, 15/36] rockchip: declare sdram_init() in common header

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We need a dedicate sdram_init() function for those SoCS not
> using SPL_FRAMEWORK.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
> index 3617ac2..7b7e336 100644
> --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
> +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
> @@ -7,5 +7,8 @@
> #ifndef _ASM_ARCH_SYS_PROTO_H
> #define _ASM_ARCH_SYS_PROTO_H
>
> +#ifndef CONFIG_SPL_FRAMEWORK
> +void sdram_init(void);

Please provide documentation for this function, as it is exposed in a 
header-file.

> +#endif
>
> #endif /* _ASM_ARCH_SYS_PROTO_H */
>

[U-Boot] [U-Boot, 17/36] rockchip: sdram_common: add common dram_init_banksize

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> dram_init_banksize() can be common used by all SoCs, move it into
> sdram_common.c
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/sdram_common.c | 63 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 62 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> index 3a71f09..ff86096 100644
> --- a/arch/arm/mach-rockchip/sdram_common.c
> +++ b/arch/arm/mach-rockchip/sdram_common.c
> @@ -21,13 +21,74 @@ struct ddr_param {
>
> #define PARAM_DRAM_INFO_OFFSET 0x2000000
>
> +#define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)

This isn't covered by what you commit message states as content for this 
patch.

> +
> +struct tos_parameter_t {
> +	u32 version;
> +	u32 checksum;
> +	struct {
> +		char name[8];
> +		s64 phy_addr;
> +		u32 size;
> +		u32 flags;
> +	} tee_mem;
> +	struct {
> +		char name[8];
> +		s64 phy_addr;
> +		u32 size;
> +		u32 flags;
> +	} drm_mem;
> +	s64 reserve[8];
> +};
> +
> +int dram_init_banksize(void)
> +{
> +	size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
> +			 gd->ram_top);
> +
> +#ifdef CONFIG_ARM64
> +	/* Reserve 0x200000 for ATF bl31 */
> +	gd->bd->bi_dram[0].start = 0x200000;
> +	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;

This should only be done when preparing to start a
 	IH_OS_ARM_TRUSTED_FIRMWARE.

> +#else
> +#ifdef CONFIG_SPL_OPTEE

I don't think that this CONFIG_SPL_OPTEE was what the comments in the 
OPTEE thread have arrived at... please check again.

Just as an unreleated comment/reminder: you still need to revise the other 
series as per the comments and final decision on how to implement it.

> +	struct tos_parameter_t *tos_parameter;
> +
> +	tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
> +			TRUST_PARAMETER_OFFSET);
> +
> +	if (tos_parameter->tee_mem.flags == 1) {

Please describe what this 'flags' member means and how it's encoded.

> +		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> +		gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
> +					- CONFIG_SYS_SDRAM_BASE;
> +		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
> +					tos_parameter->tee_mem.size;
> +		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
> +					+ top - gd->bd->bi_dram[1].start;
> +	} else {
> +		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> +		gd->bd->bi_dram[0].size = 0x8400000;
> +		/* Reserve 32M for OPTEE with TA */
> +		gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
> +					+ gd->bd->bi_dram[0].size + 0x2000000;
> +		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
> +					+ top - gd->bd->bi_dram[1].start;
> +	}

This should again only be done, when the appropriate IH_OS_* is entered.

> +#else
> +	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> +	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;

This should be the default (so you can remove the #if paths) once you make 
sure that the other paths are actually called for entering the particular 
IH_OS_* types.

> +#endif
> +#endif
> +
> +	return 0;
> +}
> +
> size_t rockchip_sdram_size(phys_addr_t reg)
> {
> 	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
> 	size_t chipsize_mb = 0;
> 	size_t size_mb = 0;
> 	u32 ch;
> -

Ok, but not really needed (unless you want to do a separate 'cosmetic' or 
'whitespace' patch.  Touching an unrelated function is usually a bad idea.

> 	u32 sys_reg = readl(reg);
> 	u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
> 		       & SYS_REG_NUM_CH_MASK);
>

[U-Boot] [U-Boot, 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We use ARM arch timer instead.



>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> include/configs/rk3188_common.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
> index 30c150e..7dddf11 100644
> --- a/include/configs/rk3188_common.h
> +++ b/include/configs/rk3188_common.h
> @@ -17,9 +17,6 @@
> #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
> #define CONFIG_SYS_CBSIZE		1024
>
> -#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
> -#define CONFIG_SYS_TIMER_BASE		0x2000e000 /* TIMER3 */
> -#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
> #define CONFIG_SYS_TIMER_COUNTS_DOWN
>
> #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
>

[U-Boot] [U-Boot, 21/36] rockchip: rk3128: prepare use common board file

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> remoe rk3128 board file and move SoC spec setting into rk3128.c

'Remove'?
Also: please elaborate on what this patch is doing.

>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Many comments agains the similar changes also apply here.

> ---
>
> arch/arm/mach-rockchip/rk3128-board.c | 127 ----------------------------------
> 1 file changed, 127 deletions(-)
> delete mode 100644 arch/arm/mach-rockchip/rk3128-board.c
>
> diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
> deleted file mode 100644
> index 2e8393d..0000000
> --- a/arch/arm/mach-rockchip/rk3128-board.c
> +++ /dev/null
> @@ -1,127 +0,0 @@
> -/*
> - * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -#include <common.h>
> -#include <clk.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <syscon.h>
> -#include <asm/io.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/periph.h>
> -#include <asm/arch/grf_rk3128.h>
> -#include <asm/arch/boot_mode.h>
> -#include <asm/arch/timer.h>
> -#include <power/regulator.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -__weak int rk_board_late_init(void)
> -{
> -	return 0;
> -}
> -
> -int board_late_init(void)
> -{
> -	setup_boot_mode();
> -
> -	return rk_board_late_init();
> -}
> -
> -int board_init(void)
> -{
> -	int ret = 0;
> -
> -	rockchip_timer_init();
> -
> -	ret = regulators_enable_boot_on(false);
> -	if (ret) {
> -		debug("%s: Cannot enable boot on regulator\n", __func__);
> -		return ret;
> -	}
> -
> -	return 0;
> -}
> -
> -int dram_init_banksize(void)
> -{
> -	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> -	gd->bd->bi_dram[0].size = 0x8400000;
> -	/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
> -	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
> -				+ gd->bd->bi_dram[0].size + 0xe00000;
> -	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
> -				+ gd->ram_size - gd->bd->bi_dram[1].start;
> -
> -	return 0;
> -}
> -
> -#ifndef CONFIG_SYS_DCACHE_OFF
> -void enable_caches(void)
> -{
> -	/* Enable D-cache. I-cache is already enabled in start.S */
> -	dcache_enable();
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> -#include <usb.h>
> -#include <usb/dwc2_udc.h>
> -
> -static struct dwc2_plat_otg_data rk3128_otg_data = {
> -	.rx_fifo_sz	= 512,
> -	.np_tx_fifo_sz	= 16,
> -	.tx_fifo_sz	= 128,
> -};
> -
> -int board_usb_init(int index, enum usb_init_type init)
> -{
> -	int node;
> -	const char *mode;
> -	bool matched = false;
> -	const void *blob = gd->fdt_blob;
> -
> -	/* find the usb_otg node */
> -	node = fdt_node_offset_by_compatible(blob, -1,
> -					     "rockchip,rk3128-usb");
> -
> -	while (node > 0) {
> -		mode = fdt_getprop(blob, node, "dr_mode", NULL);
> -		if (mode && strcmp(mode, "otg") == 0) {
> -			matched = true;
> -			break;
> -		}
> -
> -		node = fdt_node_offset_by_compatible(blob, node,
> -						     "rockchip,rk3128-usb");
> -	}
> -	if (!matched) {
> -		debug("Not found usb_otg device\n");
> -		return -ENODEV;
> -	}
> -	rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> -
> -	return dwc2_udc_probe(&rk3128_otg_data);
> -}
> -
> -int board_usb_cleanup(int index, enum usb_init_type init)
> -{
> -	return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
> -int fb_set_reboot_flag(void)
> -{
> -	struct rk3128_grf *grf;
> -
> -	printf("Setting reboot to fastboot flag ...\n");
> -	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> -	/* Set boot mode to fastboot */
> -	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
> -
> -	return 0;
> -}
> -#endif
>

[U-Boot] [U-Boot, 24/36] armv8: add timer_get_boot_us() for generic timer

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> We need timer_get_boot_us() for boot stage if we use generic timer only.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for requested changes/questions.

> ---
>
> arch/arm/cpu/armv8/generic_timer.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
> index a2dda33..d96217e 100644
> --- a/arch/arm/cpu/armv8/generic_timer.c
> +++ b/arch/arm/cpu/armv8/generic_timer.c
> @@ -7,6 +7,7 @@
>
> #include <common.h>
> #include <command.h>
> +#include <div64.h>
> #include <asm/system.h>
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -52,6 +53,11 @@ uint64_t get_ticks(void)
> 	return ticks;
> }
>
> +ulong timer_get_boot_us(void)
> +{
> +	return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
> +}
> +

Can we be sure that this does never conflict with what is added by another 
timer implementation (e.g. DM_TIMER)?  If not, you may have to add some 
additional infrastructure to allow selection of what timer is the 
boot-timer.

> unsigned long usec2ticks(unsigned long usec)
> {
> 	ulong ticks;
>

[U-Boot] [U-Boot, 31/36] rockchip: rk3399: prepare to use common board file

[Philipp Tomsich]

On Tue, 27 Mar 2018, Kever Yang wrote:

> Use common board file and move SoC spec setting into rk3399.c
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

See below for a few comments.
I'll review again, once this series is somewhat more mature...

> ---
>
> arch/arm/mach-rockchip/rk3399-board-spl.c         | 179 ----------------------
> arch/arm/mach-rockchip/rk3399-board.c             |  14 --
> arch/arm/mach-rockchip/rk3399/rk3399.c            |  86 +++++++++--
> board/rockchip/evb_rk3399/evb-rk3399.c            |  56 ++++---
> board/theobroma-systems/puma_rk3399/puma-rk3399.c |  17 +-
> 5 files changed, 103 insertions(+), 249 deletions(-)
> delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
> delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c
>
> diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
> deleted file mode 100644
> index d35990e..0000000
> --- a/arch/arm/mach-rockchip/rk3399-board-spl.c
> +++ /dev/null
> @@ -1,179 +0,0 @@
> -/*
> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH

Please make sure when moving code we contributed, that our copyright shows 
up in the new location you are moving this to.

> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <asm/arch/bootrom.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/grf_rk3399.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/periph.h>
> -#include <asm/io.h>
> -#include <debug_uart.h>
> -#include <dm.h>
> -#include <dm/pinctrl.h>
> -#include <ram.h>
> -#include <spl.h>
> -#include <syscon.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -void board_return_to_bootrom(void)
> -{
> -	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> -}
> -
> -static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> -	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
> -	[BROM_BOOTSOURCE_SPINOR] = "/spi at ff1d0000",
> -	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
> -};
> -
> -const char *board_spl_was_booted_from(void)
> -{
> -	u32  bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
> -	const char *bootdevice_ofpath = NULL;
> -
> -	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
> -		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
> -
> -	if (bootdevice_ofpath)
> -		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
> -		      __func__, bootdevice_brom_id, bootdevice_ofpath);
> -	else
> -		debug("%s: failed to resolve brom_bootdevice_id %x\n",
> -		      __func__, bootdevice_brom_id);
> -
> -	return bootdevice_ofpath;
> -}
> -
> -u32 spl_boot_device(void)
> -{
> -	u32 boot_device = BOOT_DEVICE_MMC1;
> -
> -	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
> -		return BOOT_DEVICE_BOOTROM;
> -
> -	return boot_device;
> -}
> -
> -#define TIMER_CHN10_BASE	0xff8680a0
> -#define TIMER_END_COUNT_L	0x00
> -#define TIMER_END_COUNT_H	0x04
> -#define TIMER_INIT_COUNT_L	0x10
> -#define TIMER_INIT_COUNT_H	0x14
> -#define TIMER_CONTROL_REG	0x1c
> -
> -#define TIMER_EN	0x1
> -#define	TIMER_FMODE	(0 << 1)
> -#define	TIMER_RMODE	(1 << 1)
> -
> -void secure_timer_init(void)
> -{
> -	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
> -	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
> -	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
> -	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
> -	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
> -}
> -
> -void board_debug_uart_init(void)
> -{
> -#define GRF_BASE	0xff770000
> -	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
> -
> -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> -	/* Enable early UART0 on the RK3399 */
> -	rk_clrsetreg(&grf->gpio2c_iomux,
> -		     GRF_GPIO2C0_SEL_MASK,
> -		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
> -	rk_clrsetreg(&grf->gpio2c_iomux,
> -		     GRF_GPIO2C1_SEL_MASK,
> -		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
> -#else
> -	/* Enable early UART2 channel C on the RK3399 */
> -	rk_clrsetreg(&grf->gpio4c_iomux,
> -		     GRF_GPIO4C3_SEL_MASK,
> -		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
> -	rk_clrsetreg(&grf->gpio4c_iomux,
> -		     GRF_GPIO4C4_SEL_MASK,
> -		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
> -	/* Set channel C as UART2 input */
> -	rk_clrsetreg(&grf->soc_con7,
> -		     GRF_UART_DBG_SEL_MASK,
> -		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
> -#endif
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> -	struct udevice *pinctrl;
> -	struct udevice *dev;
> -	struct rk3399_pmusgrf_regs *sgrf;
> -	struct rk3399_grf_regs *grf;
> -	int ret;
> -
> -#define EARLY_UART
> -#ifdef EARLY_UART
> -	/*
> -	 * Debug UART can be used from here if required:
> -	 *
> -	 * debug_uart_init();
> -	 * printch('a');
> -	 * printhex8(0x1234);
> -	 * printascii("string");
> -	 */
> -	debug_uart_init();
> -	printascii("U-Boot SPL board init");
> -#endif
> -
> -	ret = spl_early_init();
> -	if (ret) {
> -		debug("spl_early_init() failed: %d\n", ret);
> -		hang();
> -	}
> -
> -	/*
> -	 * Disable DDR and SRAM security regions.
> -	 *
> -	 * As we are entered from the BootROM, the region from
> -	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
> -	 * be protected. This will cause issues with the DW_MMC
> -	 * driver, which tries to DMA from/to the stack (likely)
> -	 * located in this range.
> -	 */
> -	sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
> -	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
> -	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
> -
> -	/*  eMMC clock generator: disable the clock multipilier */
> -	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> -	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
> -
> -	secure_timer_init();
> -
> -	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> -	if (ret) {
> -		debug("Pinctrl init failed: %d\n", ret);
> -		return;
> -	}
> -
> -	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> -	if (ret) {
> -		debug("DRAM init failed: %d\n", ret);
> -		return;
> -	}
> -}
> -
> -#ifdef CONFIG_SPL_LOAD_FIT
> -int board_fit_config_name_match(const char *name)
> -{
> -	/* Just empty function now - can't decide what to choose */
> -	debug("%s: %s\n", __func__, name);
> -
> -	return 0;
> -}
> -#endif
> diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c
> deleted file mode 100644
> index 9293843..0000000
> --- a/arch/arm/mach-rockchip/rk3399-board.c
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -/*
> - * Copyright (c) 2017 Rockchip Electronics Co., Ltd
> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <asm/arch/boot_mode.h>
> -
> -int board_late_init(void)
> -{
> -	setup_boot_mode();
> -	return 0;
> -}
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index dbc248f..6c89f25 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -6,8 +6,11 @@
>
> #include <common.h>
> #include <asm/armv8/mmu.h>
> -#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/grf_rk3399.h>
> #include <asm/arch/hardware.h>
> +#include <asm/io.h>
> +#include <syscon.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -35,23 +38,86 @@ static struct mm_region rk3399_mem_map[] = {
>
> struct mm_region *mem_map = rk3399_mem_map;
>
> -int dram_init_banksize(void)
> -{
> -	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> +	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
> +	[BROM_BOOTSOURCE_SPINOR] = "/spi at ff1d0000",
> +	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
> +};
>
> -	/* Reserve 0x200000 for ATF bl31 */
> -	gd->bd->bi_dram[0].start = 0x200000;
> -	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
> +#ifdef CONFIG_SPL_BUILD
>
> -	return 0;
> +#define TIMER_CHN10_BASE	0xff8680a0
> +#define TIMER_END_COUNT_L	0x00
> +#define TIMER_END_COUNT_H	0x04
> +#define TIMER_INIT_COUNT_L	0x10
> +#define TIMER_INIT_COUNT_H	0x14
> +#define TIMER_CONTROL_REG	0x1c
> +
> +#define TIMER_EN	0x1
> +#define	TIMER_FMODE	(0 << 1)
> +#define	TIMER_RMODE	(1 << 1)
> +
> +void rockchip_stimer_init(void)
> +{
> +	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
> +	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
> +	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
> +	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
> +	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
> +	printf("%s\n", __func__);
> }
>
> +#define GRF_BASE	0xff770000
> +#define PMUSGRF_BASE	0xff330000
> int arch_cpu_init(void)
> {
> +	struct rk3399_pmusgrf_regs *sgrf = (void *)PMUSGRF_BASE;
> +	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
> +
> 	/* We do some SoC one time setting here. */
> +	/*
> +	 * Disable DDR and SRAM security regions.
> +	 *
> +	 * As we are entered from the BootROM, the region from
> +	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
> +	 * be protected. This will cause issues with the DW_MMC
> +	 * driver, which tries to DMA from/to the stack (likely)
> +	 * located in this range.
> +	 */
> +	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
> +	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
>
> -	/* Emmc clock generator: disable the clock multipilier */
> -	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
> +	/*  eMMC clock generator: disable the clock multipilier */
> +	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
>
> 	return 0;
> }
> +#endif
> +
> +void board_debug_uart_init(void)
> +{
> +#define GRF_BASE	0xff770000
> +	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
> +
> +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> +	/* Enable early UART0 on the RK3399 */
> +	rk_clrsetreg(&grf->gpio2c_iomux,
> +		     GRF_GPIO2C0_SEL_MASK,
> +		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
> +	rk_clrsetreg(&grf->gpio2c_iomux,
> +		     GRF_GPIO2C1_SEL_MASK,
> +		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
> +#else
> +	/* Enable early UART2 channel C on the RK3399 */
> +	rk_clrsetreg(&grf->gpio4c_iomux,
> +		     GRF_GPIO4C3_SEL_MASK,
> +		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
> +	rk_clrsetreg(&grf->gpio4c_iomux,
> +		     GRF_GPIO4C4_SEL_MASK,
> +		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
> +	/* Set channel C as UART2 input */
> +	rk_clrsetreg(&grf->soc_con7,
> +		     GRF_UART_DBG_SEL_MASK,
> +		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
> +#endif
> +}
> diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
> index 502dec3..79b7436 100644
> --- a/board/rockchip/evb_rk3399/evb-rk3399.c
> +++ b/board/rockchip/evb_rk3399/evb-rk3399.c
> @@ -6,23 +6,29 @@
>
> #include <common.h>
> #include <dm.h>
> +#include <ram.h>
> #include <dm/pinctrl.h>
> #include <dm/uclass-internal.h>
> #include <asm/arch/periph.h>
> #include <power/regulator.h>
> +#include <usb.h>
> +#include <dwc3-uboot.h>
> #include <spl.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int board_init(void)
> +#define RK3399_CPUID_OFF  0x7
> +#define RK3399_CPUID_LEN  0x10
> +
> +int rk_board_init(void)
> {
> 	struct udevice *pinctrl, *regulator;
> 	int ret;
>
> 	/*
> -	 * The PWM do not have decicated interrupt number in dts and can
> +	 * The PWM does not have decicated interrupt number in dts and can
> 	 * not get periph_id by pinctrl framework, so let's init them here.
> -	 * The PWM2 and PWM3 are for pwm regulater.
> +	 * The PWM2 and PWM3 are for pwm regulators.
> 	 */
> 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> 	if (ret) {
> @@ -49,10 +55,6 @@ int board_init(void)
> 		goto out;
> 	}
>
> -	ret = regulators_enable_boot_on(false);
> -	if (ret)
> -		debug("%s: Cannot enable boot on regulator\n", __func__);
> -
> 	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
> 	if (ret) {
> 		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
> @@ -69,29 +71,23 @@ out:
> 	return 0;
> }
>
> -void spl_board_init(void)
> -{
> -	struct udevice *pinctrl;
> -	int ret;
> -
> -	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> -	if (ret) {
> -		debug("%s: Cannot find pinctrl device\n", __func__);
> -		goto err;
> -	}
> -
> -	/* Enable debug UART */
> -	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
> -	if (ret) {
> -		debug("%s: Failed to set up console UART\n", __func__);
> -		goto err;
> -	}
> +#ifdef CONFIG_USB_DWC3
> +static struct dwc3_device dwc3_device_data = {
> +	.maximum_speed = USB_SPEED_HIGH,
> +	.base = 0xfe800000,
> +	.dr_mode = USB_DR_MODE_PERIPHERAL,
> +	.index = 0,
> +	.dis_u2_susphy_quirk = 1,
> +};
>
> -	preloader_console_init();
> -	return;
> -err:
> -	printf("%s: Error %d\n", __func__, ret);
> +int usb_gadget_handle_interrupts(void)
> +{
> +	dwc3_uboot_handle_interrupt(0);
> +	return 0;
> +}
>
> -	/* No way to report error here */
> -	hang();
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	return dwc3_uboot_init(&dwc3_device_data);
> }
> +#endif
> diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
> index c6690fa..9946311 100644
> --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
> +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
> @@ -25,21 +25,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int board_init(void)
> -{
> -	int ret;
> -
> -	/*
> -	 * We need to call into regulators_enable_boot_on() again, as the call
> -	 * during SPL may have not included all regulators.
> -	 */
> -	ret = regulators_enable_boot_on(false);
> -	if (ret)
> -		debug("%s: Cannot enable boot on regulator\n", __func__);
> -

This is critical during SPL for us.
I don't see this being moved anywhere else.

> -	return 0;
> -}
> -
> static void rk3399_force_power_on_reset(void)
> {
> 	ofnode node;
> @@ -62,7 +47,7 @@ static void rk3399_force_power_on_reset(void)
> 	dm_gpio_set_value(&sysreset_gpio, 1);
> }
>
> -void spl_board_init(void)
> +void rk_spl_board_init(void)

I am very unhappy with this being renamed: as indicated in my review of 
the new common board-file, we need a more robust solution to this.

> {
> 	int  ret;
> 	struct rk3399_cru *cru = rockchip_get_cru();
>

[U-Boot] [U-Boot, 01/36] rockchip: rk3288: move configure_l2ctlr back to rk3288

[Kever Yang]

Hi Philipp,


On 04/02/2018 04:47 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> The configure_l2ctlr() is used only by rk3288, do not need to
>> locate in sys_proto.h
>
> Please elaborate on what the function does and why it is not needed by
> any of the other SOCs (after all: it has been available to all SOCs so
> far).

It does not available to all SoCs, only rk3288-board-spl use this function.
Jagan move this function from rk3288-board-spl.c to sys_proto.h because
he think both spl and tpl needs it:
a982d51 armv7: rk3288: Move configure_l2ctlr to common
I move this function back to rk3288 AS-IS and only with checkpatch fix,
I don't think I have to add  so much explanation for this AS-IS function
copy-paste.

>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> This should be a standalone patch and doesn't need to be part of the
> series it is in.  This series has way too many different things
> happening at once and needs to be broken up into individual series
> that do one well-defined thing each.
>
> See below for requested changes.
>
>> ---
>>
>> arch/arm/include/asm/arch-rockchip/sys_proto.h | 22
>> ----------------------
>> arch/arm/mach-rockchip/rk3288/rk3288.c         | 26
>> +++++++++++++++++++++++++-
>> 2 files changed, 25 insertions(+), 23 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h
>> b/arch/arm/include/asm/arch-rockchip/sys_proto.h
>> index e428d59..3617ac2 100644
>> --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
>> +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
>> @@ -7,27 +7,5 @@
>> #ifndef _ASM_ARCH_SYS_PROTO_H
>> #define _ASM_ARCH_SYS_PROTO_H
>>
>> -#ifdef CONFIG_ROCKCHIP_RK3288
>> -#include <asm/armv7.h>
>> -
>> -static void configure_l2ctlr(void)
>> -{
>> -    uint32_t l2ctlr;
>> -
>> -    l2ctlr = read_l2ctlr();
>> -    l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
>> -
>> -    /*
>> -    * Data RAM write latency: 2 cycles
>> -    * Data RAM read latency: 2 cycles
>> -    * Data RAM setup latency: 1 cycle
>> -    * Tag RAM write latency: 1 cycle
>> -    * Tag RAM read latency: 1 cycle
>> -    * Tag RAM setup latency: 1 cycle
>> -    */
>> -    l2ctlr |= (1 << 3 | 1 << 0);
>> -    write_l2ctlr(l2ctlr);
>> -}
>> -#endif /* CONFIG_ROCKCHIP_RK3288 */
>>
>> #endif /* _ASM_ARCH_SYS_PROTO_H */
>> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c
>> b/arch/arm/mach-rockchip/rk3288/rk3288.c
>> index acc3b79..1e1c6be 100644
>> --- a/arch/arm/mach-rockchip/rk3288/rk3288.c
>> +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
>> @@ -3,15 +3,39 @@
>>  *
>>  * SPDX-License-Identifier:     GPL-2.0+
>>  */
>> +#include <asm/armv7.h>
>> #include <asm/io.h>
>> #include <asm/arch/hardware.h>
>>
>> #define GRF_SOC_CON2 0xff77024c
>
> Please make this a const-declaration in the function it is needed in.

This const-declaration does not belong to this patch, isn't it?
>
>>
>> +#ifdef CONFIG_SPL_BUILD
>
> Should this really happen both for TPL and SPL?

I think we only need do this once, if TPL do it, then SPL no need to do
it again.

>
>> +static void configure_l2ctlr(void)
>> +{
>> +    u32 l2ctlr;
>> +
>> +    l2ctlr = read_l2ctlr();
>> +    l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
>
> What are bits 0...17?
>
>> +
>> +    /*
>> +     * Data RAM write latency: 2 cycles
>> +     * Data RAM read latency: 2 cycles
>> +     * Data RAM setup latency: 1 cycle
>> +     * Tag RAM write latency: 1 cycle
>> +     * Tag RAM read latency: 1 cycle
>> +     * Tag RAM setup latency: 1 cycle
>> +     */
>
> Please add a symbolic way to assemble these (i.e. something that makes
> it easy for the casual reader to see what values you are writing to
> which bitfields).
>
>> +    l2ctlr |= (1 << 3 | 1 << 0);
>
> From the "clear bit0 ~ bit17" and this, I assume you actually want to
> do a clrsetbits_le32...

Not really, this write operation is a 'mcr' write to cp15.
>
>> +    write_l2ctlr(l2ctlr);
>> +}
>> +#endif
>> +
>> int arch_cpu_init(void)
>> {
>>     /* We do some SoC one time setting here. */
>> -
>> +#ifdef CONFIG_SPL_BUILD
>> +    configure_l2ctlr();
>> +#else
>>     /* Use rkpwm by default */
>>     rk_setreg(GRF_SOC_CON2, 1 << 0);
>
> Please use a symbolic way to write the (1 << 0), wo it is easy for the
> casual reader to see what gets enabled/disabled here.

Again, this content does not belong to this patch,

Thanks,
- Kever
>
>>
>>
>

[U-Boot] [U-Boot, 02/36] rockchip: add common MACRO to enable sys arch timer

[Kever Yang]

On 04/02/2018 04:51 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> All rockchip SoCs can use ARM arch timer, let's enable it in
>> common header file
>
> Please provide a commit message that is more descriptive of what
> actually happens... i.e. that COUNTER_FREQUENCY gets moved to a common
> header.

Well, will add this info.
> It would be great to document why this will always remain 24M.

All the setting in header file for Rockchip is 24M, doesn't it already a
common code and we should re-use it in common file?

>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> See below for requested changes.
>
>> ---
>>
>> include/configs/rk3368_common.h   | 2 --
>> include/configs/rk3399_common.h   | 2 --
>> include/configs/rockchip-common.h | 4 ++++
>> 3 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/configs/rk3368_common.h
>> b/include/configs/rk3368_common.h
>> index 10f643f..a7fe4ca 100644
>> --- a/include/configs/rk3368_common.h
>> +++ b/include/configs/rk3368_common.h
>> @@ -22,8 +22,6 @@
>> #define CONFIG_SYS_CBSIZE        1024
>> #define CONFIG_SKIP_LOWLEVEL_INIT
>>
>> -#define COUNTER_FREQUENCY               24000000
>> -
>> #define CONFIG_SYS_NS16550_MEM32
>>
>> #define CONFIG_SYS_INIT_SP_ADDR        0x00300000
>> diff --git a/include/configs/rk3399_common.h
>> b/include/configs/rk3399_common.h
>> index d700bf2..fe8c675 100644
>> --- a/include/configs/rk3399_common.h
>> +++ b/include/configs/rk3399_common.h
>> @@ -17,8 +17,6 @@
>> #define CONFIG_SPL_SPI_LOAD
>> #endif
>>
>> -#define COUNTER_FREQUENCY               24000000
>> -
>> #define CONFIG_SYS_NS16550_MEM32
>>
>> #define CONFIG_SYS_INIT_SP_ADDR        0x00300000
>> diff --git a/include/configs/rockchip-common.h
>> b/include/configs/rockchip-common.h
>> index 26d41b5..24651ce 100644
>> --- a/include/configs/rockchip-common.h
>> +++ b/include/configs/rockchip-common.h
>> @@ -8,6 +8,10 @@
>> #define _ROCKCHIP_COMMON_H_
>> #include <linux/sizes.h>
>>
>> +#define COUNTER_FREQUENCY               24000000
>
> Is this really safe for all past, current and future SOCs (after all:
> you are putting this into 'rockchip-common.h'?

Rockchip timer always have a option of 24M, it may not default in SoC value,
we need to select to use 24M in this case.
>
>> +#define CONFIG_SYS_ARCH_TIMER
>
> I don't agree with putting this here, as the CONFIG_SYS_ARCH_TIMER
> definition is only used on ARMv7, but this file is also included by
> ARMv8 SOCs.

Does this setting break anything in ARMv8?
I don't think we need to add a rockchip_common_armv7.h,
at least we can add macro for the definition is used for CONFIG_ARM64 or
not.

Thanks,
- Kever
>
>> +#define CONFIG_SYS_HZ_CLOCK    24000000
>
> You might want to have this refer back to COUNTER_FREQUENCY.
>
>> +
>> #ifndef CONFIG_SPL_BUILD
>>
>> /* First try to boot from SD (index 0), then eMMC (index 1) */
>>
>

[U-Boot] [U-Boot,05/36] rockchip: add STIMER_BASE for all SoCs

[Kever Yang]

On 04/02/2018 04:58 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> STIMER is can only access in secure mode if the SoCs supports trust,
>> and it locate in alive power domain, as the source of ARM arch/generic
>> timer, we add a base addr for all SoCs so that we can init with a common
>> function.
>
> The commit message does not really tell what the source changes are

Then I have no idea what kind information need to add in this commit
message,
could you make it more clear?
I can add message about there is a coming up patch to use this address.
> (although it seems to describe part of the motivation for this change).
>
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> See below for requested changes.
>
>> ---
>>
>> arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm/mach-rockchip/Kconfig
>> b/arch/arm/mach-rockchip/Kconfig
>> index 007cb22..5dfe452 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
>>       The Soc will enter to different boot mode(defined in
>> asm/arch/boot_mode.h)
>>       according to the value from this register.
>>
>> +config ROCKCHIP_STIMER_BASE
>> +    hex "Rockchip Secure timer base address"
>> +    default 0xff220020 if ROCKCHIP_PX30
>
> We don't have support for the PX30 in the U-Boot code base yet.
> Until a series to add support for the PX30 comes in, you should not
> have this here yet (and then add this specific case when the PX30
> support is added).
>
>> +    default 0x200440a0 if ROCKCHIP_RK3036
>> +    default 0x2000e000 if ROCKCHIP_RK3066
>> +    default 0x20018020 if ROCKCHIP_RK3126
>> +    default 0x200440a0 if ROCKCHIP_RK3128
>> +    default 0x2000e000 if ROCKCHIP_RK3188
>> +    default 0x110d0020 if ROCKCHIP_RK322X
>> +    default 0xff810020 if ROCKCHIP_RK3288
>> +    default 0xff1d0020 if ROCKCHIP_RK3328
>> +    default 0xff830020 if ROCKCHIP_RK3368
>> +    default 0xff8680a0 if ROCKCHIP_RK3399
>> +    default 0x10350020 if ROCKCHIP_RV1108
>> +    default 0
>> +    help
>> +      The secure timer inited in SPL/TPL in secure word, ARM generic
>> timer
>> +      works after this timer work.
>
> This should not be in Kconfig and rather in a header-file.

I think it's better to make this information in one place instead of in
different
header files(more then 10 soc header files).
> With what you do here, a user (e.g. via 'make menuconfig') or a
> defconfig file (e.g. due to a typo) could accidentially change
> overwrite this.

This value connect with the SoC type, I don't understand what kind of
typo will overwrite this.

Thanks,
- Kever
>
>> +
>> config ROCKCHIP_SPL_RESERVE_IRAM
>>     hex "Size of IRAM reserved in SPL"
>>     default 0
>>
>

[U-Boot] [U-Boot, 06/36] rockchip: add IRAM_START_ADDR for all SoCs

[Kever Yang]

On 04/02/2018 05:00 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> We add this for get the location for boot device of bootrom.
>
> Your commit message should be specific enough, so the motivation for
> the change, where it fits into the overall architecture and what is
> changed are apparent.
>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> See below for requested changes.
>
>> ---
>>
>> arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm/mach-rockchip/Kconfig
>> b/arch/arm/mach-rockchip/Kconfig
>> index 5dfe452..98bf935 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -209,6 +209,23 @@ config ROCKCHIP_STIMER_BASE
>>       The secure timer inited in SPL/TPL in secure word, ARM generic
>> timer
>>       works after this timer work.
>>
>> +config ROCKCHIP_IRAM_START_ADDR
>> +    hex "Rockchip Secure timer base address"
>
> Huh: copy-and-paste?

Sorry, my fault, will fix in next version.

Thanks,
- Kever
>
>> +    default 0xff0e0000 if ROCKCHIP_PX30
>
> See my earlier comment regarding changes specific to the PX30.
>
>> +    default 0x10080000 if ROCKCHIP_RK3036
>> +    default 0x10080000 if ROCKCHIP_RK3128
>> +    default 0x10080000 if ROCKCHIP_RK3188
>> +    default 0x10080000 if ROCKCHIP_RK322X
>> +    default 0xff700000 if ROCKCHIP_RK3288
>> +    default 0xff091000 if ROCKCHIP_RK3328
>> +    default 0xff8c0000 if ROCKCHIP_RK3368
>> +    default 0xff8c0000 if ROCKCHIP_RK3399
>> +    default 0x10080000 if ROCKCHIP_RV1108
>> +    default 0
>> +    help
>> +      The IRAM start addr is to locate variant of the boot device from
>> +      bootrom.
>
> The same comment as for the secure timer-base applies here.
> This is way to important to have it in Kconfig, where a user can
> easily override.
>
>> +
>> config ROCKCHIP_SPL_RESERVE_IRAM
>>     hex "Size of IRAM reserved in SPL"
>>     default 0
>>
>

[U-Boot] [U-Boot, 16/36] rockchip: sdram-common: add api to pass dram info to trust os

[Kever Yang]

On 04/02/2018 05:43 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> Trust OS decode this info like this:
>> https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
>>
>> We have to set a available value, or else we get error info from
>> Trust OS like this:
>> "ERROR:   over or zero region, nr=3145987, max=10"
>
> Please describe what changes the patch makes.
>
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> See below for requested changes.
>
>> ---
>>
>> arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 ++++
>> arch/arm/mach-rockchip/sdram_common.c             | 21
>> +++++++++++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
>> b/arch/arm/include/asm/arch-rockchip/sdram_common.h
>> index fec8586..55c6b81 100644
>> --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
>> +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
>> @@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg);
>>
>> /* Called by U-Boot board_init_r for Rockchip SoCs */
>> int dram_init(void);
>> +
>> +/* Write ddr param to a known place for trustos */
>> +int rockchip_setup_ddr_param(struct ram_info *info);
>> +
>> #endif
>> diff --git a/arch/arm/mach-rockchip/sdram_common.c
>> b/arch/arm/mach-rockchip/sdram_common.c
>> index 76dbdc8..3a71f09 100644
>> --- a/arch/arm/mach-rockchip/sdram_common.c
>> +++ b/arch/arm/mach-rockchip/sdram_common.c
>> @@ -12,6 +12,15 @@
>> #include <dm/uclass-internal.h>
>>
>> DECLARE_GLOBAL_DATA_PTR;
>> +struct ddr_param {
>> +    u32 count;
>> +    u32 reserved;
>> +    u64 bank_addr;
>> +    u64 bank_size;
>> +};
>> +
>> +#define PARAM_DRAM_INFO_OFFSET 0x2000000
>
> Having this a fixed offset feels a bit hackish... especially as this
> is now implemented for all SOCs.

Yes, but it's using in all rockchip binaries now.
I would like to use fdt or ATAGS instead, but this still the most simple
way to implement.
Many modules with different owner in different team need to update if we
use fdt/atags:
- Rockchip ddr.bin to provide dram info, one os_reg may not enough for
those DRAM have more than one bank,
- Rockchip miniloader.bin to decode the DRAM info and pass it to
Trust(ATF/OPTEE);
- ATF/OPTEE get the DRAM info and update what memory it used, and then
passed to U-Boot,
- U-Boot need to decode the DRAM info from previous stage like ddr and
Trust.
- U-Boot TPL equal to rockchip ddr.bin, and U-Boot SPL equal to rockchip
miniloader.bin
7 modules for different SoCs need to update: ddr.bin, miniloader.bin,
atf bl31.bin, optee.bin, tpl, spl, U-Boot.

And here is the problem we may met:
- ddr.bin/TPL only have limited available internal sram, not able to
support fdt modify in most case, so ATAGS or private structure may be used;
- miniloader.bin/U-Boot SPL does not support parse input parameter,
miniloader event not support fdt now;
- U-Boot does not support parse input parameter;

So we have to use what already use in product before we make new
solution work in all modules.

Thanks,
- Kever
>
>> +
>> size_t rockchip_sdram_size(phys_addr_t reg)
>> {
>>     u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
>> @@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size)
>>
>>     return (gd->ram_top > top) ? top : gd->ram_top;
>> }
>> +
>> +int rockchip_setup_ddr_param(struct ram_info *info)
>> +{
>> +    struct ddr_param *dinfo = (struct ddr_param
>> *)CONFIG_SYS_SDRAM_BASE +
>> +                    PARAM_DRAM_INFO_OFFSET;
>> +
>> +    dinfo->count = 1;
>> +    dinfo->bank_addr = info->base;
>> +    dinfo->bank_size = info->size;
>> +
>> +    return 0;
>> +}
>
> This setup should only be performed when preparing the system to enter
> the ATF.  So you will need to hook it into path where the ATF is
> prepared for being jumped into.
>
> I would further prefer (but this is a personal preference) to
> eventually move to using the FDT we inject into the ATF to convey this
> information.
>
>>
>

[U-Boot] [U-Boot, 17/36] rockchip: sdram_common: add common dram_init_banksize

[Kever Yang]

On 04/02/2018 05:50 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> dram_init_banksize() can be common used by all SoCs, move it into
>> sdram_common.c
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> arch/arm/mach-rockchip/sdram_common.c | 63
>> ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 62 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-rockchip/sdram_common.c
>> b/arch/arm/mach-rockchip/sdram_common.c
>> index 3a71f09..ff86096 100644
>> --- a/arch/arm/mach-rockchip/sdram_common.c
>> +++ b/arch/arm/mach-rockchip/sdram_common.c
>> @@ -21,13 +21,74 @@ struct ddr_param {
>>
>> #define PARAM_DRAM_INFO_OFFSET 0x2000000
>>
>> +#define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
>
> This isn't covered by what you commit message states as content for
> this patch.

Will add it.
>
>> +
>> +struct tos_parameter_t {
>> +    u32 version;
>> +    u32 checksum;
>> +    struct {
>> +        char name[8];
>> +        s64 phy_addr;
>> +        u32 size;
>> +        u32 flags;
>> +    } tee_mem;
>> +    struct {
>> +        char name[8];
>> +        s64 phy_addr;
>> +        u32 size;
>> +        u32 flags;
>> +    } drm_mem;
>> +    s64 reserve[8];
>> +};
>> +
>> +int dram_init_banksize(void)
>> +{
>> +    size_t top = min((unsigned long)(gd->ram_size +
>> CONFIG_SYS_SDRAM_BASE),
>> +             gd->ram_top);
>> +
>> +#ifdef CONFIG_ARM64
>> +    /* Reserve 0x200000 for ATF bl31 */
>> +    gd->bd->bi_dram[0].start = 0x200000;
>> +    gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
>
> This should only be done when preparing to start a
>     IH_OS_ARM_TRUSTED_FIRMWARE.

Yes, you are right, but ATF in ARM64 is not optional, it's mandatory, so
I don't think we need
a #if/#else here.
>
>> +#else
>> +#ifdef CONFIG_SPL_OPTEE
>
> I don't think that this CONFIG_SPL_OPTEE was what the comments in the
> OPTEE thread have arrived at... please check again.
>

Will update and use new MACRO, I leave it there because you have such a
sloooow response and then a looong time discussion.

Thanks,
- Kever
> Just as an unreleated comment/reminder: you still need to revise the
> other series as per the comments and final decision on how to
> implement it.
>
>> +    struct tos_parameter_t *tos_parameter;
>> +
>> +    tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
>> +            TRUST_PARAMETER_OFFSET);
>> +
>> +    if (tos_parameter->tee_mem.flags == 1) {
>
> Please describe what this 'flags' member means and how it's encoded.
>
>> +        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
>> +        gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
>> +                    - CONFIG_SYS_SDRAM_BASE;
>> +        gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
>> +                    tos_parameter->tee_mem.size;
>> +        gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
>> +                    + top - gd->bd->bi_dram[1].start;
>> +    } else {
>> +        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
>> +        gd->bd->bi_dram[0].size = 0x8400000;
>> +        /* Reserve 32M for OPTEE with TA */
>> +        gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
>> +                    + gd->bd->bi_dram[0].size + 0x2000000;
>> +        gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
>> +                    + top - gd->bd->bi_dram[1].start;
>> +    }
>
> This should again only be done, when the appropriate IH_OS_* is entered.
>
>> +#else
>> +    gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
>> +    gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
>
> This should be the default (so you can remove the #if paths) once you
> make sure that the other paths are actually called for entering the
> particular IH_OS_* types.
>
>> +#endif
>> +#endif
>> +
>> +    return 0;
>> +}
>> +
>> size_t rockchip_sdram_size(phys_addr_t reg)
>> {
>>     u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
>>     size_t chipsize_mb = 0;
>>     size_t size_mb = 0;
>>     u32 ch;
>> -
>
> Ok, but not really needed (unless you want to do a separate 'cosmetic'
> or 'whitespace' patch.  Touching an unrelated function is usually a
> bad idea.
>
>>     u32 sys_reg = readl(reg);
>>     u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
>>                & SYS_REG_NUM_CH_MASK);
>>
>

[U-Boot] [U-Boot, 30/36] rockchip: lion-rk3368: remove rockchip timer

[Kever Yang]

On 04/02/2018 05:34 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> We use ARM generic timer.
>
> A more enlightening commit message, please.
>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> See below for comments.
>
>> ---
>>
>> configs/lion-rk3368_defconfig | 4 ----
>> 1 file changed, 4 deletions(-)
>>
>> diff --git a/configs/lion-rk3368_defconfig
>> b/configs/lion-rk3368_defconfig
>> index 8a95ce3..89c4d76 100644
>> --- a/configs/lion-rk3368_defconfig
>> +++ b/configs/lion-rk3368_defconfig
>> @@ -88,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
>> CONFIG_DEBUG_UART_SKIP_INIT=y
>> CONFIG_ROCKCHIP_SPI=y
>> CONFIG_SYSRESET=y
>> -CONFIG_TIMER=y
>> -CONFIG_SPL_TIMER=y
>> -CONFIG_TPL_TIMER=y
>> -CONFIG_ROCKCHIP_TIMER=y
>
> NAK: The reason to not do this (and to have a DM time for the RK3368)
> has been discussed, when we originally added this: SPL should not be
> specific on the software stack.
>
> Consider the following cases:
> 1. Boot to Linux (or U-Boot in EL2): this always includes an ATF as the
>    next-stage... so no need to setup the secure time here, as ATF will
>    take care of this anyway.
> 2. Boot to U-Boot in EL3 (e.g. from the Miniloader): we shouldn't rely on
>    the secure time having been set up (but U-Boot can't do it either, as
>    the same binary could either run at EL3 or at EL2).
>

I'm sure(and we have to make sure) the secure timer have been set up before
U-Boot proper, no matter who do it(SPL/miniloader/trust), because kernel is
always using ARM generic timer as clock source. If the kernel can rely
on it,
then U-Boot can rely on it.

In rockchip binaries, ddr.bin will do setup the secure timer and in
U-Boot project,
SPL or TPL need to do this.

You can still use rockchip timer as DM timer for lion-rk3368, although I
prefer
all SoCs/boards to use the timer in a same way.

Thanks,
- Kever
> So the consensus was to not have U-Boot rely on the secure timer to be
> initialised... especially, as it doesn't have to rely on this.
>
> Note that this is also true for the RK3399, but I need to finish up
> further changes to the DRAM init code, as that currently relies on
> having a timebase before the DM timer is available.
>
>> CONFIG_USE_TINY_PRINTF=y
>> CONFIG_SPL_TINY_MEMSET=y
>> CONFIG_LZO=y
>>
>

[U-Boot] [U-Boot, 31/36] rockchip: rk3399: prepare to use common board file

[Kever Yang]

On 04/02/2018 05:59 AM, Philipp Tomsich wrote:
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> -int board_init(void)
>> -{
>> -    int ret;
>> -
>> -    /*
>> -     * We need to call into regulators_enable_boot_on() again, as
>> the call
>> -     * during SPL may have not included all regulators.
>> -     */
>> -    ret = regulators_enable_boot_on(false);
>> -    if (ret)
>> -        debug("%s: Cannot enable boot on regulator\n", __func__);
>> -
>
> This is critical during SPL for us.
> I don't see this being moved anywhere else. 

This will be in common board.c in coming up patch.

Thanks,
- Kever

[U-Boot] [U-Boot, 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Artturi Alm]

On Sun, Apr 01, 2018 at 10:21:50PM +0200, Philipp Tomsich wrote:
> > We use ARM arch timer instead.
> > 
> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> > ---
> > 
> >  include/configs/rk3188_common.h | 3 ---
> >  1 file changed, 3 deletions(-)
> > 
> 
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fwiw., i don't believe rk3188(Cortex-A9) has the armv7 'arch timer'.
please do test before applying..

-Artturi

> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [U-Boot, 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Dr. Philipp Tomsich]

Arturri,

> On 2 Apr 2018, at 11:38, Artturi Alm <artturi.alm@gmail.com> wrote:
> 
> On Sun, Apr 01, 2018 at 10:21:50PM +0200, Philipp Tomsich wrote:
>>> We use ARM arch timer instead.
>>> 
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> ---
>>> 
>>> include/configs/rk3188_common.h | 3 ---
>>> 1 file changed, 3 deletions(-)
>>> 
>> 
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> 
> fwiw., i don't believe rk3188(Cortex-A9) has the armv7 'arch timer'.
> please do test before applying..

I won’t be able to test this one (and a number other ones), as I only
have access to RK3399 and RK3368 boards.

Feel free to validate this on your end and comment on this patch.

This patch set is not on my list for the current release cycle, due to
it affecting all boards and the associated test effort needed.  I am
considering either for a ‘next’-branch or for a topic-branch to be
created later in this cycle (e.g. branched off rc2?).

Thanks,
Philipp.

[U-Boot] [U-Boot, 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Heiko Stuebner]

Am Montag, 2. April 2018, 11:51:30 CEST schrieb Dr. Philipp Tomsich:
> Arturri,
> 
> > On 2 Apr 2018, at 11:38, Artturi Alm <artturi.alm@gmail.com> wrote:
> > 
> > On Sun, Apr 01, 2018 at 10:21:50PM +0200, Philipp Tomsich wrote:
> >>> We use ARM arch timer instead.
> >>> 
> >>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> >>> ---
> >>> 
> >>> include/configs/rk3188_common.h | 3 ---
> >>> 1 file changed, 3 deletions(-)
> >>> 
> >> 
> >> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> > 
> > fwiw., i don't believe rk3188(Cortex-A9) has the armv7 'arch timer'.
> > please do test before applying..
> 
> I won’t be able to test this one (and a number other ones), as I only
> have access to RK3399 and RK3368 boards.
> 
> Feel free to validate this on your end and comment on this patch.
> 
> This patch set is not on my list for the current release cycle, due to
> it affecting all boards and the associated test effort needed.  I am
> considering either for a ‘next’-branch or for a topic-branch to be
> created later in this cycle (e.g. branched off rc2?).

Cortex-A9 socs like the rk3188 (and rk3066) do not have an
architected timer. That was only introduced with the following
ARM cores. So the timer support should probably stay around


Heiko

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Kever Yang]

Philipp,


On 04/02/2018 05:28 AM, Philipp Tomsich wrote:
>
>
> On Tue, 27 Mar 2018, Kever Yang wrote:
>
>> We use common board/spl/tpl file for all rockchip SoCs,
>> - all the SoC spec setting should move into SoC file like rk3288.c;
>> - tpl is option and only purpose to init DRAM, clock, uart(option);
>> - spl do secure relate one time init, boot device select, boot into
>>  U-Boot or trust or OS in falcon mode;
>> - board do boot mode detect, enable regulator, usb init and so on.
>
> There's too much going on in a single commit/single series.
> This needs to be split up into multiple, independent steps (e.g. one
> for the timer changes, another one for the UART changes)...

I understand review the patches piece by piece is much more comfortable,
and this patch including "too much" things. And I never expect this
patch set
can be merge quickly, but we have to do this ASAP before more SoC coming.
I have do a lot of test and re-work in my local branch and at last make
it landed in
rockchip vendor U-Boot, with testing in most of SoCs(not including
rk3066/rk3188).
Well, I do try to split it into pieces, but I found that actually not
help very much
except waste much more time:
- The target is(very clear) to make rockchip soc board file in a good
shape with common files,
    instead of copy-paste for each soc(more than 10 of them now)
- then we need to identify what's common and what should go to soc and
board;
- remove using common rockchip timer and use arm generic timer instead
for armv7
    SoCs(rk3066 and rk3188 need still using rockchip timer)
- most soc need to do uart init, boot order select, and some
arch_cpu_init().
- don't break the boards already working, so I still leave some code
which not so common
    in board file, but I would like to remove or move them into right
place if I got a board
    to verify;

@Simon, @Tom,
This patch set is to remove some common files and add some other common
files for
all Rockchip SoCs, I have to make sure the whole patch set can running
good for all SoCs,
but it's really hard to make every patch to build and work perfect for
all SoCs, is there
any mandatory rules for this?

I have to do a lot of temporary work for this like add temporary MACRO
for those SoCs
convert to use common code, and remove it after all the SoCs have
convert to use common
code, which have no any help for what we get at last, but it really cost
a lot of time.

>
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> See below for requested changes (beyond splitting this up).
> Reviewing this in this state is a real chore, so I'll probably have
> more comments, once I see this presented in more manageable parcels.
>
>> ---
>>
>> arch/arm/mach-rockchip/Makefile |  23 +----
>> arch/arm/mach-rockchip/board.c  | 136 ++++++++++++++++++++++++++++
>> arch/arm/mach-rockchip/spl.c    | 195
>> ++++++++++++++++++++++++++++++++++++++++
>> arch/arm/mach-rockchip/tpl.c    | 111 +++++++++++++++++++++++
>> 4 files changed, 445 insertions(+), 20 deletions(-)
>> create mode 100644 arch/arm/mach-rockchip/board.c
>> create mode 100644 arch/arm/mach-rockchip/spl.c
>> create mode 100644 arch/arm/mach-rockchip/tpl.c
>>
>> diff --git a/arch/arm/mach-rockchip/Makefile
>> b/arch/arm/mach-rockchip/Makefile
>> index e1b0519..3aba66c 100644
>> --- a/arch/arm/mach-rockchip/Makefile
>> +++ b/arch/arm/mach-rockchip/Makefile
>> @@ -11,15 +11,8 @@
>> obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>> obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>>
>> -obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
>> -obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
>> -
>> -obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
>> -obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
>> -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
>> -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
>> -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
>> spl-boot-order.o
>> -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
>> spl-boot-order.o
>> +obj-tpl-y += tpl.o
>> +obj-spl-y += spl.o spl-boot-order.o
>>
>> ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
>>
>> @@ -28,21 +21,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
>> # we can have the preprocessor correctly recognise both 0x0 and 0
>> # meaning "turn it off".
>> obj-y += boot_mode.o
>> -
>> -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
>> -obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
>> -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
>> -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
>> -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
>> -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
>> +obj-y += board.o
>> endif
>>
>> obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
>>
>> -ifndef CONFIG_ARM64
>> -obj-y += rk_timer.o
>> -endif
>
> This would need to have gone with the rk_timer.c removal.
> Otherwise things don't build between the earlier patch and here.
>
>> -
>> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
>> obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
>> ifndef CONFIG_TPL_BUILD
>> diff --git a/arch/arm/mach-rockchip/board.c
>> b/arch/arm/mach-rockchip/board.c
>> new file mode 100644
>> index 0000000..52c6f66
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/board.c
>> @@ -0,0 +1,136 @@
>> +/*
>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
>> + *
>> + * SPDX-License-Identifier:     GPL-2.0+
>> + */
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <debug_uart.h>
>> +#include <ram.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/gpio.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/periph.h>
>> +#include <asm/arch/boot_mode.h>
>> +#ifdef CONFIG_DM_REGULATOR
>> +#include <power/regulator.h>
>> +#endif
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
>> +int fb_set_reboot_flag(void)
>> +{
>> +    printf("Setting reboot to fastboot flag ...\n");
>> +    /* Set boot mode to fastboot */
>> +    writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
>> +
>> +    return 0;
>> +}
>> +
>> +#define FASTBOOT_KEY_GPIO 43 /* GPIO1_B3 */
>> +static int fastboot_key_pressed(void)
>> +{
>> +    gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
>> +    gpio_direction_input(FASTBOOT_KEY_GPIO);
>> +    return !gpio_get_value(FASTBOOT_KEY_GPIO);
>> +}
>> +#endif
>> +
>> +__weak int rk_board_init(void)
>> +{
>> +    return 0;
>> +}
>> +
>> +__weak int rk_board_late_init(void)
>> +{
>> +    return 0;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
>> +    if (fastboot_key_pressed()) {
>> +        printf("fastboot key pressed!\n");
>> +        fb_set_reboot_flag();
>> +    }
>> +#endif
>> +
>> +#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
>> +    setup_boot_mode();
>> +#endif
>> +
>> +    return rk_board_late_init();
>> +}
>> +
>> +int board_init(void)
>> +{
>> +    int ret;
>> +
>> +#if !defined(CONFIG_SUPPORT_SPL)
>> +    board_debug_uart_init();
>> +#endif
>> +#ifdef CONFIG_DM_REGULATOR
>> +    ret = regulators_enable_boot_on(false);
>> +    if (ret)
>> +        debug("%s: Cannot enable boot on regulator\n", __func__);
>> +#endif
>> +
>> +    return rk_board_init();
>> +}
>> +
>> +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
>> +void enable_caches(void)
>> +{
>> +    /* Enable D-cache. I-cache is already enabled in start.S */
>> +    dcache_enable();
>> +}
>> +#endif
>> +
>> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
>> +#include <usb.h>
>> +#include <usb/dwc2_udc.h>
>> +
>> +static struct dwc2_plat_otg_data otg_data = {
>> +    .rx_fifo_sz    = 512,
>> +    .np_tx_fifo_sz    = 16,
>> +    .tx_fifo_sz    = 128,
>> +};
>> +
>> +int board_usb_init(int index, enum usb_init_type init)
>> +{
>> +    int node;
>> +    const char *mode;
>> +    bool matched = false;
>> +    const void *blob = gd->fdt_blob;
>> +
>> +    /* find the usb_otg node */
>> +    node = fdt_node_offset_by_compatible(blob, -1,
>> +                         "snps,dwc2");
>> +
>> +    while (node > 0) {
>> +        mode = fdt_getprop(blob, node, "dr_mode", NULL);
>> +        if (mode && strcmp(mode, "otg") == 0) {
>> +            matched = true;
>> +            break;
>> +        }
>> +
>> +        node = fdt_node_offset_by_compatible(blob, node,
>> +                             "snps,dwc2");
>> +    }
>> +    if (!matched) {
>> +        debug("Not found usb_otg device\n");
>> +        return -ENODEV;
>> +    }
>> +    otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
>> +
>> +    return dwc2_udc_probe(&otg_data);
>> +}
>
> This function is already caught in review in another thread (where
> both I and Simon had complained about the way the device-tree is
> traversed from here).
>
> Now this change would suddenly adds this code to all our SOCs instead
> of cleaning this up... in other words, this is our last change to
> clean it up w/o people depending on it: please do so.

I expect USB dwc2 maintainer can do this(convert to use DM for dwc2
gadget) very long time ago,
but I never see anyone say 'yes' and do it.
Most of Rockchip SoCs(except rk3399) using dwc2, so it's right to
present in common board
file, you can see many copies for it before this patch set.
My patch set is to merge the common code in Rockchip platform, and not
try to do any
modify to dwc2 driver.

>
> Could we do something similar to
>     https://patchwork.ozlabs.org/patch/890968/
> here?

This is dwc3 host mode, not for dwc2, there is a similar file for
rockchip dwc3.
>
>> +
>> +int board_usb_cleanup(int index, enum usb_init_type init)
>> +{
>> +    return 0;
>> +}
>> +#endif
>> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
>> new file mode 100644
>> index 0000000..3c10b63
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/spl.c
>> @@ -0,0 +1,195 @@
>> +/*
>> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd
>
> Given that there's quite a bit of code that we contributed (e.g. the
> entire spl_was_booted_from logic), I'd expect you to also
> (additionally) retain the Theobroma Systems copyright.

Sorry for missing copyright for your company, will add it back.
>
>> + *
>> + * SPDX-License-Identifier:     GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <debug_uart.h>
>> +#include <dm.h>
>> +#include <ram.h>
>> +#include <spl.h>
>> +#include <asm/arch/bootrom.h>
>> +#include <asm/arch-rockchip/sys_proto.h>
>> +#include <asm/io.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_ROCKCHIP_IRAM_START_ADDR +
>> 0x10)
>
> This should be a const-variable down where it's needed.
> Plus, you'll need to document somewhere that you expect this at offset
> 0x10 from the start of the IRAM on every SOC.
>
>> +void board_return_to_bootrom(void)
>> +{
>> +    back_to_bootrom(BROM_BOOT_NEXTSTAGE);
>> +}
>> +
>> +__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
>> +};
>
> Having this defined as __weak here is an invitation for future trouble.
> Someone will eventually forget to define it.  Better to rely on a
> link-time error to stop people from abusing this.
>
>> +
>> +const char *board_spl_was_booted_from(void)
>> +{
>> +    u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
>> +    const char *bootdevice_ofpath = NULL;
>> +
>> +    if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
>> +        bootdevice_ofpath = boot_devices[bootdevice_brom_id];
>> +
>> +    if (bootdevice_ofpath)
>> +        debug("%s: brom_bootdevice_id %x maps to '%s'\n",
>> +              __func__, bootdevice_brom_id, bootdevice_ofpath);
>> +    else
>> +        debug("%s: failed to resolve brom_bootdevice_id %x\n",
>> +              __func__, bootdevice_brom_id);
>> +
>> +    return bootdevice_ofpath;
>> +}
>> +
>> +u32 spl_boot_device(void)
>> +{
>> +    u32 boot_device = BOOT_DEVICE_MMC1;
>> +
>> +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
>> +        defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
>> +        defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
>> +    return BOOT_DEVICE_SPI;
>> +#endif
>
> This is not how it should be: if this is a common file, then there
> should be a common way to do this instead of having target-specific
> #ifdefs in here.
>
>> +    if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
>> +        return BOOT_DEVICE_BOOTROM;
>> +
>> +    return boot_device;
>> +}
>> +
>> +u32 spl_boot_mode(const u32 boot_device)
>> +{
>> +    return MMCSD_MODE_RAW;
>> +}
>> +
>> +__weak void rockchip_stimer_init(void)
>> +{
>> +#ifndef CONFIG_ARM64
>> +    asm volatile("mcr p15, 0, %0, c14, c0, 0"
>> +             : : "r"(COUNTER_FREQUENCY));
>> +#endif
>> +    writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
>> +    writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
>> +    writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
>> +    writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
>> +}
>> +
>> +__weak int arch_cpu_init(void)
>> +{
>> +    return 0;
>> +}
>> +
>> +__weak int rk_board_init_f(void)
>> +{
>> +    return 0;
>> +}
>
> This doesn't really help in modularising our board-support and I am
> not a fan of adding something like 'rk_board_init_f' in the first place.
>
> Instead this should be implemented in a way that actually makes the
> code structure easier and more resilient for the future (having __weak
> functions at the architecture-level doesn't really help)... in fact
> the only other uses of __weak in the U-Boot source-base are within
> SPL, as there's no other way to provide hooks there.

I know your proposal is to use DM for board init, then could you make it
more
clear about how to handle this in your solution?
We need to do:
- same board init flow for all rockchip platform;
- something different but common in soc level;
- something different in board level;

>
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> +#ifdef CONFIG_SPL_FRAMEWORK
>> +    int ret;
>> +#if !defined(CONFIG_SUPPORT_TPL)
>> +    struct udevice *dev;
>> +#endif
>> +#endif
>> +
>> +#if !defined(CONFIG_SUPPORT_TPL)
>> +    rockchip_stimer_init();
>> +    arch_cpu_init();
>> +#endif
>> +#define EARLY_UART
>> +#if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
>> +    /*
>> +     * Debug UART can be used from here if required:
>> +     *
>> +     * debug_uart_init();
>> +     * printch('a');
>> +     * printhex8(0x1234);
>> +     * printascii("string");
>> +     */
>> +    debug_uart_init();
>> +    printascii("U-Boot SPL board init");
>> +#endif
>> +
>> +#ifdef CONFIG_SPL_FRAMEWORK
>> +    ret = spl_early_init();
>> +    if (ret) {
>> +        printf("spl_early_init() failed: %d\n", ret);
>> +        hang();
>> +    }
>> +#if !defined(CONFIG_SUPPORT_TPL)
>> +    debug("\nspl:init dram\n");
>> +    ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>> +    if (ret) {
>> +        printf("DRAM init failed: %d\n", ret);
>> +        return;
>> +    }
>> +#endif
>> +    preloader_console_init();
>> +#else
>> +    /* Some SoCs like rk3036 does not use any frame work */
>> +    sdram_init();
>> +#endif
>
> This doesn't improve things at all, compared to having multiple files.
> In fact, it makes things worse, now that we have to have support for
> the (legacy) sdram_init and the other code.

I do consider about using one separate file for tiny sram init, but
please understand this is not 'legacy',
because it will always there and new soc will also use it.
>
>> +
>> +    rk_board_init_f();
>> +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) &&
>> !defined(CONFIG_SPL_BOARD_INIT)
>> +    back_to_bootrom(BROM_BOOT_NEXTSTAGE);
>> +#endif
>> +}
>> +
>> +#ifdef CONFIG_SPL_LOAD_FIT
>> +int board_fit_config_name_match(const char *name)
>> +{
>> +    /* Just empty function now - can't decide what to choose */
>> +    debug("%s: %s\n", __func__, name);
>> +
>> +    return 0;
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_SPL_BOARD_INIT
>> +__weak int rk_spl_board_init(void)
>> +{
>> +    return 0;
>> +}
>> +
>> +static int setup_led(void)
>> +{
>> +#ifdef CONFIG_SPL_LED
>> +    struct udevice *dev;
>> +    char *led_name;
>> +    int ret;
>> +
>> +    led_name = fdtdec_get_config_string(gd->fdt_blob,
>> "u-boot,boot-led");
>> +    if (!led_name)
>> +        return 0;
>> +    ret = led_get_by_label(led_name, &dev);
>> +    if (ret) {
>> +        debug("%s: get=%d\n", __func__, ret);
>> +        return ret;
>> +    }
>> +    ret = led_set_on(dev, 1);
>> +    if (ret)
>> +        return ret;
>> +#endif
>> +
>> +    return 0;
>> +}
>
> Please move this to a separate file, that gets compiled in for
> CONFIG_SPL_LED only.

Why?
Add one separate common file with only one function inside?

Thanks,
- Kever

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Tom Rini]

On Sun, Apr 08, 2018 at 09:45:22AM +0800, Kever Yang wrote:
> Philipp,
> 
> 
> On 04/02/2018 05:28 AM, Philipp Tomsich wrote:
> >
> >
> > On Tue, 27 Mar 2018, Kever Yang wrote:
> >
> >> We use common board/spl/tpl file for all rockchip SoCs,
> >> - all the SoC spec setting should move into SoC file like rk3288.c;
> >> - tpl is option and only purpose to init DRAM, clock, uart(option);
> >> - spl do secure relate one time init, boot device select, boot into
> >>  U-Boot or trust or OS in falcon mode;
> >> - board do boot mode detect, enable regulator, usb init and so on.
> >
> > There's too much going on in a single commit/single series.
> > This needs to be split up into multiple, independent steps (e.g. one
> > for the timer changes, another one for the UART changes)...
> 
> I understand review the patches piece by piece is much more comfortable,
> and this patch including "too much" things. And I never expect this
> patch set
> can be merge quickly, but we have to do this ASAP before more SoC coming.
> I have do a lot of test and re-work in my local branch and at last make
> it landed in
> rockchip vendor U-Boot, with testing in most of SoCs(not including
> rk3066/rk3188).
> Well, I do try to split it into pieces, but I found that actually not
> help very much
> except waste much more time:
> - The target is(very clear) to make rockchip soc board file in a good
> shape with common files,
>     instead of copy-paste for each soc(more than 10 of them now)
> - then we need to identify what's common and what should go to soc and
> board;
> - remove using common rockchip timer and use arm generic timer instead
> for armv7
>     SoCs(rk3066 and rk3188 need still using rockchip timer)
> - most soc need to do uart init, boot order select, and some
> arch_cpu_init().
> - don't break the boards already working, so I still leave some code
> which not so common
>     in board file, but I would like to remove or move them into right
> place if I got a board
>     to verify;
> 
> @Simon, @Tom,
> This patch set is to remove some common files and add some other common
> files for
> all Rockchip SoCs, I have to make sure the whole patch set can running
> good for all SoCs,
> but it's really hard to make every patch to build and work perfect for
> all SoCs, is there
> any mandatory rules for this?

So you mean possibly breaking some existing platforms?  I don't like the
idea of doing that...

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180408/c6c4039d/attachment.sig>

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Dr. Philipp Tomsich]

Kever,

> On 9 Apr 2018, at 00:35, Tom Rini <trini@konsulko.com> wrote:
> 
> On Sun, Apr 08, 2018 at 09:45:22AM +0800, Kever Yang wrote:
>> Philipp,
>> 
>> 
>> On 04/02/2018 05:28 AM, Philipp Tomsich wrote:
>>> 
>>> 
>>> On Tue, 27 Mar 2018, Kever Yang wrote:
>>> 
>>>> We use common board/spl/tpl file for all rockchip SoCs,
>>>> - all the SoC spec setting should move into SoC file like rk3288.c;
>>>> - tpl is option and only purpose to init DRAM, clock, uart(option);
>>>> - spl do secure relate one time init, boot device select, boot into
>>>>  U-Boot or trust or OS in falcon mode;
>>>> - board do boot mode detect, enable regulator, usb init and so on.
>>> 
>>> There's too much going on in a single commit/single series.
>>> This needs to be split up into multiple, independent steps (e.g. one
>>> for the timer changes, another one for the UART changes)...
>> 
>> I understand review the patches piece by piece is much more comfortable,
>> and this patch including "too much" things. And I never expect this
>> patch set
>> can be merge quickly, but we have to do this ASAP before more SoC coming.
>> I have do a lot of test and re-work in my local branch and at last make
>> it landed in
>> rockchip vendor U-Boot, with testing in most of SoCs(not including
>> rk3066/rk3188).
>> Well, I do try to split it into pieces, but I found that actually not
>> help very much
>> except waste much more time:
>> - The target is(very clear) to make rockchip soc board file in a good
>> shape with common files,
>>     instead of copy-paste for each soc(more than 10 of them now)
>> - then we need to identify what's common and what should go to soc and
>> board;
>> - remove using common rockchip timer and use arm generic timer instead
>> for armv7
>>     SoCs(rk3066 and rk3188 need still using rockchip timer)
>> - most soc need to do uart init, boot order select, and some
>> arch_cpu_init().
>> - don't break the boards already working, so I still leave some code
>> which not so common
>>     in board file, but I would like to remove or move them into right
>> place if I got a board
>>     to verify;

Having a clean commit-history and the ability to bisect and revert individual
patches is an important requirement for the overall project.

I thought to have already provided you the needed guidance on how to get
most fo this merged and highlighted where architectural discussions will be
needed.

So to get most of this merged quickly, you will need to break this up into
series that are more manageable (this is likely to not be a full list):
 * the changes for split out the UART configs
 * the timer changes
 * adding a common board-file and switching boards over
For the common board-file, you should add this first and then start moving
SoCs over onto this new file.  I believe (my memory may be wrong) to have
commented so in some of the individual reviews.

Finally, there’s a few architectural issues to discuss:
 1.	You are merging the “board”-files, but these are now merged across
	multiple SoCs and across multiple boards per SoC.  This is already
	causing some fraying at the edges (e.g. the number of rk_* hooks and
	the weak functions added).  We should very carefully consider how
	this will affect adding boards (which may have a specific market
	segment in mind and may—for lack of a better example—not want
	to have rockusb included) in the future.
 2.	The new weak-functions are causing a major headache: they are at
	odds with us trying to move to DM across the entire tree. I strongly
	believe that these weak functions will cause added debug issues in
	the short term and that they will eventually be replaced with more
	DM-like model in the long term.

Thanks,
Philipp.

>> @Simon, @Tom,
>> This patch set is to remove some common files and add some other common
>> files for
>> all Rockchip SoCs, I have to make sure the whole patch set can running
>> good for all SoCs,
>> but it's really hard to make every patch to build and work perfect for
>> all SoCs, is there
>> any mandatory rules for this?
> 
> So you mean possibly breaking some existing platforms?  I don't like the
> idea of doing that...
> 
> -- 
> Tom

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Dr. Philipp Tomsich]

Kever,

> On 8 Apr 2018, at 03:45, Kever Yang <kever.yang@rock-chips.com> wrote:
> 
> Philipp,
> 
> 
> On 04/02/2018 05:28 AM, Philipp Tomsich wrote:
>> 
>> 
>> On Tue, 27 Mar 2018, Kever Yang wrote:
>> 
>>> We use common board/spl/tpl file for all rockchip SoCs,
>>> - all the SoC spec setting should move into SoC file like rk3288.c;
>>> - tpl is option and only purpose to init DRAM, clock, uart(option);
>>> - spl do secure relate one time init, boot device select, boot into
>>>  U-Boot or trust or OS in falcon mode;
>>> - board do boot mode detect, enable regulator, usb init and so on.
>> 
>> There's too much going on in a single commit/single series.
>> This needs to be split up into multiple, independent steps (e.g. one
>> for the timer changes, another one for the UART changes)...
> 
> I understand review the patches piece by piece is much more comfortable,

In fact I do not like to do these reviews, as they are a tiresome chore…
…but they need to be done, as some issues are best caught at this stage.
Note, that a good commit message (i.e. one that summarises the status
quo/presents the motivation for the specific change; then summarises
what is changed how and to what effect; finally notes on anything that
the reviewer/someone debugging in the future should know) helps very
much in reviewing.

However, a review can not catch all issues and once a patch-set gets
to a certain level of complexity, it is likely to introduce unnecessary
breakage that could have been avoided in a review (if there simply
hadn’t been too many changes at once).

Consequently, we need a clean history consisting of orthogonal changes
so we can bisect and revert if necessary (and I’d prefer not to revert an
entire series)… which again requires patches that are (a) in a healthy
application-order and (b) do a well-defined number of things well.

> and this patch including "too much" things. And I never expect this
> patch set
> can be merge quickly, but we have to do this ASAP before more SoC coming.

The quickest way to get at least some of this merged quickly (e.g. the
UART changes) is to have smaller series for these.

> I have do a lot of test and re-work in my local branch and at last make
> it landed in
> rockchip vendor U-Boot, with testing in most of SoCs(not including
> rk3066/rk3188).
> Well, I do try to split it into pieces, but I found that actually not
> help very much
> except waste much more time:
> - The target is(very clear) to make rockchip soc board file in a good
> shape with common files,
>     instead of copy-paste for each soc(more than 10 of them now)
> - then we need to identify what's common and what should go to soc and
> board;
> - remove using common rockchip timer and use arm generic timer instead
> for armv7
>     SoCs(rk3066 and rk3188 need still using rockchip timer)
> - most soc need to do uart init, boot order select, and some
> arch_cpu_init().
> - don't break the boards already working, so I still leave some code
> which not so common
>     in board file, but I would like to remove or move them into right
> place if I got a board
>     to verify;
> 
> @Simon, @Tom,
> This patch set is to remove some common files and add some other common
> files for
> all Rockchip SoCs, I have to make sure the whole patch set can running
> good for all SoCs,
> but it's really hard to make every patch to build and work perfect for
> all SoCs, is there
> any mandatory rules for this?
> 
> I have to do a lot of temporary work for this like add temporary MACRO
> for those SoCs
> convert to use common code, and remove it after all the SoCs have
> convert to use common
> code, which have no any help for what we get at last, but it really cost
> a lot of time.
> 
>> 
>>> 
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> 
>> See below for requested changes (beyond splitting this up).
>> Reviewing this in this state is a real chore, so I'll probably have
>> more comments, once I see this presented in more manageable parcels.
>> 
>>> ---
>>> 
>>> arch/arm/mach-rockchip/Makefile |  23 +----
>>> arch/arm/mach-rockchip/board.c  | 136 ++++++++++++++++++++++++++++
>>> arch/arm/mach-rockchip/spl.c    | 195
>>> ++++++++++++++++++++++++++++++++++++++++
>>> arch/arm/mach-rockchip/tpl.c    | 111 +++++++++++++++++++++++
>>> 4 files changed, 445 insertions(+), 20 deletions(-)
>>> create mode 100644 arch/arm/mach-rockchip/board.c
>>> create mode 100644 arch/arm/mach-rockchip/spl.c
>>> create mode 100644 arch/arm/mach-rockchip/tpl.c
>>> 
>>> diff --git a/arch/arm/mach-rockchip/Makefile
>>> b/arch/arm/mach-rockchip/Makefile
>>> index e1b0519..3aba66c 100644
>>> --- a/arch/arm/mach-rockchip/Makefile
>>> +++ b/arch/arm/mach-rockchip/Makefile
>>> @@ -11,15 +11,8 @@
>>> obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>>> obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>>> 
>>> -obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
>>> -obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
>>> -
>>> -obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
>>> -obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
>>> -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
>>> -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
>>> -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
>>> spl-boot-order.o
>>> -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
>>> spl-boot-order.o
>>> +obj-tpl-y += tpl.o
>>> +obj-spl-y += spl.o spl-boot-order.o
>>> 
>>> ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
>>> 
>>> @@ -28,21 +21,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
>>> # we can have the preprocessor correctly recognise both 0x0 and 0
>>> # meaning "turn it off".
>>> obj-y += boot_mode.o
>>> -
>>> -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
>>> -obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
>>> -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
>>> -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
>>> -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
>>> -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
>>> +obj-y += board.o
>>> endif
>>> 
>>> obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
>>> 
>>> -ifndef CONFIG_ARM64
>>> -obj-y += rk_timer.o
>>> -endif
>> 
>> This would need to have gone with the rk_timer.c removal.
>> Otherwise things don't build between the earlier patch and here.
>> 
>>> -
>>> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
>>> obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
>>> ifndef CONFIG_TPL_BUILD
>>> diff --git a/arch/arm/mach-rockchip/board.c
>>> b/arch/arm/mach-rockchip/board.c
>>> new file mode 100644
>>> index 0000000..52c6f66
>>> --- /dev/null
>>> +++ b/arch/arm/mach-rockchip/board.c
>>> @@ -0,0 +1,136 @@
>>> +/*
>>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
>>> + *
>>> + * SPDX-License-Identifier:     GPL-2.0+
>>> + */
>>> +#include <common.h>
>>> +#include <clk.h>
>>> +#include <dm.h>
>>> +#include <debug_uart.h>
>>> +#include <ram.h>
>>> +#include <syscon.h>
>>> +#include <asm/io.h>
>>> +#include <asm/gpio.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/periph.h>
>>> +#include <asm/arch/boot_mode.h>
>>> +#ifdef CONFIG_DM_REGULATOR
>>> +#include <power/regulator.h>
>>> +#endif
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
>>> +int fb_set_reboot_flag(void)
>>> +{
>>> +    printf("Setting reboot to fastboot flag ...\n");
>>> +    /* Set boot mode to fastboot */
>>> +    writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +#define FASTBOOT_KEY_GPIO 43 /* GPIO1_B3 */
>>> +static int fastboot_key_pressed(void)
>>> +{
>>> +    gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
>>> +    gpio_direction_input(FASTBOOT_KEY_GPIO);
>>> +    return !gpio_get_value(FASTBOOT_KEY_GPIO);
>>> +}
>>> +#endif
>>> +
>>> +__weak int rk_board_init(void)
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +__weak int rk_board_late_init(void)
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +int board_late_init(void)
>>> +{
>>> +#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
>>> +    if (fastboot_key_pressed()) {
>>> +        printf("fastboot key pressed!\n");
>>> +        fb_set_reboot_flag();
>>> +    }
>>> +#endif
>>> +
>>> +#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
>>> +    setup_boot_mode();
>>> +#endif
>>> +
>>> +    return rk_board_late_init();
>>> +}
>>> +
>>> +int board_init(void)
>>> +{
>>> +    int ret;
>>> +
>>> +#if !defined(CONFIG_SUPPORT_SPL)
>>> +    board_debug_uart_init();
>>> +#endif
>>> +#ifdef CONFIG_DM_REGULATOR
>>> +    ret = regulators_enable_boot_on(false);
>>> +    if (ret)
>>> +        debug("%s: Cannot enable boot on regulator\n", __func__);
>>> +#endif
>>> +
>>> +    return rk_board_init();
>>> +}
>>> +
>>> +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
>>> +void enable_caches(void)
>>> +{
>>> +    /* Enable D-cache. I-cache is already enabled in start.S */
>>> +    dcache_enable();
>>> +}
>>> +#endif
>>> +
>>> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
>>> +#include <usb.h>
>>> +#include <usb/dwc2_udc.h>
>>> +
>>> +static struct dwc2_plat_otg_data otg_data = {
>>> +    .rx_fifo_sz    = 512,
>>> +    .np_tx_fifo_sz    = 16,
>>> +    .tx_fifo_sz    = 128,
>>> +};
>>> +
>>> +int board_usb_init(int index, enum usb_init_type init)
>>> +{
>>> +    int node;
>>> +    const char *mode;
>>> +    bool matched = false;
>>> +    const void *blob = gd->fdt_blob;
>>> +
>>> +    /* find the usb_otg node */
>>> +    node = fdt_node_offset_by_compatible(blob, -1,
>>> +                         "snps,dwc2");
>>> +
>>> +    while (node > 0) {
>>> +        mode = fdt_getprop(blob, node, "dr_mode", NULL);
>>> +        if (mode && strcmp(mode, "otg") == 0) {
>>> +            matched = true;
>>> +            break;
>>> +        }
>>> +
>>> +        node = fdt_node_offset_by_compatible(blob, node,
>>> +                             "snps,dwc2");
>>> +    }
>>> +    if (!matched) {
>>> +        debug("Not found usb_otg device\n");
>>> +        return -ENODEV;
>>> +    }
>>> +    otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
>>> +
>>> +    return dwc2_udc_probe(&otg_data);
>>> +}
>> 
>> This function is already caught in review in another thread (where
>> both I and Simon had complained about the way the device-tree is
>> traversed from here).
>> 
>> Now this change would suddenly adds this code to all our SOCs instead
>> of cleaning this up... in other words, this is our last change to
>> clean it up w/o people depending on it: please do so.
> 
> I expect USB dwc2 maintainer can do this(convert to use DM for dwc2
> gadget) very long time ago,
> but I never see anyone say 'yes' and do it.
> Most of Rockchip SoCs(except rk3399) using dwc2, so it's right to
> present in common board
> file, you can see many copies for it before this patch set.
> My patch set is to merge the common code in Rockchip platform, and not
> try to do any
> modify to dwc2 driver.
> 
>> 
>> Could we do something similar to
>>     https://patchwork.ozlabs.org/patch/890968/ <https://patchwork.ozlabs.org/patch/890968/>
>> here?
> 
> This is dwc3 host mode, not for dwc2, there is a similar file for
> rockchip dwc3.
>> 
>>> +
>>> +int board_usb_cleanup(int index, enum usb_init_type init)
>>> +{
>>> +    return 0;
>>> +}
>>> +#endif
>>> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
>>> new file mode 100644
>>> index 0000000..3c10b63
>>> --- /dev/null
>>> +++ b/arch/arm/mach-rockchip/spl.c
>>> @@ -0,0 +1,195 @@
>>> +/*
>>> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd
>> 
>> Given that there's quite a bit of code that we contributed (e.g. the
>> entire spl_was_booted_from logic), I'd expect you to also
>> (additionally) retain the Theobroma Systems copyright.
> 
> Sorry for missing copyright for your company, will add it back.
>> 
>>> + *
>>> + * SPDX-License-Identifier:     GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <debug_uart.h>
>>> +#include <dm.h>
>>> +#include <ram.h>
>>> +#include <spl.h>
>>> +#include <asm/arch/bootrom.h>
>>> +#include <asm/arch-rockchip/sys_proto.h>
>>> +#include <asm/io.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_ROCKCHIP_IRAM_START_ADDR +
>>> 0x10)
>> 
>> This should be a const-variable down where it's needed.
>> Plus, you'll need to document somewhere that you expect this at offset
>> 0x10 from the start of the IRAM on every SOC.
>> 
>>> +void board_return_to_bootrom(void)
>>> +{
>>> +    back_to_bootrom(BROM_BOOT_NEXTSTAGE);
>>> +}
>>> +
>>> +__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
>>> +};
>> 
>> Having this defined as __weak here is an invitation for future trouble.
>> Someone will eventually forget to define it.  Better to rely on a
>> link-time error to stop people from abusing this.
>> 
>>> +
>>> +const char *board_spl_was_booted_from(void)
>>> +{
>>> +    u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
>>> +    const char *bootdevice_ofpath = NULL;
>>> +
>>> +    if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
>>> +        bootdevice_ofpath = boot_devices[bootdevice_brom_id];
>>> +
>>> +    if (bootdevice_ofpath)
>>> +        debug("%s: brom_bootdevice_id %x maps to '%s'\n",
>>> +              __func__, bootdevice_brom_id, bootdevice_ofpath);
>>> +    else
>>> +        debug("%s: failed to resolve brom_bootdevice_id %x\n",
>>> +              __func__, bootdevice_brom_id);
>>> +
>>> +    return bootdevice_ofpath;
>>> +}
>>> +
>>> +u32 spl_boot_device(void)
>>> +{
>>> +    u32 boot_device = BOOT_DEVICE_MMC1;
>>> +
>>> +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
>>> +        defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
>>> +        defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
>>> +    return BOOT_DEVICE_SPI;
>>> +#endif
>> 
>> This is not how it should be: if this is a common file, then there
>> should be a common way to do this instead of having target-specific
>> #ifdefs in here.
>> 
>>> +    if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
>>> +        return BOOT_DEVICE_BOOTROM;
>>> +
>>> +    return boot_device;
>>> +}
>>> +
>>> +u32 spl_boot_mode(const u32 boot_device)
>>> +{
>>> +    return MMCSD_MODE_RAW;
>>> +}
>>> +
>>> +__weak void rockchip_stimer_init(void)
>>> +{
>>> +#ifndef CONFIG_ARM64
>>> +    asm volatile("mcr p15, 0, %0, c14, c0, 0"
>>> +             : : "r"(COUNTER_FREQUENCY));
>>> +#endif
>>> +    writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
>>> +    writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
>>> +    writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
>>> +    writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
>>> +}
>>> +
>>> +__weak int arch_cpu_init(void)
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +__weak int rk_board_init_f(void)
>>> +{
>>> +    return 0;
>>> +}
>> 
>> This doesn't really help in modularising our board-support and I am
>> not a fan of adding something like 'rk_board_init_f' in the first place.
>> 
>> Instead this should be implemented in a way that actually makes the
>> code structure easier and more resilient for the future (having __weak
>> functions at the architecture-level doesn't really help)... in fact
>> the only other uses of __weak in the U-Boot source-base are within
>> SPL, as there's no other way to provide hooks there.
> 
> I know your proposal is to use DM for board init, then could you make it
> more
> clear about how to handle this in your solution?
> We need to do:
> - same board init flow for all rockchip platform;
> - something different but common in soc level;
> - something different in board level;
> 
>> 
>>> +
>>> +void board_init_f(ulong dummy)
>>> +{
>>> +#ifdef CONFIG_SPL_FRAMEWORK
>>> +    int ret;
>>> +#if !defined(CONFIG_SUPPORT_TPL)
>>> +    struct udevice *dev;
>>> +#endif
>>> +#endif
>>> +
>>> +#if !defined(CONFIG_SUPPORT_TPL)
>>> +    rockchip_stimer_init();
>>> +    arch_cpu_init();
>>> +#endif
>>> +#define EARLY_UART
>>> +#if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
>>> +    /*
>>> +     * Debug UART can be used from here if required:
>>> +     *
>>> +     * debug_uart_init();
>>> +     * printch('a');
>>> +     * printhex8(0x1234);
>>> +     * printascii("string");
>>> +     */
>>> +    debug_uart_init();
>>> +    printascii("U-Boot SPL board init");
>>> +#endif
>>> +
>>> +#ifdef CONFIG_SPL_FRAMEWORK
>>> +    ret = spl_early_init();
>>> +    if (ret) {
>>> +        printf("spl_early_init() failed: %d\n", ret);
>>> +        hang();
>>> +    }
>>> +#if !defined(CONFIG_SUPPORT_TPL)
>>> +    debug("\nspl:init dram\n");
>>> +    ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>>> +    if (ret) {
>>> +        printf("DRAM init failed: %d\n", ret);
>>> +        return;
>>> +    }
>>> +#endif
>>> +    preloader_console_init();
>>> +#else
>>> +    /* Some SoCs like rk3036 does not use any frame work */
>>> +    sdram_init();
>>> +#endif
>> 
>> This doesn't improve things at all, compared to having multiple files.
>> In fact, it makes things worse, now that we have to have support for
>> the (legacy) sdram_init and the other code.
> 
> I do consider about using one separate file for tiny sram init, but
> please understand this is not 'legacy',
> because it will always there and new soc will also use it.
>> 
>>> +
>>> +    rk_board_init_f();
>>> +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) &&
>>> !defined(CONFIG_SPL_BOARD_INIT)
>>> +    back_to_bootrom(BROM_BOOT_NEXTSTAGE);
>>> +#endif
>>> +}
>>> +
>>> +#ifdef CONFIG_SPL_LOAD_FIT
>>> +int board_fit_config_name_match(const char *name)
>>> +{
>>> +    /* Just empty function now - can't decide what to choose */
>>> +    debug("%s: %s\n", __func__, name);
>>> +
>>> +    return 0;
>>> +}
>>> +#endif
>>> +
>>> +#ifdef CONFIG_SPL_BOARD_INIT
>>> +__weak int rk_spl_board_init(void)
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +static int setup_led(void)
>>> +{
>>> +#ifdef CONFIG_SPL_LED
>>> +    struct udevice *dev;
>>> +    char *led_name;
>>> +    int ret;
>>> +
>>> +    led_name = fdtdec_get_config_string(gd->fdt_blob,
>>> "u-boot,boot-led");
>>> +    if (!led_name)
>>> +        return 0;
>>> +    ret = led_get_by_label(led_name, &dev);
>>> +    if (ret) {
>>> +        debug("%s: get=%d\n", __func__, ret);
>>> +        return ret;
>>> +    }
>>> +    ret = led_set_on(dev, 1);
>>> +    if (ret)
>>> +        return ret;
>>> +#endif
>>> +
>>> +    return 0;
>>> +}
>> 
>> Please move this to a separate file, that gets compiled in for
>> CONFIG_SPL_LED only.
> 
> Why?
> Add one separate common file with only one function inside?
> 
> Thanks,
> - Kever

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Kever Yang]

Hi Tom,


On 04/09/2018 06:35 AM, Tom Rini wrote:
>> I have do a lot of test and re-work in my local branch and at last make
>> it landed in
>> rockchip vendor U-Boot, with testing in most of SoCs(not including
>> rk3066/rk3188).
>> Well, I do try to split it into pieces, but I found that actually not
>> help very much
>> except waste much more time:
>> - The target is(very clear) to make rockchip soc board file in a good
>> shape with common files,
>>     instead of copy-paste for each soc(more than 10 of them now)
>> - then we need to identify what's common and what should go to soc and
>> board;
>> - remove using common rockchip timer and use arm generic timer instead
>> for armv7
>>     SoCs(rk3066 and rk3188 need still using rockchip timer)
>> - most soc need to do uart init, boot order select, and some
>> arch_cpu_init().
>> - don't break the boards already working, so I still leave some code
>> which not so common
>>     in board file, but I would like to remove or move them into right
>> place if I got a board
>>     to verify;
>>
>> @Simon, @Tom,
>> This patch set is to remove some common files and add some other common
>> files for
>> all Rockchip SoCs, I have to make sure the whole patch set can running
>> good for all SoCs,
>> but it's really hard to make every patch to build and work perfect for
>> all SoCs, is there
>> any mandatory rules for this?
> So you mean possibly breaking some existing platforms?  I don't like the
> idea of doing that...

No, I'm not intent to to breaking some existing platforms,
this patch set including 36 patches, all the platform should work fine
after apply all these patches, but if only some of them applied,
there is compile error or running error because of feature missing.

Thanks,
- Kever

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Tom Rini]

On Tue, Apr 10, 2018 at 02:54:09PM +0800, Kever Yang wrote:
> Hi Tom,
> 
> 
> On 04/09/2018 06:35 AM, Tom Rini wrote:
> >> I have do a lot of test and re-work in my local branch and at last make
> >> it landed in
> >> rockchip vendor U-Boot, with testing in most of SoCs(not including
> >> rk3066/rk3188).
> >> Well, I do try to split it into pieces, but I found that actually not
> >> help very much
> >> except waste much more time:
> >> - The target is(very clear) to make rockchip soc board file in a good
> >> shape with common files,
> >>     instead of copy-paste for each soc(more than 10 of them now)
> >> - then we need to identify what's common and what should go to soc and
> >> board;
> >> - remove using common rockchip timer and use arm generic timer instead
> >> for armv7
> >>     SoCs(rk3066 and rk3188 need still using rockchip timer)
> >> - most soc need to do uart init, boot order select, and some
> >> arch_cpu_init().
> >> - don't break the boards already working, so I still leave some code
> >> which not so common
> >>     in board file, but I would like to remove or move them into right
> >> place if I got a board
> >>     to verify;
> >>
> >> @Simon, @Tom,
> >> This patch set is to remove some common files and add some other common
> >> files for
> >> all Rockchip SoCs, I have to make sure the whole patch set can running
> >> good for all SoCs,
> >> but it's really hard to make every patch to build and work perfect for
> >> all SoCs, is there
> >> any mandatory rules for this?
> > So you mean possibly breaking some existing platforms?  I don't like the
> > idea of doing that...
> 
> No, I'm not intent to to breaking some existing platforms,
> this patch set including 36 patches, all the platform should work fine
> after apply all these patches, but if only some of them applied,
> there is compile error or running error because of feature missing.

OK.  Similar to the Linux kernel, it's not a good thing to break
buildability of things during a patch series.

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180410/a3f50a86/attachment.sig>

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Dr. Philipp Tomsich]

> On 10 Apr 2018, at 14:32, Tom Rini <trini@konsulko.com> wrote:
> 
> On Tue, Apr 10, 2018 at 02:54:09PM +0800, Kever Yang wrote:
>> Hi Tom,
>> 
>> 
>> On 04/09/2018 06:35 AM, Tom Rini wrote:
>>>> I have do a lot of test and re-work in my local branch and at last make
>>>> it landed in
>>>> rockchip vendor U-Boot, with testing in most of SoCs(not including
>>>> rk3066/rk3188).
>>>> Well, I do try to split it into pieces, but I found that actually not
>>>> help very much
>>>> except waste much more time:
>>>> - The target is(very clear) to make rockchip soc board file in a good
>>>> shape with common files,
>>>>     instead of copy-paste for each soc(more than 10 of them now)
>>>> - then we need to identify what's common and what should go to soc and
>>>> board;
>>>> - remove using common rockchip timer and use arm generic timer instead
>>>> for armv7
>>>>     SoCs(rk3066 and rk3188 need still using rockchip timer)
>>>> - most soc need to do uart init, boot order select, and some
>>>> arch_cpu_init().
>>>> - don't break the boards already working, so I still leave some code
>>>> which not so common
>>>>     in board file, but I would like to remove or move them into right
>>>> place if I got a board
>>>>     to verify;
>>>> 
>>>> @Simon, @Tom,
>>>> This patch set is to remove some common files and add some other common
>>>> files for
>>>> all Rockchip SoCs, I have to make sure the whole patch set can running
>>>> good for all SoCs,
>>>> but it's really hard to make every patch to build and work perfect for
>>>> all SoCs, is there
>>>> any mandatory rules for this?
>>> So you mean possibly breaking some existing platforms?  I don't like the
>>> idea of doing that...
>> 
>> No, I'm not intent to to breaking some existing platforms,
>> this patch set including 36 patches, all the platform should work fine
>> after apply all these patches, but if only some of them applied,
>> there is compile error or running error because of feature missing.
> 
> OK.  Similar to the Linux kernel, it's not a good thing to break
> buildability of things during a patch series.


Independent of this: this is not a single series, but multiple series rolled
into one.  Once the commit messages are reworked to convey what’s
changed in a more meaningful way, this will be even more apparent
than it already is today.

Thanks,
Philipp.

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Kever Yang]

Hi Philipp,


On 04/08/2018 09:45 AM, Kever Yang wrote:
>>> +__weak int arch_cpu_init(void)
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +__weak int rk_board_init_f(void)
>>> +{
>>> +    return 0;
>>> +}
>> This doesn't really help in modularising our board-support and I am
>> not a fan of adding something like 'rk_board_init_f' in the first place.
>>
>> Instead this should be implemented in a way that actually makes the
>> code structure easier and more resilient for the future (having __weak
>> functions at the architecture-level doesn't really help)... in fact
>> the only other uses of __weak in the U-Boot source-base are within
>> SPL, as there's no other way to provide hooks there.
> I know your proposal is to use DM for board init, then could you make it
> more
> clear about how to handle this in your solution?
> We need to do:
> - same board init flow for all rockchip platform;
> - something different but common in soc level;
> - something different in board level;

I didn't see your response for this, could you send out your patches?

I admit that I'm not very clear about the limitation of '__weak' function,
but I do see there are many '__weak' function in common/board_f/r.c,
and my common board file is connect to the board_r.c.

@Simon, @Tom,
    Could you kindly give some comment here?

Thanks,
- Kever

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Tom Rini]

On Fri, Apr 13, 2018 at 03:51:07PM +0800, Kever Yang wrote:
> Hi Philipp,
> 
> 
> On 04/08/2018 09:45 AM, Kever Yang wrote:
> >>> +__weak int arch_cpu_init(void)
> >>> +{
> >>> +    return 0;
> >>> +}
> >>> +
> >>> +__weak int rk_board_init_f(void)
> >>> +{
> >>> +    return 0;
> >>> +}
> >> This doesn't really help in modularising our board-support and I am
> >> not a fan of adding something like 'rk_board_init_f' in the first place.
> >>
> >> Instead this should be implemented in a way that actually makes the
> >> code structure easier and more resilient for the future (having __weak
> >> functions at the architecture-level doesn't really help)... in fact
> >> the only other uses of __weak in the U-Boot source-base are within
> >> SPL, as there's no other way to provide hooks there.
> > I know your proposal is to use DM for board init, then could you make it
> > more
> > clear about how to handle this in your solution?
> > We need to do:
> > - same board init flow for all rockchip platform;
> > - something different but common in soc level;
> > - something different in board level;
> 
> I didn't see your response for this, could you send out your patches?
> 
> I admit that I'm not very clear about the limitation of '__weak' function,
> but I do see there are many '__weak' function in common/board_f/r.c,
> and my common board file is connect to the board_r.c.
> 
> @Simon, @Tom,
>     Could you kindly give some comment here?

I am perhaps more of a fan of using weak functions than other people
are.  The problem with weak functions is that you must know when
designing the code that it can safely only be overridden in one place
per build.  Otherwise the results are not predictable.

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180413/759eb09f/attachment.sig>

[U-Boot] [U-Boot, 36/36] rockchip: add common board file for rockchip platform

[Dr. Philipp Tomsich]

Kever,

> On 13 Apr 2018, at 09:51, Kever Yang <kever.yang@rock-chips.com> wrote:
> On 04/08/2018 09:45 AM, Kever Yang wrote:
> 
>>>> +__weak int arch_cpu_init(void)
>>>> +{
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +__weak int rk_board_init_f(void)
>>>> +{
>>>> +    return 0;
>>>> +}
>>> This doesn't really help in modularising our board-support and I am
>>> not a fan of adding something like 'rk_board_init_f' in the first place.
>>> 
>>> Instead this should be implemented in a way that actually makes the
>>> code structure easier and more resilient for the future (having __weak
>>> functions at the architecture-level doesn't really help)... in fact
>>> the only other uses of __weak in the U-Boot source-base are within
>>> SPL, as there's no other way to provide hooks there.
>> I know your proposal is to use DM for board init, then could you make it
>> more
>> clear about how to handle this in your solution?
>> We need to do:
>> - same board init flow for all rockchip platform;
>> - something different but common in soc level;
>> - something different in board level;
> 
> I didn't see your response for this, could you send out your patches?

This isn’t at the stage of a patch-set yet… I had asked for comments to
this, so we could design this in a way that benefits all platforms.

> I admit that I'm not very clear about the limitation of '__weak' function,
> but I do see there are many '__weak' function in common/board_f/r.c,
> and my common board file is connect to the board_r.c.

I like __weak as a way to provide a hook for something that is part of the
common API (so it’s ok, if spl.c uses this).  However, I don’t want individual
platforms to suddenly expose new extension points.

And with the two examples above (arch_cpu_init and rk_board_init_f), you
basically highlight what’s wrong about using __weak at this level:
1	arch_cpu_init is an extension point to do low-level initialisation for a
	CPU (not a board).  Implementation for it usually live below arch/arm/cpu
	and takes care of things like MMU maintenance.  Now we suddenly provide
	this below arch/arm/mach-rockchip … and using a __weak function.
	This goes against everything that users will expect.  So just move it
	to arch/arm/cpu (you’ll probably need to have 2 separate ones for
	armv7 and armv8) and nothing unexpected will ever happen.
2	If we rk_board_init_f here, we are again changing the extension API
	of U-Boot: board_init_f belongs to each board (i.e. any board can expect
	to override it w/o ill effect), but now you’d suddenly create a link error.
	Instead users need to override rk_board_init_f.  This is a documentation
	nightmare (and the current solution would be to provide a common
	function that all board_init_f implementations could call as their head
	or tail…).

My question—as to whether the DM could/should be extended to CPUs,
SoCs, architectures and boards—was meant to discuss exactly these
observed issues in how boards and SoCs today interact.

I usually don’t mind to touch APIs and extend them (or the driver model),
but a solution for how to handle board/SoC/CPU init sequences is nothing
I want to start before getting an actual design discussion going and reaching
something resembling a consensus of how this aspect of U-Boot should be
structured in a year’s (or two years’) time.

> 
> @Simon, @Tom,
>     Could you kindly give some comment here?
> 
> Thanks,
> - Kever

[U-Boot] [PATCH 05/36] rockchip: add STIMER_BASE for all SoCs

[Kever Yang]

Hi U-Boot Maintainers:

I would like to close this topic and update all related source code, you
can find the previous discussion at [0][1].
Philipp object this patch and his original reason is:

> This should not be in Kconfig and rather in a header-file.
> With what you do here, a user (e.g. via 'make menuconfig') or a defconfig
> file (e.g. due to a typo) could accidentially change overwrite this.

and Philipp also think:
 > asm/arch-rockchip would be preferable over include/config as a header

There are many ways for feature  configure on rockchip platform now:
- board dts;
- header file in include/config
- Kconfig in $(BOARD)_defconfig
- Kconfig default value in 'Kconfig' file
Already too many place to config, we should make it simple rather than
complex.

I think people are migrating more and more configurations from header file
to Kconfig, including:
- option for enable/disable modules;
- option for module parameter which is numerical value;
- option for module parameter which is string;
I think the target is that most of the configs goes to Kconfig and user can
config options with menuconfig
and no need to touch header file(Please tell me if this is not true).

And for all those config options, I think at lease can be separate into two
kind:
- options per-board;
- options per-soc (some of them may per-vendor);
I think the idealized model would be per-soc options goes to 'Kconfig' file
with default value combine with SOC,
and per-board options at $(BOARD)_defconfig.

ROCKCHIP_STIMER_REG(another case is BOOT_MODE_REG) is per-soc config
option, just like SYS_TEXT_BASE,
TPL_TEXT_BASE,  TPL_MAX_SIZE, SYS_SOC and so on. Driver for different SOCs
to use this reg are just the same,
and this reg needs to be used very early in TPL/SPL which means no DM, no
dts available.

Here are the solutions from previous discussion:
- dts (by Simon)
    extra dtb code needed, setting separate into individual board dts;
    not available and not suggestion to use in TPL/SPL;
- move to header in 'asm/arch-rockchip' (by Philipp)
    one more place to config, make config options more complicate;
    may separate in more than 10+ files for different soc/board;
- RMII setting like, (by Philipp)
    reference to 'drivers/net/gmac_rockchip.c', driver for different SoCs
are not re-usable, driver needs to update for each new SoC support;
    not available with DM in early TPL/SPL;
- Kconfig with default value in this patch
    Keep driver clean and no need to update with new SoC;
    One place rather than 10+ individual files, same usage like
SYS_TEXT_BASE, reference to:
      341c058654 sunxi: move CONFIG_SYS_TEXT_BASE out of defconfigs

I think the default value in Kconfig is the best solution, the SPL/TPL
should be small, fast and with enough functionality for use.

Thanks,
- Kever
[0] https://patchwork.ozlabs.org/patch/1004148/
[1] http://patchwork.ozlabs.org/patch/891462/

Kever Yang <kever.yang@rock-chips.com> 于2018年3月27日周二 下午5:30写道：

> STIMER is can only access in secure mode if the SoCs supports trust,
> and it locate in alive power domain, as the source of ARM arch/generic
> timer, we add a base addr for all SoCs so that we can init with a common
> function.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig
> b/arch/arm/mach-rockchip/Kconfig
> index 007cb22..5dfe452 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
>           The Soc will enter to different boot mode(defined in
> asm/arch/boot_mode.h)
>           according to the value from this register.
>
> +config ROCKCHIP_STIMER_BASE
> +       hex "Rockchip Secure timer base address"
> +       default 0xff220020 if ROCKCHIP_PX30
> +       default 0x200440a0 if ROCKCHIP_RK3036
> +       default 0x2000e000 if ROCKCHIP_RK3066
> +       default 0x20018020 if ROCKCHIP_RK3126
> +       default 0x200440a0 if ROCKCHIP_RK3128
> +       default 0x2000e000 if ROCKCHIP_RK3188
> +       default 0x110d0020 if ROCKCHIP_RK322X
> +       default 0xff810020 if ROCKCHIP_RK3288
> +       default 0xff1d0020 if ROCKCHIP_RK3328
> +       default 0xff830020 if ROCKCHIP_RK3368
> +       default 0xff8680a0 if ROCKCHIP_RK3399
> +       default 0x10350020 if ROCKCHIP_RV1108
> +       default 0
> +       help
> +         The secure timer inited in SPL/TPL in secure word, ARM generic
> timer
> +         works after this timer work.
> +
>  config ROCKCHIP_SPL_RESERVE_IRAM
>         hex "Size of IRAM reserved in SPL"
>         default 0
> --
> 1.9.1
>
>

[U-Boot] [RFC] simple address definition method for early TPL/SPL

[Kever Yang]

Hi U-Boot Maintainers:

The use-case is:
- A register address is needed for a function init, eg. stimer init,
boot mode detect;
- It's a per-SoC config, the address is not the same for different SoCs;
- The driver can be just the same other than the address itself is
different;
- The address will be used very early in SPL/TPL;
There is no no effective communication other than the requirement from
the maintainer in the whole passed *YEAR*,
while the requirement does not make sense to this case. And no matter
how I explain why I implement the
patch in this format over and over, there is no response to my
explanation but only the same 'change request'.
I have no experience on mainline U-Boot maintain, but I do maintain a
lot of other project, and I have to convince others
and get agreement if I ask for implement in my way.

It has pending for such a loooooooong time, and I would like to close
this topic and update all related source code,
you can find the previous discussion at [0][1].
Philipp object this patch and his original reason is:

> This should not be in Kconfig and rather in a header-file.
> With what you do here, a user (e.g. via 'make menuconfig') or a defconfig 
> file (e.g. due to a typo) could accidentially change overwrite this.

and Philipp also think:
 > asm/arch-rockchip would be preferable over include/config as a header

There are many ways for feature configure on rockchip platform now:
- board dts;
- header file in 'include/config'
- Kconfig in $(BOARD)_defconfig
- Kconfig default value in 'Kconfig' file
Already too many place to config, we should make it simple rather than
complex.

I think people are migrating more and more configurations from header
file to Kconfig, including:
- option for enable/disable modules;
- option for module parameter which is numerical value;
- option for module parameter which is string;
I think the target is that most of the configs goes to Kconfig and user
can config options with menuconfig
and no need to touch header file(Please tell me if this is not true).

And for all those config options, I think at lease can be separate into
two kind:
- options per-board;
- options per-soc (some of them may per-vendor);
I think the idealized model would be per-soc options goes to 'Kconfig'
file with default value combine with SOC,
and per-board options at $(BOARD)_defconfig.

ROCKCHIP_STIMER_REG(another case is BOOT_MODE_REG) is per-soc config
option, just like SYS_TEXT_BASE,
TPL_TEXT_BASE,  TPL_MAX_SIZE, SYS_SOC and so on. Driver for different
SOCs to use this reg are just the same,
and this reg needs to be used very early in TPL/SPL which means no DM,
no dts available.

Here are the solutions from previous discussion:
- dts (by Simon)
    extra dtb code needed, setting separate into individual board dts;
    not available and not suggestion to use in TPL/SPL;
- move to header in 'asm/arch-rockchip' (by Philipp)
    one more place to config, make config options more complicate;
    may separate in more than 10+ files for different soc/board;
- RMII setting like, (by Philipp)
    reference to 'drivers/net/gmac_rockchip.c', driver for different
SoCs are not re-usable, driver needs to update for each new SoC support;
    not available with DM in early TPL/SPL;
- Kconfig with default value in this patch
    Keep driver clean and no need to update with new SoC;
    One place rather than 10+ individual files, same usage like
SYS_TEXT_BASE, reference to:
      341c058654 sunxi: move CONFIG_SYS_TEXT_BASE out of defconfigs

I think the default value in Kconfig is the best solution, the SPL/TPL
should be small, fast and with enough functionality for use.

Thanks,
- Kever
[0] https://patchwork.ozlabs.org/patch/1004148/
[1] http://patchwork.ozlabs.org/patch/891462/

Kever Yang <kever.yang at rock-chips.com
<mailto:kever.yang@rock-chips.com>> 于2018年3月27日周二 下午5:30写道：

    STIMER is can only access in secure mode if the SoCs supports trust,
    and it locate in alive power domain, as the source of ARM arch/generic
    timer, we add a base addr for all SoCs so that we can init with a common
    function.

    Signed-off-by: Kever Yang <kever.yang at rock-chips.com
    <mailto:kever.yang@rock-chips.com>>
    ---

     arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
     1 file changed, 19 insertions(+)

    diff --git a/arch/arm/mach-rockchip/Kconfig
    b/arch/arm/mach-rockchip/Kconfig
    index 007cb22..5dfe452 100644
    --- a/arch/arm/mach-rockchip/Kconfig
    +++ b/arch/arm/mach-rockchip/Kconfig
    @@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
              The Soc will enter to different boot mode(defined in
    asm/arch/boot_mode.h)
              according to the value from this register.

    +config ROCKCHIP_STIMER_BASE
    +       hex "Rockchip Secure timer base address"
    +       default 0xff220020 if ROCKCHIP_PX30
    +       default 0x200440a0 if ROCKCHIP_RK3036
    +       default 0x2000e000 if ROCKCHIP_RK3066
    +       default 0x20018020 if ROCKCHIP_RK3126
    +       default 0x200440a0 if ROCKCHIP_RK3128
    +       default 0x2000e000 if ROCKCHIP_RK3188
    +       default 0x110d0020 if ROCKCHIP_RK322X
    +       default 0xff810020 if ROCKCHIP_RK3288
    +       default 0xff1d0020 if ROCKCHIP_RK3328
    +       default 0xff830020 if ROCKCHIP_RK3368
    +       default 0xff8680a0 if ROCKCHIP_RK3399
    +       default 0x10350020 if ROCKCHIP_RV1108
    +       default 0
    +       help
    +         The secure timer inited in SPL/TPL in secure word, ARM
    generic timer
    +         works after this timer work.
    +
     config ROCKCHIP_SPL_RESERVE_IRAM
            hex "Size of IRAM reserved in SPL"
            default 0
    -- 
    1.9.1

[U-Boot] [PATCH 32/36] rockchip: remove rk_timer

[Alexander Kochetkov]

Hello, Kever!

Please keep rk_timer.c for rk3188 and other legacy chips. There is no ARM generic timer in
this SoC. This SoC only have private timers.

see https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/1449/generic-timer-on-cortex-a7-cortex-a9

> 27 марта 2018 г., в 12:29, Kever Yang <kever.yang@rock-chips.com> написал(а):
> 
> We do not use rk_timer.c now, remove it.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---

[U-Boot] [PATCH 32/36] rockchip: remove rk_timer

[Kever Yang]

Hi Alexander,

    Thanks for your comment, don't worry, I got this info and have
solution for it.

    rk3188 has moved to use DM timer instead of rk_timer.c, the patch
has been mered at last April and works pretty well, see:

fd9e0fe0e3 rockchip: rk3188: use DM timer instead of rk_timer
f9ef544786 rockchip: rk3188: add timer3 node
7abb7e8fcb rockchip: rk3188: add -u-boot.dtsi for rock-rk3188
e0e1d3f98c rockchip: timer: add compatible strings for rk3188 and rk3288

Thanks,
- Kever
On 03/29/2019 04:35 PM, Alexander Kochetkov wrote:
> Hello, Kever!
>
> Please keep rk_timer.c for rk3188 and other legacy chips. There is
> no ARM generic timer in
> this SoC. This SoC only have private timers.
>
> see https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/1449/generic-timer-on-cortex-a7-cortex-a9
>
>> 27 марта 2018 г., в 12:29, Kever Yang <kever.yang@rock-chips.com
>> <mailto:kever.yang@rock-chips.com>> написал(а):
>>
>> We do not use rk_timer.c now, remove it.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com
>> <mailto:kever.yang@rock-chips.com>>
>> ---
>

[U-Boot] [RFC] simple address definition method for early TPL/SPL

[Kever Yang]

On 03/29/2019 09:02 AM, Kever Yang wrote:
>
> Here are the solutions from previous discussion:
> - dts (by Simon)
>     extra dtb code needed, setting separate into individual board dts;
>     not available and not suggestion to use in TPL/SPL;
> - move to header in 'asm/arch-rockchip' (by Philipp)
>     one more place to config, make config options more complicate;
>     may separate in more than 10+ files for different soc/board;
> - RMII setting like, (by Philipp)
>     reference to 'drivers/net/gmac_rockchip.c', driver for different
> SoCs are not re-usable, driver needs to update for each new SoC support;
>     not available with DM in early TPL/SPL;
> - Kconfig with default value in this patch
>     Keep driver clean and no need to update with new SoC;
>     One place rather than 10+ individual files, same usage like
> SYS_TEXT_BASE, reference to:
>       341c058654 sunxi: move CONFIG_SYS_TEXT_BASE out of defconfigs

If you are not happy with the format which all soc reg address defined
in the same place, one more solution:
How about using the format like TPL_TEXT_BASE followed by each SoC and
system will report error if not defined:
140 if
ROCKCHIP_RK3368                                                             

141                                                                                

142 config
TPL_TEXT_BASE                                                           
143         default
0xff8c1000                                                     
144                                                                                

145 config
TPL_MAX_SIZE                                                            
146         default
28672                                                          
147                                                                                                                                          

148 config
TPL_STACK                                                               
149         default
0xff8cffff                                                     
150                                                                                

151 endif 

Thanks,
- Kever