From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: Re: RFC on writel and writel_relaxed Date: Wed, 28 Mar 2018 20:50:16 +1100 Message-ID: <1522230616.21446.1.camel@kernel.crashing.org> References: <1522141019.7364.43.camel@kernel.crashing.org> <20180327095745.GB29373@arm.com> <20180327100944.GD29373@arm.com> <20180327110258.GF2464@arm.com> <20180327143628.GA10642@arm.com> <1522186185.7364.59.camel@kernel.crashing.org> <20180328085338.GA28871@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180328085338.GA28871@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@lists.ozlabs.org Sender: "Linuxppc-dev" To: Will Deacon Cc: Arnd Bergmann , Jonathan Corbet , "linux-rdma@vger.kernel.org" , Sinan Kaya , Jason Gunthorpe , Peter Zijlstra , David Laight , Oliver , "Paul E. McKenney" , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , Ingo Molnar List-Id: linux-rdma@vger.kernel.org On Wed, 2018-03-28 at 09:53 +0100, Will Deacon wrote: > For arm/arm64 these end up behaving exactly the same as readX/writeX, but > I'm nervous about changing the documentation without understanding why it's > like it is currently. Maybe another ia64 thing?. I doubt it ... the Intel ancestry here would make me think they are completely ordered there too. powerpc and ARM can't quite make them synchronous I think, but at least they should have the same semantics as writel. Cheers, Ben. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40B36g09wYzF2K8 for ; Wed, 28 Mar 2018 20:51:06 +1100 (AEDT) Message-ID: <1522230616.21446.1.camel@kernel.crashing.org> Subject: Re: RFC on writel and writel_relaxed From: Benjamin Herrenschmidt To: Will Deacon Cc: Sinan Kaya , Arnd Bergmann , Jason Gunthorpe , David Laight , Oliver , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , "linux-rdma@vger.kernel.org" , "Paul E. McKenney" , Peter Zijlstra , Ingo Molnar , Jonathan Corbet Date: Wed, 28 Mar 2018 20:50:16 +1100 In-Reply-To: <20180328085338.GA28871@arm.com> References: <1522141019.7364.43.camel@kernel.crashing.org> <20180327095745.GB29373@arm.com> <20180327100944.GD29373@arm.com> <20180327110258.GF2464@arm.com> <20180327143628.GA10642@arm.com> <1522186185.7364.59.camel@kernel.crashing.org> <20180328085338.GA28871@arm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2018-03-28 at 09:53 +0100, Will Deacon wrote: > For arm/arm64 these end up behaving exactly the same as readX/writeX, but > I'm nervous about changing the documentation without understanding why it's > like it is currently. Maybe another ia64 thing?. I doubt it ... the Intel ancestry here would make me think they are completely ordered there too. powerpc and ARM can't quite make them synchronous I think, but at least they should have the same semantics as writel. Cheers, Ben.