From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f1Hsa-000445-3s for qemu-devel@nongnu.org; Wed, 28 Mar 2018 16:41:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f1HsZ-0000XG-0h for qemu-devel@nongnu.org; Wed, 28 Mar 2018 16:41:08 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:41502) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f1HsY-0000Wx-Qp for qemu-devel@nongnu.org; Wed, 28 Mar 2018 16:41:06 -0400 Received: by mail-pg0-x243.google.com with SMTP id t10so1552496pgv.8 for ; Wed, 28 Mar 2018 13:41:06 -0700 (PDT) From: Michael Clark Date: Wed, 28 Mar 2018 13:40:19 -0700 Message-Id: <1522269619-48636-3-git-send-email-mjc@sifive.com> In-Reply-To: <1522269619-48636-1-git-send-email-mjc@sifive.com> References: <1522269619-48636-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 2/2] RISC-V: Fix incorrect disassembly for addiw List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@groups.riscv.org, Michael Clark , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Peter Maydell This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the disseasembler: https://github.com/michaeljclark/riscv-meta/ commit/4a6b2f3898430768acfe201405224d2ea31e1477 Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- disas/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3c17501..74ad16e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; -static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end }; +static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; -- 2.7.0