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From: Ramalingam C <ramalingam.c@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	seanpaul@chromium.org
Cc: rodrigo.vivi@intel.com
Subject: [PATCH v2 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch
Date: Thu, 29 Mar 2018 19:39:05 +0530	[thread overview]
Message-ID: <1522332548-15370-2-git-send-email-ramalingam.c@intel.com> (raw)
In-Reply-To: <1522332548-15370-1-git-send-email-ramalingam.c@intel.com>

As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.

And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.

This patch is needed for DP HDCP1.4 CTS Test: 1A-06.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..96b9025dc759 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -496,9 +496,11 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 	}
 
 	/*
-	 * Wait for R0' to become available. The spec says 100ms from Aksv, but
-	 * some monitors can take longer than this. We'll set the timeout at
-	 * 300ms just to be sure.
+	 * Wait for R0' to become available. The spec says minimum 100ms from
+	 * Aksv, but some monitors can take longer than this. So we are
+	 * combinely waiting for 300mSec just to be sure in case of HDMI.
+	 * DP HDCP Spec mandates the two more reattempt to read R0, incase
+	 * of R0 mismatch.
 	 *
 	 * On DP, there's an R0_READY bit available but no such bit
 	 * exists on HDMI. Since the upper-bound is the same, we'll just do
@@ -506,15 +508,21 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 	 */
 	wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
 
-	ri.reg = 0;
-	ret = shim->read_ri_prime(intel_dig_port, ri.shim);
-	if (ret)
-		return ret;
-	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+	tries = 3;
+	for (i = 0; i < tries; i++) {
+		ri.reg = 0;
+		ret = shim->read_ri_prime(intel_dig_port, ri.shim);
+		if (ret)
+			return ret;
+		I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
 
-	/* Wait for Ri prime match */
-	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
-		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
+		/* Wait for Ri prime match */
+		if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+		    (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
+			break;
+	}
+
+	if (i == tries) {
 		DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
 			  I915_READ(PORT_HDCP_STATUS(port)));
 		return -ETIMEDOUT;
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-03-29 14:09 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-29 14:09 [PATCH v2 0/4] HDCP1.4 fixes Ramalingam C
2018-03-29 14:09 ` Ramalingam C [this message]
2018-03-29 14:35   ` [PATCH v2 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Sean Paul
2018-04-02  9:08     ` Ramalingam C
2018-03-29 14:09 ` [PATCH v2 2/4] drm/i915: Read Vprime thrice incase " Ramalingam C
2018-03-29 14:38   ` Sean Paul
2018-04-02  9:16     ` Ramalingam C
2018-03-29 14:09 ` [PATCH v2 3/4] drm/i915: Check hdcp key loadability Ramalingam C
2018-03-29 14:24   ` Ville Syrjälä
2018-04-02  9:05     ` Ramalingam C
2018-04-06 16:02       ` Ville Syrjälä
2018-04-09  8:28         ` Daniel Vetter
2018-04-11  8:27           ` Ramalingam C
2018-04-13 15:49             ` Daniel Vetter
2018-03-29 14:09 ` [PATCH v2 4/4] drm/i915: Fix downstream dev count read Ramalingam C
2018-03-29 14:39   ` Sean Paul
2018-03-29 14:12 ` [PATCH v2 0/4] HDCP1.4 fixes Ramalingam C
2018-03-29 14:45 ` ✓ Fi.CI.BAT: success for HDCP1.4 fixes (rev3) Patchwork
2018-03-29 17:53 ` ✗ Fi.CI.IGT: failure " Patchwork

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