From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [Bug 1748434] Re: Possibly wrong GICv3 behavior when secure enabled
Date: Tue, 10 Apr 2018 13:57:40 -0000 [thread overview]
Message-ID: <152336866058.29721.5047450009917419747.malone@gac.canonical.com> (raw)
In-Reply-To: 151817810596.29573.3248344286701751294.malonedeb@chaenomeles.canonical.com
Now fixed in master in commit a2e2d7fc46fd8be, so will be in 2.12.0.
** Changed in: qemu
Status: In Progress => Fix Committed
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https://bugs.launchpad.net/bugs/1748434
Title:
Possibly wrong GICv3 behavior when secure enabled
Status in QEMU:
Fix Committed
Bug description:
I an tried arm-aarch64 interrupt routing to EL3, by SCR_EL3.FIQ=1. First I am started QEMU with secure=on and GICv3 support.
I programmed secure and non-secure timers and set-up appropriate interrupts.Secure timer to be GRP1_Secure and non-secure timer to be GRP1_NonSecure. ICC_PMR = 0xff. Then I switched CPU to EL1.
With that setup no interrupt was delivered to PE. GIC interface showed that non secure IRQ is pending. ICC_PMR read at EL1 returns 0 (shall return value ((PMR_(el3) << 1) & 0xff) according to GIC specification.
Than I tried to increase interrupt priority mask - so I set ICC_PMR = 0x7f (at EL3). Then I read at EL1 ICC_PMR=0xfe - (is shall be 0). With this setup IRQ of secure timer was taken at EL3, non secure timer didn't rise IRQ (as it is masked by PMR).
I dig to qemu code and see wrong condition in file arm_gicv3_cpuif.c in function icc_pmr_read(). This behavior is opposite of ARM specification.
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next prev parent reply other threads:[~2018-04-10 14:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-09 12:08 [Qemu-devel] [Bug 1748434] [NEW] Possibly wrong GICv3 behavior when secure enabled Robert Pasz
2018-02-09 14:08 ` [Qemu-devel] [Bug 1748434] " Robert Pasz
2018-03-15 11:41 ` Peter Maydell
2018-03-15 13:26 ` Peter Maydell
2018-03-15 15:01 ` Peter Maydell
2018-04-10 13:57 ` Peter Maydell [this message]
2018-04-26 5:14 ` Thomas Huth
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