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From: vathsala nagaraju <vathsala.nagaraju@intel.com>
To: rodrigo.vivi@intel.com, intel-gfx@lists.freedesktop.org
Cc: Puthikorn Voravootivat <puthik@chromium.org>,
	Maulik V Vaghela <maulik.v.vaghela@intel.com>
Subject: [PATCH] drm/i915/psr: vbt change for psr
Date: Wed, 11 Apr 2018 23:27:01 +0530	[thread overview]
Message-ID: <1523469421-21131-1-git-send-email-vathsala.nagaraju@intel.com> (raw)

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c |  3 ++
 drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
 3 files changed, 61 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..6aa6d68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1075,6 +1075,7 @@ struct intel_vbt_data {
 		enum psr_lines_to_wait lines_to_wait;
 		int tp1_wakeup_time;
 		int tp2_tp3_wakeup_time;
+		int is_tp_time_options;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index c5c7530..08e82e0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -659,6 +659,9 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		return;
 	}
 
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
+		dev_priv->vbt.psr.is_tp_time_options = true;
+
 	psr_table = &psr->psr_table[panel_type];
 
 	dev_priv->vbt.psr.full_link = psr_table->full_link;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f73..74ed6d0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
-		val |= EDP_PSR_TP1_TIME_100us;
-	else
-		val |= EDP_PSR_TP1_TIME_0us;
-
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR_TP2_TP3_TIME_100us;
-	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+	if (dev_priv->vbt.psr.is_tp_time_options) {
+		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
+			val |= EDP_PSR_TP1_TIME_500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
+			val |= EDP_PSR_TP1_TIME_100us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
+			val |= EDP_PSR_TP1_TIME_2500us;
+		else
+			val |= EDP_PSR_TP1_TIME_0us;
+	} else {
+		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
+			val |= EDP_PSR_TP1_TIME_2500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
+			val |= EDP_PSR_TP1_TIME_500us;
+		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+			val |= EDP_PSR_TP1_TIME_100us;
+		else
+			val |= EDP_PSR_TP1_TIME_0us;
+	}
 
+	if (dev_priv->vbt.psr.is_tp_time_options) {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+			val |=  EDP_PSR_TP2_TP3_TIME_500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+			val |= EDP_PSR_TP2_TP3_TIME_100us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+			val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		else
+			val |= EDP_PSR_TP2_TP3_TIME_0us;
+	} else {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+			val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+			val |= EDP_PSR_TP2_TP3_TIME_500us;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+			val |= EDP_PSR_TP2_TP3_TIME_100us;
+		else
+			val |= EDP_PSR_TP2_TP3_TIME_0us;
+	}
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
 		val |= EDP_PSR_TP1_TP3_SEL;
@@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	}
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
-
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
-	else
-		val |= EDP_PSR2_TP2_TIME_50;
-
+	if (dev_priv->vbt.psr.is_tp_time_options) {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+			val |= EDP_PSR2_TP2_TIME_500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+			val |= EDP_PSR2_TP2_TIME_100;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+			val |= EDP_PSR2_TP2_TIME_2500;
+		else
+			val |= EDP_PSR2_TP2_TIME_50;
+	} else {
+		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+			val |= EDP_PSR2_TP2_TIME_2500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+			val |= EDP_PSR2_TP2_TIME_500;
+		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+			val |= EDP_PSR2_TP2_TIME_100;
+		else
+			val |= EDP_PSR2_TP2_TIME_50;
+	}
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
-- 
1.9.1

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             reply	other threads:[~2018-04-11 17:57 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-11 17:57 vathsala nagaraju [this message]
2018-04-11 18:59 ` ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev2) Patchwork
2018-04-11 22:25 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-12  9:26 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2018-05-23  3:05 vathsala nagaraju
2018-05-23 10:03 ` Jani Nikula
2018-05-23 12:55   ` Nagaraju, Vathsala
2018-05-23 13:10     ` Jani Nikula
2018-05-22  9:27 vathsala nagaraju
2018-05-22 12:46 ` Jani Nikula
2018-05-24 13:04   ` Jani Nikula
2018-05-18  8:55 vathsala nagaraju
2018-05-18  9:31 ` Jani Nikula
2018-05-22  4:48   ` Nagaraju, Vathsala
2018-05-22  8:05     ` Jani Nikula
2018-05-22  8:36       ` Nagaraju, Vathsala
2018-05-14  3:32 vathsala nagaraju
2018-05-15 22:55 ` Puthikorn Voravootivat
2018-05-16  3:48   ` vathsala nagaraju
2018-05-15 23:03 ` Dhinakaran Pandiyan
2018-05-16  3:44   ` vathsala nagaraju
2018-05-16  8:08     ` Jani Nikula
2018-05-16 17:44       ` Dhinakaran Pandiyan
2018-05-17  8:02         ` Jani Nikula
2018-05-17 20:12           ` Dhinakaran Pandiyan
2018-05-16  8:13     ` Jani Nikula
2018-05-16 22:04     ` Dhinakaran Pandiyan
2018-05-03 11:36 vathsala nagaraju
2018-05-03 15:44 ` Rodrigo Vivi
2018-05-03 17:13   ` Nagaraju, Vathsala
2018-05-04 23:13     ` Puthikorn Voravootivat
2018-05-03  9:08 vathsala nagaraju
2018-05-03  9:39 ` Jani Nikula
2018-05-02  9:13 vathsala nagaraju
2018-05-02 21:15 ` Rodrigo Vivi
2018-05-03  3:21   ` vathsala nagaraju
2018-05-03  6:59   ` Jani Nikula
2018-05-03  7:07 ` Jani Nikula
2018-04-19  7:42 vathsala nagaraju
2018-04-19 13:35 ` Jani Nikula
2018-04-20  6:30   ` vathsala nagaraju
2018-04-27  7:52     ` Jani Nikula
2018-04-06 17:28 vathsala nagaraju
2018-04-06 17:41 ` Rodrigo Vivi
2018-04-09 13:57   ` Jani Nikula

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