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* [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds
@ 2018-04-13 16:00 Oscar Mateo
  2018-04-13 16:00 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
                   ` (23 more replies)
  0 siblings, 24 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
    comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
      drm/i915/icl: add icelake_init_clock_gating()
    from Paulo Zanoni <paulo.r.zanoni@intel.com>
  - Squashed with this patch:
      drm/i915/icl: WaForceEnableNonCoherent
    from Oscar Mateo <oscar.mateo@intel.com>
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
    applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
    to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring

Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  9 ++++++
 drivers/gpu/drm/i915/i915_gem_gtt.c      |  4 +--
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 drivers/gpu/drm/i915/intel_lrc.c         |  2 ++
 drivers/gpu/drm/i915/intel_pm.c          |  2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 47 ++++++++++++++++++++++++++++++++
 6 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e50d958..b08a22a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
 	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0		0x0
+#define ICL_REVID_A2		0x1
+#define ICL_REVID_B0		0x3
+#define ICL_REVID_B2		0x4
+#define ICL_REVID_C0		0x5
+
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 	else if (IS_GEN9_LP(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0			_MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7c8513..675c19d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1633,6 +1633,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 		return -EINVAL;
 
 	switch (INTEL_GEN(engine->i915)) {
+	case 11:
+		return 0;
 	case 10:
 		wa_bb_fn[0] = gen10_init_indirectctx_bb;
 		wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..cfa03ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,6 +9123,8 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
+	if (IS_ICELAKE(dev_priv))
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
 	if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index bbbf4ed..8c2d17c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+	/* Wa_1604370585:icl (pre-prod)
+	 * Formerly known as WaPushConstantDereferenceHoldDisable
+	 */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+				  PUSH_CONSTANT_DEREF_DISABLE);
+
+	/* WaForceEnableNonCoherent:icl
+	 * This is not the same workaround as in early Gen9 platforms, where
+	 * lacking this could cause system hangs, but coherency performance
+	 * overhead is high and only a few compute workloads really need it
+	 * (the register is whitelisted in hardware now, so UMDs can opt in
+	 * for coherency if they have a good reason).
+	 */
+	WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+
+	return 0;
+}
+
 int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 {
 	int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		err = cfl_ctx_workarounds_init(dev_priv);
 	else if (IS_CANNONLAKE(dev_priv))
 		err = cnl_ctx_workarounds_init(dev_priv);
+	else if (IS_ICELAKE(dev_priv))
+		err = icl_ctx_workarounds_init(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 	if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 }
 
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+	/* This is not an Wa. Enable for better image quality */
+	I915_WRITE(_3D_CHICKEN3,
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+	/* WaInPlaceDecompressionHang:icl */
+	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+	/* WaPipelineFlushCoherentLines:icl */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		cfl_gt_workarounds_apply(dev_priv);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_gt_workarounds_apply(dev_priv);
+	else if (IS_ICELAKE(dev_priv))
+		icl_gt_workarounds_apply(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 }
@@ -818,6 +858,11 @@ static int cnl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
+{
+	return 0;
+}
+
 int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
@@ -845,6 +890,8 @@ int intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 		err = cfl_whitelist_workarounds_apply(engine);
 	else if (IS_CANNONLAKE(dev_priv))
 		err = cnl_whitelist_workarounds_apply(engine);
+	else if (IS_ICELAKE(dev_priv))
+		err = icl_whitelist_workarounds_apply(engine);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 	if (err)
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 02/22] drm/i915/icl: Enable Sampler DFR
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-20  7:26   ` Sagar Arun Kamble
  2018-04-13 16:00 ` [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
                   ` (22 subsequent siblings)
  23 siblings, 1 reply; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx; +Cc: Praveen Paneri

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
 #define GEN8_GARBCNTL                   _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
+#define   DFR_DISABLE			(1 << 9)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 8c2d17c..34a0b56 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+	/* This is not an Wa. Enable to reduce Sampler power */
+	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
 	/* WaInPlaceDecompressionHang:icl */
 	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
 					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
  2018-04-13 16:00 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
                   ` (21 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622

v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b7e6bc..a6b1f85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8215,8 +8215,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
-#define GEN8_GARBCNTL                   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL				_MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 34a0b56..3a44f6f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -703,6 +703,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	/* WaPipelineFlushCoherentLines:icl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+	/* Wa_1405543622:icl
+	 * Formerly known as WaGAPZPriorityScheme
+	 */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
  2018-04-13 16:00 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
  2018-04-13 16:00 ` [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
                   ` (20 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
 drivers/gpu/drm/i915/intel_workarounds.c | 20 ++++++++++++++++----
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6b1f85..5637cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,12 @@ enum {
 #define GEN8_GARBCNTL				_MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
+
+#define GEN11_GLBLINVL				_MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 0)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x3f << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3a44f6f..a94cd93 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-	/* Wa_1405543622:icl
-	 * Formerly known as WaGAPZPriorityScheme
+	I915_WRITE(GEN8_GARBCNTL,
+		   /* Wa_1604223664:icl
+		    * Formerly known as WaL3BankAddressHashing
+		    */
+		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+		    GEN11_HASH_CTRL_EXCL_BIT0 |
+		    /* Wa_1405543622:icl
+		     * Formerly known as WaGAPZPriorityScheme
+		     */
+		    GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+	/* Wa_1604223664:icl
+	 * Formerly known as WaL3BankAddressHashing
 	 */
-	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+	I915_WRITE(GEN11_GLBLINVL,
+		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (2 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
                   ` (19 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5637cd7..fe35785 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8228,6 +8228,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
 
+#define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0			(1 << 0)
+#define   GEN11_HASH_CTRL_BIT4			(1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a94cd93..d7b2b07 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -721,6 +721,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_GLBLINVL,
 		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
 		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+	/* WaModifyGamTlbPartitioning:icl */
+	I915_WRITE(GEN11_GACB_PERF_CTRL,
+		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (3 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
                   ` (18 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe35785..fea85ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7197,8 +7197,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
 #define GEN8_L3SQCREG4				_MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index d7b2b07..f9c6174 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_GACB_PERF_CTRL,
 		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
 		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+	/* Wa_1405733216:icl
+	 * Formerly known as WaDisableCleanEvicts
+	 */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (4 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
                   ` (17 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 4 ++++
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fea85ac..43fdd2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8234,6 +8234,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
 #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
 
+#define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index f9c6174..642325a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -732,6 +732,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+	/* Wa_1405766107:icl
+	 * Formerly known as WaCL2SFHalfMaxAlloc
+	 */
+	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 08/22] drm/i915/icl: WaDisCtxReload
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (5 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 09/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
                   ` (16 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43fdd2e..161d04e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8238,6 +8238,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 642325a..75fad6f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
 				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
 				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+	/* Wa_220166154:icl
+	 * Formerly known as WaDisCtxReload
+	 */
+	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 09/22] drm/i915/icl: Wa_1405779004
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (6 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410 Oscar Mateo
                   ` (15 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 161d04e..9ab5731 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
 #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS		(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 75fad6f..76059ed 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
 					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
+	/* Wa_1405779004:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+			    MSCUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (7 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 09/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 11/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
                   ` (14 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 76059ed..57a69aa 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
 			    MSCUNIT_CLKGATE_DIS));
+
+	/* Wa_1406680159:icl */
+	/* Wa_2201832410:icl (pre-prod, only until C0) */
+	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+		    GWUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 11/22] drm/i915/icl: Wa_1604302699
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (8 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410 Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 12/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
                   ` (13 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ab5731..b462938 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,7 +7192,9 @@ enum {
 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
-#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+#define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
+#define  GEN7_WA_L3_CHICKEN_MODE		0x20000000
+#define  GEN11_I2M_WRITE_DISABLE		(1 << 28)
 
 #define GEN7_L3SQCREG4				_MMIO(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 57a69aa..0cebafa 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -757,6 +757,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
 		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
 		    GWUNIT_CLKGATE_DIS));
+
+	/* Wa_1604302699:icl */
+	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+		    GEN11_I2M_WRITE_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 12/22] drm/i915/icl: Wa_1406838659
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (9 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 11/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
                   ` (12 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Disable CGPSF unit clock gating to prevent an issue.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 13 ++++++++-----
 drivers/gpu/drm/i915/intel_workarounds.c |  6 ++++++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b462938..fc09b83 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3838,15 +3838,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
-#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
-#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
+#define   SARBUNIT_CLKGATE_DIS		(1 << 5)
+#define   RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define   MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS		(1 << 16)
+#define   GWUNIT_CLKGATE_DIS		(1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define   VFUNIT_CLKGATE_DIS		(1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS		(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 0cebafa..72497e1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -762,6 +762,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
 		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
 		    GEN11_I2M_WRITE_DISABLE));
+
+	/* Wa_1406838659:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+			    CGPSF_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (10 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 12/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
                   ` (11 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc09b83..cfb9b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9711,6 +9711,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
 
+#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
+#define   PMFLUSHDONE_LNEBLK		(1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 72497e1..413a43d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -768,6 +768,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
 			    CGPSF_CLKGATE_DIS));
+
+	/* WaForwardProgressSoftReset:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(GEN10_SCRATCH_LNCF2,
+			   (I915_READ(GEN10_SCRATCH_LNCF2) |
+			    PMFLUSHDONE_LNICRSDROP |
+			    PMFLUSH_GAPL3UNBLOCK |
+			    PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (11 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
                   ` (10 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only
v4:
  - Add spaces around '<<' (and fix the surrounding code as well)
  - Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfb9b0d..fca143b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8284,8 +8284,9 @@ enum {
 
 #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
-#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
-#define   PUSH_CONSTANT_DEREF_DISABLE	(1<<8)
+#define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
+#define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
 
 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 413a43d..6c03af0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	 */
 	WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
 
+	/* Wa_2006611047:icl (pre-prod)
+	 * Formerly known as WaDisableImprovedTdlClkGating
+	 */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (12 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:00 ` [PATCH 16/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
                   ` (9 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fca143b..452e24d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7173,6 +7173,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
 
 #define GEN7_L3SQCREG1				_MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 6c03af0..5884a7d5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -466,6 +466,10 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+	/* WaEnableStateCacheRedirectToCS:icl */
+	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 16/22] drm/i915/icl: Wa_2006665173
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (13 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
@ 2018-04-13 16:00 ` Oscar Mateo
  2018-04-13 16:01 ` [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
                   ` (8 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:00 UTC (permalink / raw)
  To: intel-gfx

Disable blend embellishment in RCC.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 18 +++++++++++-------
 drivers/gpu/drm/i915/intel_workarounds.c |  5 +++++
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 452e24d..71696dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7157,13 +7157,17 @@ enum {
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
-#define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION	(1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
+  #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1 << 10) | (1 << 26))
+  #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
+
+#define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
+  #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
+  #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
+  #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
+  #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
 
 #define HIZ_CHICKEN					_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 5884a7d5..90906ab 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,11 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
 			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
 
+	/* Wa_2006665173:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (14 preceding siblings ...)
  2018-04-13 16:00 ` [PATCH 16/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
@ 2018-04-13 16:01 ` Oscar Mateo
  2018-04-13 16:01 ` [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
                   ` (7 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:01 UTC (permalink / raw)
  To: intel-gfx

Enables blend optimization for floating point RTs

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 71696dc..127d2a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
 
+#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
+
 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT			16
 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 90906ab..9e50fba 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,6 +475,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
+	/* WaEnableFloatBlendOptimization:icl */
+	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (15 preceding siblings ...)
  2018-04-13 16:01 ` [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
@ 2018-04-13 16:01 ` Oscar Mateo
  2018-04-13 16:01 ` [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
                   ` (6 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:01 UTC (permalink / raw)
  To: intel-gfx

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 9e50fba..970a763 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -956,6 +956,13 @@ static int cnl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 
 static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 {
+	int ret;
+
+	/* WaSendPushConstantsFromMMIO:icl */
+	ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (16 preceding siblings ...)
  2018-04-13 16:01 ` [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
@ 2018-04-13 16:01 ` Oscar Mateo
  2018-04-13 16:01 ` [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
                   ` (5 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:01 UTC (permalink / raw)
  To: intel-gfx

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 970a763..43dbeed 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -963,6 +963,11 @@ static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
+	/* WaAllowUMDToModifyHalfSliceChicken2:icl */
+	ret = wa_ring_whitelist_reg(engine, HALF_SLICE_CHICKEN2);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (17 preceding siblings ...)
  2018-04-13 16:01 ` [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
@ 2018-04-13 16:01 ` Oscar Mateo
  2018-04-13 16:01 ` [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
                   ` (4 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:01 UTC (permalink / raw)
  To: intel-gfx

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 43dbeed..8a76bc4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -968,6 +968,11 @@ static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
+	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
+	ret = wa_ring_whitelist_reg(engine, GEN9_HALF_SLICE_CHICKEN7);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (18 preceding siblings ...)
  2018-04-13 16:01 ` [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
@ 2018-04-13 16:01 ` Oscar Mateo
  2018-04-13 16:01 ` [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
                   ` (3 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:01 UTC (permalink / raw)
  To: intel-gfx

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 127d2a3..d008a70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8255,6 +8255,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 8a76bc4..b52ac41 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -973,6 +973,14 @@ static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
+	/* WaAllowUmdWriteTRTTRootTable:icl */
+	ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW0);
+	if (ret)
+		return ret;
+	ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW1);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (19 preceding siblings ...)
  2018-04-13 16:01 ` [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
@ 2018-04-13 16:01 ` Oscar Mateo
  2018-04-13 16:19 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds Patchwork
                   ` (2 subsequent siblings)
  23 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-13 16:01 UTC (permalink / raw)
  To: intel-gfx

Required for Bindless samplers.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d008a70..3394cc0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8258,6 +8258,8 @@ enum {
 #define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
 
+#define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b52ac41..d8f0cf9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -981,6 +981,11 @@ static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
+	/* WaAllowUMDToModifySamplerMode:icl */
+	ret = wa_ring_whitelist_reg(engine, GEN10_SAMPLER_MODE);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 31+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (20 preceding siblings ...)
  2018-04-13 16:01 ` [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
@ 2018-04-13 16:19 ` Patchwork
  2018-04-13 16:34 ` ✓ Fi.CI.BAT: success " Patchwork
  2018-04-13 20:11 ` ✓ Fi.CI.IGT: " Patchwork
  23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2018-04-13 16:19 UTC (permalink / raw)
  To: Oscar Mateo; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
URL   : https://patchwork.freedesktop.org/series/41687/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bc09764ddda4 drm/i915/icl: Introduce initial Icelake Workarounds
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:2471:
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 135 lines checked
5ae138861bbe drm/i915/icl: Enable Sampler DFR
b36a6c421a87 drm/i915/icl: WaGAPZPriorityScheme
011f158b8a19 drm/i915/icl: WaL3BankAddressHashing
a78f4ed1040f drm/i915/icl: WaModifyGamTlbPartitioning
e0c061b03dd4 drm/i915/icl: WaDisableCleanEvicts
8a6f39285391 drm/i915/icl: WaCL2SFHalfMaxAlloc
75938bbf671a drm/i915/icl: WaDisCtxReload
9f3dfb692dec drm/i915/icl: Wa_1405779004
005066f5b27e drm/i915/icl: Wa_1406680159 and Wa_2201832410
bb7e420ff378 drm/i915/icl: Wa_1604302699
e30c867f83d8 drm/i915/icl: Wa_1406838659
ed3af10bec1d drm/i915/icl: WaForwardProgressSoftReset
82515343b1a6 drm/i915/icl: WaDisableImprovedTdlClkGating
a9f9101ed56b drm/i915/icl: WaEnableStateCacheRedirectToCS
4c42d02cef0a drm/i915/icl: Wa_2006665173
a753045fa070 drm/i915/icl: WaEnableFloatBlendOptimization
40b8ef4094c1 drm/i915/icl: WaSendPushConstantsFromMMIO
4dfa2b45285d drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
317ef6d4aedf drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
797cfbca5d58 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
a5d656177b7e drm/i915/icl: WaAllowUMDToModifySamplerMode

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 31+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (21 preceding siblings ...)
  2018-04-13 16:19 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds Patchwork
@ 2018-04-13 16:34 ` Patchwork
  2018-04-13 20:11 ` ✓ Fi.CI.IGT: " Patchwork
  23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2018-04-13 16:34 UTC (permalink / raw)
  To: Oscar Mateo; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
URL   : https://patchwork.freedesktop.org/series/41687/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053 -> Patchwork_8688 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41687/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8688 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    
    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713


== Participating hosts (35 -> 33) ==

  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4053 -> Patchwork_8688

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8688: a5d656177b7ead3baa5b6629f814bb4edacd8b61 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

a5d656177b7e drm/i915/icl: WaAllowUMDToModifySamplerMode
797cfbca5d58 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
317ef6d4aedf drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
4dfa2b45285d drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
40b8ef4094c1 drm/i915/icl: WaSendPushConstantsFromMMIO
a753045fa070 drm/i915/icl: WaEnableFloatBlendOptimization
4c42d02cef0a drm/i915/icl: Wa_2006665173
a9f9101ed56b drm/i915/icl: WaEnableStateCacheRedirectToCS
82515343b1a6 drm/i915/icl: WaDisableImprovedTdlClkGating
ed3af10bec1d drm/i915/icl: WaForwardProgressSoftReset
e30c867f83d8 drm/i915/icl: Wa_1406838659
bb7e420ff378 drm/i915/icl: Wa_1604302699
005066f5b27e drm/i915/icl: Wa_1406680159 and Wa_2201832410
9f3dfb692dec drm/i915/icl: Wa_1405779004
75938bbf671a drm/i915/icl: WaDisCtxReload
8a6f39285391 drm/i915/icl: WaCL2SFHalfMaxAlloc
e0c061b03dd4 drm/i915/icl: WaDisableCleanEvicts
a78f4ed1040f drm/i915/icl: WaModifyGamTlbPartitioning
011f158b8a19 drm/i915/icl: WaL3BankAddressHashing
b36a6c421a87 drm/i915/icl: WaGAPZPriorityScheme
5ae138861bbe drm/i915/icl: Enable Sampler DFR
bc09764ddda4 drm/i915/icl: Introduce initial Icelake Workarounds

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8688/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 31+ messages in thread

* ✓ Fi.CI.IGT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
  2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
                   ` (22 preceding siblings ...)
  2018-04-13 16:34 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-04-13 20:11 ` Patchwork
  23 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2018-04-13 20:11 UTC (permalink / raw)
  To: Oscar Mateo; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds
URL   : https://patchwork.freedesktop.org/series/41687/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053_full -> Patchwork_8688_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8688_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8688_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41687/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8688_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_mocs_settings@mocs-rc6-ctx-render:
      shard-kbl:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_8688_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_atomic_transition@plane-toggle-modeset-transition:
      shard-hsw:          PASS -> DMESG-WARN (fdo#102614) +1

    igt@kms_flip@plain-flip-fb-recreate:
      shard-hsw:          PASS -> FAIL (fdo#100368)

    
    ==== Possible fixes ====

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 4) ==

  Missing    (2): shard-glk shard-glkb 


== Build changes ==

    * Linux: CI_DRM_4053 -> Patchwork_8688

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8688: a5d656177b7ead3baa5b6629f814bb4edacd8b61 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8688/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR
  2018-04-13 16:00 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
@ 2018-04-20  7:26   ` Sagar Arun Kamble
  0 siblings, 0 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2018-04-20  7:26 UTC (permalink / raw)
  To: Oscar Mateo, intel-gfx; +Cc: Praveen Paneri



On 4/13/2018 9:30 PM, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
>
> v2: Wrong operation to clear the bit (Praveen)
> v3: Rebased on top of the WA refactoring
>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Praveen Paneri <praveen.paneri@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>   drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f2ee225..4b7e6bc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8218,6 +8218,9 @@ enum {
>   #define GEN8_GARBCNTL                   _MMIO(0xB004)
>   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>   
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> +#define   DFR_DISABLE			(1 << 9)
> +
>   /* IVYBRIDGE DPF */
>   #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>   #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 8c2d17c..34a0b56 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   	I915_WRITE(_3D_CHICKEN3,
>   		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>   
> +	/* This is not an Wa. Enable to reduce Sampler power */
> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> +
>   	/* WaInPlaceDecompressionHang:icl */
>   	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>   					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));

-- 
Thanks,
Sagar

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
  2018-05-08 21:29 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
@ 2018-05-09 11:18   ` Mika Kuoppala
  0 siblings, 0 replies; 31+ messages in thread
From: Mika Kuoppala @ 2018-05-09 11:18 UTC (permalink / raw)
  To: Oscar Mateo, intel-gfx

Oscar Mateo <oscar.mateo@intel.com> writes:

> Avoids a hang during soft reset.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
> v4:
>   - Rebased
>   - C, not lisp (Chris)
>   - Which steppings affected by this are not clear.
>     For the moment, apply unconditionally as per the
>     BSpec (Mika)
>   - Add reference to another HSD also related
>
> References: HSDES#1405476379
> References: HSDES#2006612137
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
>  2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ce48427..1449178 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9897,6 +9897,11 @@ enum skl_power_gate {
>  /* Media decoder 2 MOCS registers */
>  #define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
>  
> +#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
> +#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
> +#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
> +#define   PMFLUSHDONE_LNEBLK		(1 << 22)
> +
>  /* gamt regs */
>  #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 942d322..5eec4ce 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
>  			   I915_READ(INF_UNIT_LEVEL_CLKGATE) |
>  			   CGPSF_CLKGATE_DIS);
> +
> +	/* WaForwardProgressSoftReset:icl */
> +	I915_WRITE(GEN10_SCRATCH_LNCF2,
> +		   I915_READ(GEN10_SCRATCH_LNCF2) |
> +		   PMFLUSHDONE_LNICRSDROP |
> +		   PMFLUSH_GAPL3UNBLOCK |
> +		   PMFLUSHDONE_LNEBLK);
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
  2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-05-08 21:29 ` Oscar Mateo
  2018-05-09 11:18   ` Mika Kuoppala
  0 siblings, 1 reply; 31+ messages in thread
From: Oscar Mateo @ 2018-05-08 21:29 UTC (permalink / raw)
  To: intel-gfx

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
  - Rebased
  - C, not lisp (Chris)
  - Which steppings affected by this are not clear.
    For the moment, apply unconditionally as per the
    BSpec (Mika)
  - Add reference to another HSD also related

References: HSDES#1405476379
References: HSDES#2006612137
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce48427..1449178 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9897,6 +9897,11 @@ enum skl_power_gate {
 /* Media decoder 2 MOCS registers */
 #define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
 
+#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
+#define   PMFLUSHDONE_LNEBLK		(1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 942d322..5eec4ce 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
 			   I915_READ(INF_UNIT_LEVEL_CLKGATE) |
 			   CGPSF_CLKGATE_DIS);
+
+	/* WaForwardProgressSoftReset:icl */
+	I915_WRITE(GEN10_SCRATCH_LNCF2,
+		   I915_READ(GEN10_SCRATCH_LNCF2) |
+		   PMFLUSHDONE_LNICRSDROP |
+		   PMFLUSH_GAPL3UNBLOCK |
+		   PMFLUSHDONE_LNEBLK);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
  2018-05-02 20:34 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
@ 2018-05-08 14:44   ` Mika Kuoppala
  0 siblings, 0 replies; 31+ messages in thread
From: Mika Kuoppala @ 2018-05-08 14:44 UTC (permalink / raw)
  To: Oscar Mateo, intel-gfx

Oscar Mateo <oscar.mateo@intel.com> writes:

> Avoids a hang during soft reset.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1405476379
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8caf42f..8da119f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9895,6 +9895,11 @@ enum skl_power_gate {
>  #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
>  #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
>  
> +#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
> +#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
> +#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
> +#define   PMFLUSHDONE_LNEBLK		(1 << 22)
> +
>  /* gamt regs */
>  #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 35f2de3..f89a5c2 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -761,6 +761,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
>  			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
>  			    CGPSF_CLKGATE_DIS));
> +
> +	/* WaForwardProgressSoftReset:icl (pre-prod) */
> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> +		I915_WRITE(GEN10_SCRATCH_LNCF2,
> +			   (I915_READ(GEN10_SCRATCH_LNCF2) |
> +			    PMFLUSHDONE_LNICRSDROP |
> +			    PMFLUSH_GAPL3UNBLOCK |
> +			    PMFLUSHDONE_LNEBLK));

The references on this are someone contradicting.

I did found anything that would point it being fixed in C0
even tho wa database says that for B0.

Bspec says that you must set these unconditionally.
I would go with the bspec and unconditionally enable these
three bits.

-Mika


>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
  2018-05-02 20:33 [PATCH v2 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-05-02 20:34 ` Oscar Mateo
  2018-05-08 14:44   ` Mika Kuoppala
  0 siblings, 1 reply; 31+ messages in thread
From: Oscar Mateo @ 2018-05-02 20:34 UTC (permalink / raw)
  To: intel-gfx

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1405476379
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8caf42f..8da119f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9895,6 +9895,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
 
+#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
+#define   PMFLUSHDONE_LNEBLK		(1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 35f2de3..f89a5c2 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -761,6 +761,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
 			    CGPSF_CLKGATE_DIS));
+
+	/* WaForwardProgressSoftReset:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(GEN10_SCRATCH_LNCF2,
+			   (I915_READ(GEN10_SCRATCH_LNCF2) |
+			    PMFLUSHDONE_LNICRSDROP |
+			    PMFLUSH_GAPL3UNBLOCK |
+			    PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset
  2018-04-20 20:33 [PATCH v4 00/22] Workarounds for Icelake Oscar Mateo
@ 2018-04-20 20:33 ` Oscar Mateo
  0 siblings, 0 replies; 31+ messages in thread
From: Oscar Mateo @ 2018-04-20 20:33 UTC (permalink / raw)
  To: intel-gfx

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc09b83..cfb9b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9711,6 +9711,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
 
+#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
+#define   PMFLUSHDONE_LNEBLK		(1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a9868e9..beb98c6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -768,6 +768,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
 			    CGPSF_CLKGATE_DIS));
+
+	/* WaForwardProgressSoftReset:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(GEN10_SCRATCH_LNCF2,
+			   (I915_READ(GEN10_SCRATCH_LNCF2) |
+			    PMFLUSHDONE_LNICRSDROP |
+			    PMFLUSH_GAPL3UNBLOCK |
+			    PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 31+ messages in thread

end of thread, other threads:[~2018-05-09 11:18 UTC | newest]

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-13 16:00 [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds Oscar Mateo
2018-04-13 16:00 ` [PATCH 02/22] drm/i915/icl: Enable Sampler DFR Oscar Mateo
2018-04-20  7:26   ` Sagar Arun Kamble
2018-04-13 16:00 ` [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme Oscar Mateo
2018-04-13 16:00 ` [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing Oscar Mateo
2018-04-13 16:00 ` [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning Oscar Mateo
2018-04-13 16:00 ` [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts Oscar Mateo
2018-04-13 16:00 ` [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc Oscar Mateo
2018-04-13 16:00 ` [PATCH 08/22] drm/i915/icl: WaDisCtxReload Oscar Mateo
2018-04-13 16:00 ` [PATCH 09/22] drm/i915/icl: Wa_1405779004 Oscar Mateo
2018-04-13 16:00 ` [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410 Oscar Mateo
2018-04-13 16:00 ` [PATCH 11/22] drm/i915/icl: Wa_1604302699 Oscar Mateo
2018-04-13 16:00 ` [PATCH 12/22] drm/i915/icl: Wa_1406838659 Oscar Mateo
2018-04-13 16:00 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
2018-04-13 16:00 ` [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
2018-04-13 16:00 ` [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
2018-04-13 16:00 ` [PATCH 16/22] drm/i915/icl: Wa_2006665173 Oscar Mateo
2018-04-13 16:01 ` [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
2018-04-13 16:01 ` [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
2018-04-13 16:01 ` [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
2018-04-13 16:01 ` [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
2018-04-13 16:01 ` [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
2018-04-13 16:01 ` [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
2018-04-13 16:19 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds Patchwork
2018-04-13 16:34 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-13 20:11 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-20 20:33 [PATCH v4 00/22] Workarounds for Icelake Oscar Mateo
2018-04-20 20:33 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
2018-05-02 20:33 [PATCH v2 00/22] Workarounds for Icelake Oscar Mateo
2018-05-02 20:34 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
2018-05-08 14:44   ` Mika Kuoppala
2018-05-08 21:29 [PATCH v3 00/22] Workarounds for Icelake Oscar Mateo
2018-05-08 21:29 ` [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset Oscar Mateo
2018-05-09 11:18   ` Mika Kuoppala

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