[PATCH v5 0/8] arm: Base support for Renesas RZN1D-DB Board

[PATCH v5 0/8] arm: Base support for Renesas RZN1D-DB Board

[Michel Pollet]

This series adds the plain basic support for booting a bare
kernel on the RZ/N1D-DB Board. It's been trimmed to the strict
minimum as a 'base', further patches that will add the
rest of the support, pinctrl, clock architecture and quite
a few others.

Thanks for the comments on the previous versions!

v5:
 + Given the problems I have with getting in some structure around the 
   sysctrl block, I've removed the MFD, I've now attached a simple reboot 
   driver on it's own pair of registers.
 + Rebased on next-20180417
v4:
 + Fixes for suggestions by Simon Horman
 + Fixes for suggestions by Jacopo Mondi
 + Fixes for suggestions by Geert Uytterhoeven
 + Renamed the r9a06g0xx.dtsi file, given up on trying to get a family
   common file in, so dropped potential RZ/N1S support and now only
   focus on RZ/N1D for this patchset.
 + Added 'always-on' to the architected timer node, because it is.
 + Added ARCH_R9A06G032, to match others patterns like RCAR
 + Sorted the .dts files, added empty lines as required.
 + Fixed patch prefixes to match git-log for bindings&dts
 + Merged board .dts & Makefile changes together
 + Rebased on next-20180410
v3:
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed SoC Specific renesas,r9a06g032-xxx, as it's not needed for now.
 + Kept renesas,rzn1 as a family/generic for this family.
 + Fixed a couple of the commit messages.
 + Added Geert's Reviewed-By where appropriate.
v2:
 + Fixes for suggestions by Simon Horman
 + Fixes for suggestions by Rob Herring
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed the mach file
 + Added a MFD base for the sysctrl block
 + Added a regmap based sub driver for the reboot handler
 + Renamed the files to match shmobile conventions
 + Adapted the compatible= strings to reflect 'family' vs 'part'
   distinction.
 + Removed the sysctrl.h file entirelly.
 + Fixed every warnings from the DTC compiler on W=12 mode.
 + Split the device-tree patches from the code.

Michel Pollet (6):
  arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig
  dt-bindings: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver
  dt-bindings: arm: Document the RZN1D-DB board
  ARM: dts: Renesas RZ/N1 SoC base device tree file
  ARM: dts: Renesas RZN1D-DB Board base file
  reset: Renesas RZ/N1 reboot driver

 Documentation/devicetree/bindings/arm/shmobile.txt |  5 +-
 .../bindings/power/renesas,rzn1-reboot.txt         | 17 ++++
 arch/arm/boot/dts/Makefile                         |  1 +
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts        | 29 +++++++
 arch/arm/boot/dts/r9a06g032.dtsi                   | 89 ++++++++++++++++++++
 arch/arm/mach-shmobile/Kconfig                     |  4 +
 drivers/power/reset/Kconfig                        |  7 ++
 drivers/power/reset/Makefile                       |  1 +
 drivers/power/reset/rzn1-reboot.c                  | 96 ++++++++++++++++++++++
 9 files changed, 248 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
 create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
 create mode 100644 drivers/power/reset/rzn1-reboot.c

-- 
2.7.4

[PATCH v5 0/8] arm: Base support for Renesas RZN1D-DB Board

[Michel Pollet]

This series adds the plain basic support for booting a bare
kernel on the RZ/N1D-DB Board. It's been trimmed to the strict
minimum as a 'base', further patches that will add the
rest of the support, pinctrl, clock architecture and quite
a few others.

Thanks for the comments on the previous versions!

v5:
 + Given the problems I have with getting in some structure around the 
   sysctrl block, I've removed the MFD, I've now attached a simple reboot 
   driver on it's own pair of registers.
 + Rebased on next-20180417
v4:
 + Fixes for suggestions by Simon Horman
 + Fixes for suggestions by Jacopo Mondi
 + Fixes for suggestions by Geert Uytterhoeven
 + Renamed the r9a06g0xx.dtsi file, given up on trying to get a family
   common file in, so dropped potential RZ/N1S support and now only
   focus on RZ/N1D for this patchset.
 + Added 'always-on' to the architected timer node, because it is.
 + Added ARCH_R9A06G032, to match others patterns like RCAR
 + Sorted the .dts files, added empty lines as required.
 + Fixed patch prefixes to match git-log for bindings&dts
 + Merged board .dts & Makefile changes together
 + Rebased on next-20180410
v3:
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed SoC Specific renesas,r9a06g032-xxx, as it's not needed for now.
 + Kept renesas,rzn1 as a family/generic for this family.
 + Fixed a couple of the commit messages.
 + Added Geert's Reviewed-By where appropriate.
v2:
 + Fixes for suggestions by Simon Horman
 + Fixes for suggestions by Rob Herring
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed the mach file
 + Added a MFD base for the sysctrl block
 + Added a regmap based sub driver for the reboot handler
 + Renamed the files to match shmobile conventions
 + Adapted the compatible= strings to reflect 'family' vs 'part'
   distinction.
 + Removed the sysctrl.h file entirelly.
 + Fixed every warnings from the DTC compiler on W=12 mode.
 + Split the device-tree patches from the code.

Michel Pollet (6):
  arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig
  dt-bindings: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver
  dt-bindings: arm: Document the RZN1D-DB board
  ARM: dts: Renesas RZ/N1 SoC base device tree file
  ARM: dts: Renesas RZN1D-DB Board base file
  reset: Renesas RZ/N1 reboot driver

 Documentation/devicetree/bindings/arm/shmobile.txt |  5 +-
 .../bindings/power/renesas,rzn1-reboot.txt         | 17 ++++
 arch/arm/boot/dts/Makefile                         |  1 +
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts        | 29 +++++++
 arch/arm/boot/dts/r9a06g032.dtsi                   | 89 ++++++++++++++++++++
 arch/arm/mach-shmobile/Kconfig                     |  4 +
 drivers/power/reset/Kconfig                        |  7 ++
 drivers/power/reset/Makefile                       |  1 +
 drivers/power/reset/rzn1-reboot.c                  | 96 ++++++++++++++++++++++
 9 files changed, 248 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
 create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
 create mode 100644 drivers/power/reset/rzn1-reboot.c

-- 
2.7.4

[PATCH v5 1/6] arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig

[Michel Pollet]

Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/mach-shmobile/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 96672da..fcc273f 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -114,6 +114,10 @@ config ARCH_R8A7794
 	bool "R-Car E2 (R8A77940)"
 	select ARCH_RCAR_GEN2
 
+config ARCH_R9A06G032
+	bool "RZ/N1D (R9A06G032)"
+	select ARCH_RZN1
+
 config ARCH_RZN1
 	bool "RZ/N1 (R9A06G0xx) Family"
 	select ARM_AMBA
-- 
2.7.4

[PATCH v5 1/6] arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig

[Michel Pollet]

Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/mach-shmobile/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 96672da..fcc273f 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -114,6 +114,10 @@ config ARCH_R8A7794
 	bool "R-Car E2 (R8A77940)"
 	select ARCH_RCAR_GEN2
 
+config ARCH_R9A06G032
+	bool "RZ/N1D (R9A06G032)"
+	select ARCH_RZN1
+
 config ARCH_RZN1
 	bool "RZ/N1 (R9A06G0xx) Family"
 	select ARM_AMBA
-- 
2.7.4

[PATCH v5 2/6] dt-bindings: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 .../devicetree/bindings/power/renesas,rzn1-reboot.txt   | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt

diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
new file mode 100644
index 0000000..a553864
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
@@ -0,0 +1,17 @@
+DT bindings for the Renesas RZ/N1 Reboot Driver
+
+== Reboot Driver Node ==
+
+The reboot driver allows restarting the RZ/N1.
+
+Bindings:
++ Required:
+	compatible = "renesas,r9a06g032-reboot", "renesas,rzn1-reboot";
+
+Example:
+	reboot@4000c120 {
+		compatible = "renesas,r9a06g032-reboot",
+				"renesas,rzn1-reboot";
+		reg = <0x4000c120 4>,
+			<0x4000c198 4>;
+	};
-- 
2.7.4

[PATCH v5 2/6] dt-bindings: reset: renesas, rzn1-reboot: document RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 .../devicetree/bindings/power/renesas,rzn1-reboot.txt   | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt

diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
new file mode 100644
index 0000000..a553864
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
@@ -0,0 +1,17 @@
+DT bindings for the Renesas RZ/N1 Reboot Driver
+
+== Reboot Driver Node ==
+
+The reboot driver allows restarting the RZ/N1.
+
+Bindings:
++ Required:
+	compatible = "renesas,r9a06g032-reboot", "renesas,rzn1-reboot";
+
+Example:
+	reboot at 4000c120 {
+		compatible = "renesas,r9a06g032-reboot",
+				"renesas,rzn1-reboot";
+		reg = <0x4000c120 4>,
+			<0x4000c198 4>;
+	};
-- 
2.7.4

[PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Michel Pollet]

This documents the RZ/N1 bindings for the RZN1D-DB board.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 61b486f..6efb3f1 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
     compatible = "renesas,r8a77990"
   - R-Car D3 (R8A77995)
     compatible = "renesas,r8a77995"
-
+  - RZ/N1D (R9A06G032)
+    compatible = "renesas,r9a06g032", "renesas,rzn1"
 
 Boards:
 
@@ -112,6 +113,8 @@ Boards:
     compatible = "renesas,porter", "renesas,r8a7791"
   - RSKRZA1 (YR0K77210C000BE)
     compatible = "renesas,rskrza1", "renesas,r7s72100"
+  - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+    compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1"
   - Salvator-X (RTP0RC7795SIPB0010S)
     compatible = "renesas,salvator-x", "renesas,r8a7795"
   - Salvator-X (RTP0RC7796SIPB0011S)
-- 
2.7.4

[PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Michel Pollet]

This documents the RZ/N1 bindings for the RZN1D-DB board.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 61b486f..6efb3f1 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
     compatible = "renesas,r8a77990"
   - R-Car D3 (R8A77995)
     compatible = "renesas,r8a77995"
-
+  - RZ/N1D (R9A06G032)
+    compatible = "renesas,r9a06g032", "renesas,rzn1"
 
 Boards:
 
@@ -112,6 +113,8 @@ Boards:
     compatible = "renesas,porter", "renesas,r8a7791"
   - RSKRZA1 (YR0K77210C000BE)
     compatible = "renesas,rskrza1", "renesas,r7s72100"
+  - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+    compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1"
   - Salvator-X (RTP0RC7795SIPB0010S)
     compatible = "renesas,salvator-x", "renesas,r8a7795"
   - Salvator-X (RTP0RC7796SIPB0011S)
-- 
2.7.4

[PATCH v5 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file

[Michel Pollet]

This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.

This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
new file mode 100644
index 0000000..23c56d7
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a06g032", "renesas,rzn1";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clkuarts: clkuarts {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <47619047>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		reboot@4000c120 {
+			compatible = "renesas,r9a06g032-reboot",
+					"renesas,rzn1-reboot";
+			reg = <0x4000c120 4>,
+				<0x4000c198 4>;
+		};
+
+		uart0: serial@40060000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x40060000 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&clkuarts>;
+			clock-names = "baudclk";
+			status = "disabled";
+		};
+
+		gic: gic@44101000 {
+			compatible = "arm,cortex-a7-gic", "arm,gic-400";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x44101000 0x1000>, /* Distributer */
+			      <0x44102000 0x2000>, /* CPU interface */
+			      <0x44104000 0x2000>, /* Virt interface control */
+			      <0x44106000 0x2000>; /* Virt CPU interface */
+			interrupts =
+				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	timer {
+		compatible = "arm,cortex-a7-timer",
+			     "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+		interrupts =
+			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.7.4

[PATCH v5 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file

[Michel Pollet]

This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.

This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
new file mode 100644
index 0000000..23c56d7
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a06g032", "renesas,rzn1";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clkuarts: clkuarts {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <47619047>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		reboot at 4000c120 {
+			compatible = "renesas,r9a06g032-reboot",
+					"renesas,rzn1-reboot";
+			reg = <0x4000c120 4>,
+				<0x4000c198 4>;
+		};
+
+		uart0: serial at 40060000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x40060000 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&clkuarts>;
+			clock-names = "baudclk";
+			status = "disabled";
+		};
+
+		gic: gic at 44101000 {
+			compatible = "arm,cortex-a7-gic", "arm,gic-400";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x44101000 0x1000>, /* Distributer */
+			      <0x44102000 0x2000>, /* CPU interface */
+			      <0x44104000 0x2000>, /* Virt interface control */
+			      <0x44106000 0x2000>; /* Virt CPU interface */
+			interrupts =
+				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	timer {
+		compatible = "arm,cortex-a7-timer",
+			     "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+		interrupts =
+			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.7.4

[PATCH v5 5/6] ARM: dts: Renesas RZN1D-DB Board base file

[Michel Pollet]

This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/Makefile                  |  1 +
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 052aaf0..a53a677 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -809,6 +809,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 	r8a7793-gose.dtb \
 	r8a7794-alt.dtb \
 	r8a7794-silk.dtb \
+	r9a06g032-rzn1d400-db.dtb \
 	sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1108-evb.dtb \
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 0000000..5fc2c40
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+
+/ {
+	model = "RZN1D-DB Board";
+	compatible = "renesas,rzn1d400-db",
+			"renesas,r9a06g032", "renesas,rzn1";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.7.4

[PATCH v5 5/6] ARM: dts: Renesas RZN1D-DB Board base file

[Michel Pollet]

This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/Makefile                  |  1 +
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 052aaf0..a53a677 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -809,6 +809,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 	r8a7793-gose.dtb \
 	r8a7794-alt.dtb \
 	r8a7794-silk.dtb \
+	r9a06g032-rzn1d400-db.dtb \
 	sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1108-evb.dtb \
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 0000000..5fc2c40
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+
+/ {
+	model = "RZN1D-DB Board";
+	compatible = "renesas,rzn1d400-db",
+			"renesas,r9a06g032", "renesas,rzn1";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.7.4

[PATCH v5 6/6] reset: Renesas RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 drivers/power/reset/Kconfig       |  7 +++
 drivers/power/reset/Makefile      |  1 +
 drivers/power/reset/rzn1-reboot.c | 96 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 104 insertions(+)
 create mode 100644 drivers/power/reset/rzn1-reboot.c

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index df58fc8..1416d88 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -144,6 +144,13 @@ config POWER_RESET_RESTART
 	  Instead they restart, and u-boot holds the SoC until the
 	  user presses a key. u-boot then boots into Linux.
 
+config POWER_RESET_RZN1
+	bool "Renesas RZ/N1 reboot driver"
+	depends on ARCH_RZN1
+	help
+	  This driver allows rebooting the CA7 cores of the
+	  Renesas RZ/N1 Family of SoC (Part # R9A06G0xx).
+
 config POWER_RESET_ST
 	bool "ST restart driver"
 	depends on ARCH_STI
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 7778c74..bad9702 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
 obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+obj-$(CONFIG_POWER_RESET_RZN1) += rzn1-reboot.o
 obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
 obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o
 obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
diff --git a/drivers/power/reset/rzn1-reboot.c b/drivers/power/reset/rzn1-reboot.c
new file mode 100644
index 0000000..43876d5
--- /dev/null
+++ b/drivers/power/reset/rzn1-reboot.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 reboot driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ * Derived from zx-reboot.c
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+
+/* Definitions from the SDK rzn1-sysctrl.h autogenerated file */
+#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN		0
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN		1
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN_MASK		0x6
+#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN		3
+#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN		4
+#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN		5
+#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN			6
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ		1
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ_MASK	0x6
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDM3RST_REQ		3
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3LOCKUPRST_REQ	4
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3SYSRESET_REQ	5
+#define RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ		6
+
+static void __iomem *reg_rsten, *reg_rstctrl;
+
+static int rzn1_reboot_handler(struct notifier_block *this,
+			      unsigned long mode, void *cmd)
+{
+	writel(readl(reg_rsten) |
+			BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
+			BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN),
+		reg_rsten);
+	writel(readl(reg_rstctrl) |
+			BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ),
+		reg_rstctrl);
+
+	mdelay(50);
+	pr_emerg("Unable to restart system\n");
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block rzn1_reboot_nb = {
+	.notifier_call = rzn1_reboot_handler,
+	.priority = 128,
+};
+
+static int rzn1_reboot_probe(struct platform_device *ofdev)
+{
+	int err;
+
+	reg_rsten = of_iomap(ofdev->dev.of_node, 0);
+	reg_rstctrl = of_iomap(ofdev->dev.of_node, 1);
+
+	if (!reg_rsten || !reg_rstctrl) {
+		dev_err(&ofdev->dev, "invalid register mapping\n");
+		return -ENODEV;
+	}
+
+	err = register_restart_handler(&rzn1_reboot_nb);
+	if (err) {
+		dev_err(&ofdev->dev, "register restart handler failed(err=%d)\n",
+			err);
+	}
+
+	return err;
+}
+
+static const struct of_device_id rzn1_reboot_of_match[] = {
+	{ .compatible = "renesas,rzn1-reboot" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
+
+static struct platform_driver rzn1_reboot_driver = {
+	.probe = rzn1_reboot_probe,
+	.driver = {
+		.name = "rzn1-reboot",
+		.of_match_table = rzn1_reboot_of_match,
+	},
+};
+module_platform_driver(rzn1_reboot_driver);
+
+MODULE_DESCRIPTION("RZ/N1 reboot driver");
+MODULE_AUTHOR("Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

[PATCH v5 6/6] reset: Renesas RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 drivers/power/reset/Kconfig       |  7 +++
 drivers/power/reset/Makefile      |  1 +
 drivers/power/reset/rzn1-reboot.c | 96 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 104 insertions(+)
 create mode 100644 drivers/power/reset/rzn1-reboot.c

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index df58fc8..1416d88 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -144,6 +144,13 @@ config POWER_RESET_RESTART
 	  Instead they restart, and u-boot holds the SoC until the
 	  user presses a key. u-boot then boots into Linux.
 
+config POWER_RESET_RZN1
+	bool "Renesas RZ/N1 reboot driver"
+	depends on ARCH_RZN1
+	help
+	  This driver allows rebooting the CA7 cores of the
+	  Renesas RZ/N1 Family of SoC (Part # R9A06G0xx).
+
 config POWER_RESET_ST
 	bool "ST restart driver"
 	depends on ARCH_STI
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 7778c74..bad9702 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
 obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+obj-$(CONFIG_POWER_RESET_RZN1) += rzn1-reboot.o
 obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
 obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o
 obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
diff --git a/drivers/power/reset/rzn1-reboot.c b/drivers/power/reset/rzn1-reboot.c
new file mode 100644
index 0000000..43876d5
--- /dev/null
+++ b/drivers/power/reset/rzn1-reboot.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 reboot driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ * Derived from zx-reboot.c
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+
+/* Definitions from the SDK rzn1-sysctrl.h autogenerated file */
+#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN		0
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN		1
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN_MASK		0x6
+#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN		3
+#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN		4
+#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN		5
+#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN			6
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ		1
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ_MASK	0x6
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDM3RST_REQ		3
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3LOCKUPRST_REQ	4
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3SYSRESET_REQ	5
+#define RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ		6
+
+static void __iomem *reg_rsten, *reg_rstctrl;
+
+static int rzn1_reboot_handler(struct notifier_block *this,
+			      unsigned long mode, void *cmd)
+{
+	writel(readl(reg_rsten) |
+			BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
+			BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN),
+		reg_rsten);
+	writel(readl(reg_rstctrl) |
+			BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ),
+		reg_rstctrl);
+
+	mdelay(50);
+	pr_emerg("Unable to restart system\n");
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block rzn1_reboot_nb = {
+	.notifier_call = rzn1_reboot_handler,
+	.priority = 128,
+};
+
+static int rzn1_reboot_probe(struct platform_device *ofdev)
+{
+	int err;
+
+	reg_rsten = of_iomap(ofdev->dev.of_node, 0);
+	reg_rstctrl = of_iomap(ofdev->dev.of_node, 1);
+
+	if (!reg_rsten || !reg_rstctrl) {
+		dev_err(&ofdev->dev, "invalid register mapping\n");
+		return -ENODEV;
+	}
+
+	err = register_restart_handler(&rzn1_reboot_nb);
+	if (err) {
+		dev_err(&ofdev->dev, "register restart handler failed(err=%d)\n",
+			err);
+	}
+
+	return err;
+}
+
+static const struct of_device_id rzn1_reboot_of_match[] = {
+	{ .compatible = "renesas,rzn1-reboot" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
+
+static struct platform_driver rzn1_reboot_driver = {
+	.probe = rzn1_reboot_probe,
+	.driver = {
+		.name = "rzn1-reboot",
+		.of_match_table = rzn1_reboot_of_match,
+	},
+};
+module_platform_driver(rzn1_reboot_driver);
+
+MODULE_DESCRIPTION("RZ/N1 reboot driver");
+MODULE_AUTHOR("Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

Re: [PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Rob Herring]

On Tue, Apr 17, 2018 at 12:04:18PM +0100, Michel Pollet wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)

Please add acks/reviewed-bys when posting new versions.

Rob

[PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Rob Herring]

On Tue, Apr 17, 2018 at 12:04:18PM +0100, Michel Pollet wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)

Please add acks/reviewed-bys when posting new versions.

Rob

Re: [PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Geert Uytterhoeven]

Hi Michel,

On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
> index 61b486f..6efb3f1 100644
> --- a/Documentation/devicetree/bindings/arm/shmobile.txt
> +++ b/Documentation/devicetree/bindings/arm/shmobile.txt
> @@ -51,7 +51,8 @@ SoCs:
>      compatible = "renesas,r8a77990"
>    - R-Car D3 (R8A77995)
>      compatible = "renesas,r8a77995"
> -
> +  - RZ/N1D (R9A06G032)
> +    compatible = "renesas,r9a06g032", "renesas,rzn1"

Why do you need a family-specific compatible value ("renesas,rzn1",
which is a marketing name)?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Geert Uytterhoeven]

Hi Michel,

On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
> index 61b486f..6efb3f1 100644
> --- a/Documentation/devicetree/bindings/arm/shmobile.txt
> +++ b/Documentation/devicetree/bindings/arm/shmobile.txt
> @@ -51,7 +51,8 @@ SoCs:
>      compatible = "renesas,r8a77990"
>    - R-Car D3 (R8A77995)
>      compatible = "renesas,r8a77995"
> -
> +  - RZ/N1D (R9A06G032)
> +    compatible = "renesas,r9a06g032", "renesas,rzn1"

Why do you need a family-specific compatible value ("renesas,rzn1",
which is a marketing name)?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 2/6] dt-bindings: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Geert Uytterhoeven]

Hi Michel,

On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> as part of the sysctrl MFD to handle rebooting the CA7 cores.
> This documents the driver bindings.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  .../devicetree/bindings/power/renesas,rzn1-reboot.txt   | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
>
> diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> new file mode 100644
> index 0000000..a553864
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> @@ -0,0 +1,17 @@
> +DT bindings for the Renesas RZ/N1 Reboot Driver
> +
> +== Reboot Driver Node ==
> +
> +The reboot driver allows restarting the RZ/N1.
> +
> +Bindings:
> ++ Required:
> +       compatible = "renesas,r9a06g032-reboot", "renesas,rzn1-reboot";
> +
> +Example:
> +       reboot@4000c120 {
> +               compatible = "renesas,r9a06g032-reboot",
> +                               "renesas,rzn1-reboot";
> +               reg = <0x4000c120 4>,
> +                       <0x4000c198 4>;
> +       };

I'm afraid this will become a messy DT structure, once device nodes for the
registers just before, between, and after these 2 registers will be added...

There's really only a single multi-function sysctrl device here, using a 4 KiB
block at 0x4000c000, containing a mix of:
  1. Clock Control Registers (Table 6.1 [*]),
  2. Reset Control (Table 6.2 [*]),
  3. System Configuration (Table 6.3 [*]).

Looks a lot like the mix used in the Amiga's custom chip block at 0xdff000,
which also cannot be separated into logical blocks without listing individual
registers ;-)

So I suggest to have a DT binding for the whole block, and a clock driver
matching against the whole block, registering all clocks and a small reset
controller driver.

[*] RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: System
    Introduction, Multiplexing, Electrical and Mechanical Information.
    https://www.renesas.com/en-eu/doc/products/mpumcu/doc/rz/r01uh0750ej0090-rzn1-introduction.pdf

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v5 2/6] dt-bindings: reset: renesas, rzn1-reboot: document RZ/N1 reboot driver

[Geert Uytterhoeven]

Hi Michel,

On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> as part of the sysctrl MFD to handle rebooting the CA7 cores.
> This documents the driver bindings.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  .../devicetree/bindings/power/renesas,rzn1-reboot.txt   | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
>
> diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> new file mode 100644
> index 0000000..a553864
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> @@ -0,0 +1,17 @@
> +DT bindings for the Renesas RZ/N1 Reboot Driver
> +
> +== Reboot Driver Node ==
> +
> +The reboot driver allows restarting the RZ/N1.
> +
> +Bindings:
> ++ Required:
> +       compatible = "renesas,r9a06g032-reboot", "renesas,rzn1-reboot";
> +
> +Example:
> +       reboot at 4000c120 {
> +               compatible = "renesas,r9a06g032-reboot",
> +                               "renesas,rzn1-reboot";
> +               reg = <0x4000c120 4>,
> +                       <0x4000c198 4>;
> +       };

I'm afraid this will become a messy DT structure, once device nodes for the
registers just before, between, and after these 2 registers will be added...

There's really only a single multi-function sysctrl device here, using a 4 KiB
block at 0x4000c000, containing a mix of:
  1. Clock Control Registers (Table 6.1 [*]),
  2. Reset Control (Table 6.2 [*]),
  3. System Configuration (Table 6.3 [*]).

Looks a lot like the mix used in the Amiga's custom chip block at 0xdff000,
which also cannot be separated into logical blocks without listing individual
registers ;-)

So I suggest to have a DT binding for the whole block, and a clock driver
matching against the whole block, registering all clocks and a small reset
controller driver.

[*] RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User?s Manual: System
    Introduction, Multiplexing, Electrical and Mechanical Information.
    https://www.renesas.com/en-eu/doc/products/mpumcu/doc/rz/r01uh0750ej0090-rzn1-introduction.pdf

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Simon Horman]

On Tue, Apr 17, 2018 at 05:49:25PM +0200, Geert Uytterhoeven wrote:
> Hi Michel,
> 
> On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
> <michel.pollet@bp.renesas.com> wrote:
> > This documents the RZ/N1 bindings for the RZN1D-DB board.
> >
> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> > ---
> >  Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
> > index 61b486f..6efb3f1 100644
> > --- a/Documentation/devicetree/bindings/arm/shmobile.txt
> > +++ b/Documentation/devicetree/bindings/arm/shmobile.txt
> > @@ -51,7 +51,8 @@ SoCs:
> >      compatible = "renesas,r8a77990"
> >    - R-Car D3 (R8A77995)
> >      compatible = "renesas,r8a77995"
> > -
> > +  - RZ/N1D (R9A06G032)
> > +    compatible = "renesas,r9a06g032", "renesas,rzn1"
> 
> Why do you need a family-specific compatible value ("renesas,rzn1",
> which is a marketing name)?

Thanks Michel, Thanks Geert,

it looks like this extra compatible value should be dropped.
Its not consistent with the way other Renesas SoC families are handled
and past experience has not lead us to want family-specific compatible
values.

[PATCH v5 3/6] dt-bindings: arm: Document the RZN1D-DB board

[Simon Horman]

On Tue, Apr 17, 2018 at 05:49:25PM +0200, Geert Uytterhoeven wrote:
> Hi Michel,
> 
> On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
> <michel.pollet@bp.renesas.com> wrote:
> > This documents the RZ/N1 bindings for the RZN1D-DB board.
> >
> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> > ---
> >  Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
> > index 61b486f..6efb3f1 100644
> > --- a/Documentation/devicetree/bindings/arm/shmobile.txt
> > +++ b/Documentation/devicetree/bindings/arm/shmobile.txt
> > @@ -51,7 +51,8 @@ SoCs:
> >      compatible = "renesas,r8a77990"
> >    - R-Car D3 (R8A77995)
> >      compatible = "renesas,r8a77995"
> > -
> > +  - RZ/N1D (R9A06G032)
> > +    compatible = "renesas,r9a06g032", "renesas,rzn1"
> 
> Why do you need a family-specific compatible value ("renesas,rzn1",
> which is a marketing name)?

Thanks Michel, Thanks Geert,

it looks like this extra compatible value should be dropped.
Its not consistent with the way other Renesas SoC families are handled
and past experience has not lead us to want family-specific compatible
values.

Re: [PATCH v5 1/6] arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig

[Simon Horman]

On Tue, Apr 17, 2018 at 12:04:16PM +0100, Michel Pollet wrote:
> Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

Thanks, applied.

[PATCH v5 1/6] arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig

[Simon Horman]

On Tue, Apr 17, 2018 at 12:04:16PM +0100, Michel Pollet wrote:
> Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

Thanks, applied.

Re: [PATCH v5 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file

[Simon Horman]

On Tue, Apr 17, 2018 at 12:04:19PM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
> 
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  arch/arm/boot/dts/r9a06g032.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 89 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
> 
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> new file mode 100644
> index 0000000..23c56d7
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "renesas,r9a06g032", "renesas,rzn1";

As discussed elsewhere, please drop "renesas,rzn1".

> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	clkuarts: clkuarts {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <47619047>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0>;
> +		};
> +
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <1>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		reboot@4000c120 {
> +			compatible = "renesas,r9a06g032-reboot",
> +					"renesas,rzn1-reboot";
> +			reg = <0x4000c120 4>,
> +				<0x4000c198 4>;
> +		};
> +
> +		uart0: serial@40060000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x40060000 0x400>;
> +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&clkuarts>;
> +			clock-names = "baudclk";
> +			status = "disabled";
> +		};
> +
> +		gic: gic@44101000 {
> +			compatible = "arm,cortex-a7-gic", "arm,gic-400";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0x44101000 0x1000>, /* Distributer */
> +			      <0x44102000 0x2000>, /* CPU interface */
> +			      <0x44104000 0x2000>, /* Virt interface control */
> +			      <0x44106000 0x2000>; /* Virt CPU interface */
> +			interrupts =
> +				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,cortex-a7-timer",
> +			     "arm,armv7-timer";
> +		interrupt-parent = <&gic>;
> +		arm,cpu-registers-not-fw-configured;
> +		always-on;
> +		interrupts =
> +			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

Rather than using interrupt-parent, please use interrupts-extended,
something like this:

		interrupts-extended =
			<&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;


> +	};
> +};
> -- 
> 2.7.4
> 

[PATCH v5 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file

[Simon Horman]

On Tue, Apr 17, 2018 at 12:04:19PM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
> 
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  arch/arm/boot/dts/r9a06g032.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 89 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
> 
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> new file mode 100644
> index 0000000..23c56d7
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "renesas,r9a06g032", "renesas,rzn1";

As discussed elsewhere, please drop "renesas,rzn1".

> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	clkuarts: clkuarts {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <47619047>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0>;
> +		};
> +
> +		cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <1>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		reboot at 4000c120 {
> +			compatible = "renesas,r9a06g032-reboot",
> +					"renesas,rzn1-reboot";
> +			reg = <0x4000c120 4>,
> +				<0x4000c198 4>;
> +		};
> +
> +		uart0: serial at 40060000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x40060000 0x400>;
> +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&clkuarts>;
> +			clock-names = "baudclk";
> +			status = "disabled";
> +		};
> +
> +		gic: gic at 44101000 {
> +			compatible = "arm,cortex-a7-gic", "arm,gic-400";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0x44101000 0x1000>, /* Distributer */
> +			      <0x44102000 0x2000>, /* CPU interface */
> +			      <0x44104000 0x2000>, /* Virt interface control */
> +			      <0x44106000 0x2000>; /* Virt CPU interface */
> +			interrupts =
> +				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,cortex-a7-timer",
> +			     "arm,armv7-timer";
> +		interrupt-parent = <&gic>;
> +		arm,cpu-registers-not-fw-configured;
> +		always-on;
> +		interrupts =
> +			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

Rather than using interrupt-parent, please use interrupts-extended,
something like this:

		interrupts-extended =
			<&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;


> +	};
> +};
> -- 
> 2.7.4
> 

Re: [PATCH v5 6/6] reset: Renesas RZ/N1 reboot driver

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 5388 bytes --]

Hi,

On Tue, Apr 17, 2018 at 12:04:21PM +0100, Michel Pollet wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
> to reboot the Cortex-A7 cores. This driver is a sub driver of
> the sysctrl MFD.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  drivers/power/reset/Kconfig       |  7 +++
>  drivers/power/reset/Makefile      |  1 +
>  drivers/power/reset/rzn1-reboot.c | 96 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 104 insertions(+)
>  create mode 100644 drivers/power/reset/rzn1-reboot.c
> 
> diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
> index df58fc8..1416d88 100644
> --- a/drivers/power/reset/Kconfig
> +++ b/drivers/power/reset/Kconfig
> @@ -144,6 +144,13 @@ config POWER_RESET_RESTART
>  	  Instead they restart, and u-boot holds the SoC until the
>  	  user presses a key. u-boot then boots into Linux.
>  
> +config POWER_RESET_RZN1
> +	bool "Renesas RZ/N1 reboot driver"
> +	depends on ARCH_RZN1
> +	help
> +	  This driver allows rebooting the CA7 cores of the
> +	  Renesas RZ/N1 Family of SoC (Part # R9A06G0xx).
> +
>  config POWER_RESET_ST
>  	bool "ST restart driver"
>  	depends on ARCH_STI
> diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
> index 7778c74..bad9702 100644
> --- a/drivers/power/reset/Makefile
> +++ b/drivers/power/reset/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
>  obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
>  obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
>  obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
> +obj-$(CONFIG_POWER_RESET_RZN1) += rzn1-reboot.o
>  obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
>  obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o
>  obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
> diff --git a/drivers/power/reset/rzn1-reboot.c b/drivers/power/reset/rzn1-reboot.c
> new file mode 100644
> index 0000000..43876d5
> --- /dev/null
> +++ b/drivers/power/reset/rzn1-reboot.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/N1 reboot driver
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
> + * Derived from zx-reboot.c
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +
> +/* Definitions from the SDK rzn1-sysctrl.h autogenerated file */
> +#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN		0
> +#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN		1
> +#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN_MASK		0x6
> +#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN		3
> +#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN		4
> +#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN		5
> +#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN			6
> +#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ		1
> +#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ_MASK	0x6
> +#define RZN1_SYSCTRL_REG_RSTCTRL_WDM3RST_REQ		3
> +#define RZN1_SYSCTRL_REG_RSTCTRL_CM3LOCKUPRST_REQ	4
> +#define RZN1_SYSCTRL_REG_RSTCTRL_CM3SYSRESET_REQ	5
> +#define RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ		6
> +
> +static void __iomem *reg_rsten, *reg_rstctrl;

Please make this into a proper driver and allocate this dynamically.
You can get device context from the notifier_block, see for example
gpio-restart.

> +static int rzn1_reboot_handler(struct notifier_block *this,
> +			      unsigned long mode, void *cmd)
> +{
> +	writel(readl(reg_rsten) |
> +			BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
> +			BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN),
> +		reg_rsten);
> +	writel(readl(reg_rstctrl) |
> +			BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ),
> +		reg_rstctrl);
> +
> +	mdelay(50);
> +	pr_emerg("Unable to restart system\n");
> +
> +	return NOTIFY_DONE;
> +}
> +
> +static struct notifier_block rzn1_reboot_nb = {
> +	.notifier_call = rzn1_reboot_handler,
> +	.priority = 128,
> +};
> +
> +static int rzn1_reboot_probe(struct platform_device *ofdev)
> +{
> +	int err;
> +
> +	reg_rsten = of_iomap(ofdev->dev.of_node, 0);
> +	reg_rstctrl = of_iomap(ofdev->dev.of_node, 1);

Please use devm_ioremap().

> +
> +	if (!reg_rsten || !reg_rstctrl) {
> +		dev_err(&ofdev->dev, "invalid register mapping\n");
> +		return -ENODEV;
> +	}
> +
> +	err = register_restart_handler(&rzn1_reboot_nb);
> +	if (err) {
> +		dev_err(&ofdev->dev, "register restart handler failed(err=%d)\n",
> +			err);
> +	}

Missing unregister_restart_handler() in .remove.

> +
> +	return err;
> +}
> +
> +static const struct of_device_id rzn1_reboot_of_match[] = {
> +	{ .compatible = "renesas,rzn1-reboot" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
> +
> +static struct platform_driver rzn1_reboot_driver = {
> +	.probe = rzn1_reboot_probe,
> +	.driver = {
> +		.name = "rzn1-reboot",
> +		.of_match_table = rzn1_reboot_of_match,
> +	},
> +};
> +module_platform_driver(rzn1_reboot_driver);
> +
> +MODULE_DESCRIPTION("RZ/N1 reboot driver");
> +MODULE_AUTHOR("Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>");
> +MODULE_LICENSE("GPL v2");

-- Sebastian

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[PATCH v5 6/6] reset: Renesas RZ/N1 reboot driver

[Sebastian Reichel]

Hi,

On Tue, Apr 17, 2018 at 12:04:21PM +0100, Michel Pollet wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
> to reboot the Cortex-A7 cores. This driver is a sub driver of
> the sysctrl MFD.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  drivers/power/reset/Kconfig       |  7 +++
>  drivers/power/reset/Makefile      |  1 +
>  drivers/power/reset/rzn1-reboot.c | 96 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 104 insertions(+)
>  create mode 100644 drivers/power/reset/rzn1-reboot.c
> 
> diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
> index df58fc8..1416d88 100644
> --- a/drivers/power/reset/Kconfig
> +++ b/drivers/power/reset/Kconfig
> @@ -144,6 +144,13 @@ config POWER_RESET_RESTART
>  	  Instead they restart, and u-boot holds the SoC until the
>  	  user presses a key. u-boot then boots into Linux.
>  
> +config POWER_RESET_RZN1
> +	bool "Renesas RZ/N1 reboot driver"
> +	depends on ARCH_RZN1
> +	help
> +	  This driver allows rebooting the CA7 cores of the
> +	  Renesas RZ/N1 Family of SoC (Part # R9A06G0xx).
> +
>  config POWER_RESET_ST
>  	bool "ST restart driver"
>  	depends on ARCH_STI
> diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
> index 7778c74..bad9702 100644
> --- a/drivers/power/reset/Makefile
> +++ b/drivers/power/reset/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
>  obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
>  obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
>  obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
> +obj-$(CONFIG_POWER_RESET_RZN1) += rzn1-reboot.o
>  obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
>  obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o
>  obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
> diff --git a/drivers/power/reset/rzn1-reboot.c b/drivers/power/reset/rzn1-reboot.c
> new file mode 100644
> index 0000000..43876d5
> --- /dev/null
> +++ b/drivers/power/reset/rzn1-reboot.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/N1 reboot driver
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
> + * Derived from zx-reboot.c
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +
> +/* Definitions from the SDK rzn1-sysctrl.h autogenerated file */
> +#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN		0
> +#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN		1
> +#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN_MASK		0x6
> +#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN		3
> +#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN		4
> +#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN		5
> +#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN			6
> +#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ		1
> +#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ_MASK	0x6
> +#define RZN1_SYSCTRL_REG_RSTCTRL_WDM3RST_REQ		3
> +#define RZN1_SYSCTRL_REG_RSTCTRL_CM3LOCKUPRST_REQ	4
> +#define RZN1_SYSCTRL_REG_RSTCTRL_CM3SYSRESET_REQ	5
> +#define RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ		6
> +
> +static void __iomem *reg_rsten, *reg_rstctrl;

Please make this into a proper driver and allocate this dynamically.
You can get device context from the notifier_block, see for example
gpio-restart.

> +static int rzn1_reboot_handler(struct notifier_block *this,
> +			      unsigned long mode, void *cmd)
> +{
> +	writel(readl(reg_rsten) |
> +			BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
> +			BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN),
> +		reg_rsten);
> +	writel(readl(reg_rstctrl) |
> +			BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ),
> +		reg_rstctrl);
> +
> +	mdelay(50);
> +	pr_emerg("Unable to restart system\n");
> +
> +	return NOTIFY_DONE;
> +}
> +
> +static struct notifier_block rzn1_reboot_nb = {
> +	.notifier_call = rzn1_reboot_handler,
> +	.priority = 128,
> +};
> +
> +static int rzn1_reboot_probe(struct platform_device *ofdev)
> +{
> +	int err;
> +
> +	reg_rsten = of_iomap(ofdev->dev.of_node, 0);
> +	reg_rstctrl = of_iomap(ofdev->dev.of_node, 1);

Please use devm_ioremap().

> +
> +	if (!reg_rsten || !reg_rstctrl) {
> +		dev_err(&ofdev->dev, "invalid register mapping\n");
> +		return -ENODEV;
> +	}
> +
> +	err = register_restart_handler(&rzn1_reboot_nb);
> +	if (err) {
> +		dev_err(&ofdev->dev, "register restart handler failed(err=%d)\n",
> +			err);
> +	}

Missing unregister_restart_handler() in .remove.

> +
> +	return err;
> +}
> +
> +static const struct of_device_id rzn1_reboot_of_match[] = {
> +	{ .compatible = "renesas,rzn1-reboot" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
> +
> +static struct platform_driver rzn1_reboot_driver = {
> +	.probe = rzn1_reboot_probe,
> +	.driver = {
> +		.name = "rzn1-reboot",
> +		.of_match_table = rzn1_reboot_of_match,
> +	},
> +};
> +module_platform_driver(rzn1_reboot_driver);
> +
> +MODULE_DESCRIPTION("RZ/N1 reboot driver");
> +MODULE_AUTHOR("Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>");
> +MODULE_LICENSE("GPL v2");

-- Sebastian
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