[PATCH v5 0/6] Enable NV12 support

[PATCH v5 0/6] Enable NV12 support

[Vidya Srinivas]

Enabling NV12 support:
- Framebuffer creation
- Primary and Sprite plane support
Patch series depend on Enable display workaround 827 patch
mentioned below submitted by Maarten

Changes from prev version:
Removed BXT support for NV12 due to WA826

Chandra Konduru (3):
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Maarten Lankhorst (2):
  drm/i915: Enable display workaround 827 for all planes, v2.
  drm/i915: Add skl_check_nv12_surface for NV12

Vidya Srinivas (1):
  drm/i915: Enable Display WA 0528

 drivers/gpu/drm/i915/intel_atomic_plane.c |   7 +-
 drivers/gpu/drm/i915/intel_display.c      | 175 ++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_drv.h          |   3 +
 drivers/gpu/drm/i915/intel_sprite.c       |  44 +++++++-
 4 files changed, 203 insertions(+), 26 deletions(-)

-- 
2.7.4

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[PATCH v5 1/6] drm/i915: Enable display workaround 827 for all planes, v2.

[Vidya Srinivas]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

The workaround was applied only to the primary plane, but is required
on all planes. Iterate over all planes in the crtc atomic check to see
if the workaround is enabled, and only perform the actual toggling in
the pre/post plane update functions.

Changes since v1:
- Track active NV12 planes in a nv12_planes bitmask. (Ville)

v2: Removing BROXTON support for NV12 due to WA826

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  7 ++++-
 drivers/gpu/drm/i915/intel_display.c      | 43 +++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_drv.h          |  1 +
 3 files changed, 33 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7481ce8..6d06878 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -183,11 +183,16 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	}
 
 	/* FIXME pre-g4x don't work like this */
-	if (intel_state->base.visible)
+	if (state->visible)
 		crtc_state->active_planes |= BIT(intel_plane->id);
 	else
 		crtc_state->active_planes &= ~BIT(intel_plane->id);
 
+	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+		crtc_state->nv12_planes |= BIT(intel_plane->id);
+	else
+		crtc_state->nv12_planes &= ~BIT(intel_plane->id);
+
 	return intel_plane_atomic_calc_changes(old_crtc_state,
 					       &crtc_state->base,
 					       old_plane_state,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 020900e..53f82fa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5138,6 +5138,22 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
 	return !old_crtc_state->ips_enabled;
 }
 
+static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
+			  const struct intel_crtc_state *crtc_state)
+{
+	if (!crtc_state->nv12_planes)
+		return false;
+
+	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+		return false;
+
+	if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+	       IS_CANNONLAKE(dev_priv))
+		return true;
+
+	return false;
+}
+
 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
@@ -5162,7 +5178,6 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 	if (old_primary_state) {
 		struct drm_plane_state *new_primary_state =
 			drm_atomic_get_new_plane_state(old_state, primary);
-		struct drm_framebuffer *fb = new_primary_state->fb;
 
 		intel_fbc_post_update(crtc);
 
@@ -5170,15 +5185,12 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 		    (needs_modeset(&pipe_config->base) ||
 		     !old_primary_state->visible))
 			intel_post_enable_primary(&crtc->base, pipe_config);
-
-		/* Display WA 827 */
-		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-		    IS_CANNONLAKE(dev_priv)) {
-			if (fb && fb->format->format == DRM_FORMAT_NV12)
-				skl_wa_clkgate(dev_priv, crtc->pipe, false);
-		}
-
 	}
+
+	/* Display WA 827 */
+	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
+	    !needs_nv12_wa(dev_priv, pipe_config))
+		skl_wa_clkgate(dev_priv, crtc->pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5202,14 +5214,6 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 		struct intel_plane_state *new_primary_state =
 			intel_atomic_get_new_plane_state(old_intel_state,
 							 to_intel_plane(primary));
-		struct drm_framebuffer *fb = new_primary_state->base.fb;
-
-		/* Display WA 827 */
-		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-		    IS_CANNONLAKE(dev_priv)) {
-			if (fb && fb->format->format == DRM_FORMAT_NV12)
-				skl_wa_clkgate(dev_priv, crtc->pipe, true);
-		}
 
 		intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
 		/*
@@ -5221,6 +5225,11 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 	}
 
+	/* Display WA 827 */
+	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
+	    needs_nv12_wa(dev_priv, pipe_config))
+		skl_wa_clkgate(dev_priv, crtc->pipe, true);
+
 	/*
 	 * Vblank time updates from the shadow to live plane control register
 	 * are blocked if the memory self-refresh mode is active at that
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5bd2263..d8930676 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -882,6 +882,7 @@ struct intel_crtc_state {
 
 	/* bitmask of visible planes (enum plane_id) */
 	u8 active_planes;
+	u8 nv12_planes;
 
 	/* HDMI scrambling status */
 	bool hdmi_scrambling;
-- 
2.7.4

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[PATCH v5 2/6] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
	Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

v10: Addressed review comments from Maarten.
	Adding NV12 inside skl_primary_formats itself.

v11: Adding Reviewed By tag from Shashank Sharma

v12: Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v13: Addressed review comments from Ville
Added skl_pri_planar_formats to include NV12
and skl_plane_has_planar function to check for
NV12 support on plane. Added NV12 format to
skl_mod_supported. These were review comments
from Kristian Høgsberg <hoegsberg@gmail.com>

v14: Added reviewed by from Juha-Pekka Heikkila

v15: Rebased the series

v16: Added all tiling support under mod supported
for NV12. Credits to Megha Aggarwal

v17: Added RB by Maarten and Kristian

v18: Review comments from Maarten addressed -
Removing BROXTON support for NV12 due to WA826

Credits-to: Megha Aggarwal megha.aggarwal@intel.com
Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 55 ++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53f82fa..dc9c424 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,6 +88,22 @@ static const uint32_t skl_primary_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static const uint32_t skl_pri_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 static const uint64_t skl_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -13127,6 +13143,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier)
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */
+	case DRM_FORMAT_NV12:
+		if (modifier == DRM_FORMAT_MOD_LINEAR ||
+		    modifier == I915_FORMAT_MOD_X_TILED ||
+		    modifier == I915_FORMAT_MOD_Y_TILED ||
+		    modifier == I915_FORMAT_MOD_Yf_TILED)
+			return true;
 	case DRM_FORMAT_C8:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
@@ -13331,6 +13353,30 @@ static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
 	return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
 }
 
+bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
+			  enum pipe pipe, enum plane_id plane_id)
+{
+	if (plane_id == PLANE_PRIMARY) {
+		if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+			return false;
+		else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
+			 !IS_GEMINILAKE(dev_priv))
+			return false;
+	} else if (plane_id >= PLANE_SPRITE0) {
+		if (plane_id == PLANE_CURSOR)
+			return false;
+		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
+			if (plane_id != PLANE_SPRITE0)
+				return false;
+		} else {
+			if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
+			    IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+				return false;
+		}
+	}
+	return true;
+}
+
 static struct intel_plane *
 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
@@ -13391,8 +13437,13 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	primary->check_plane = intel_check_primary_plane;
 
 	if (INTEL_GEN(dev_priv) >= 9) {
-		intel_primary_formats = skl_primary_formats;
-		num_formats = ARRAY_SIZE(skl_primary_formats);
+		if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+			intel_primary_formats = skl_pri_planar_formats;
+			num_formats = ARRAY_SIZE(skl_pri_planar_formats);
+		} else {
+			intel_primary_formats = skl_primary_formats;
+			num_formats = ARRAY_SIZE(skl_primary_formats);
+		}
 
 		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
 			modifiers = skl_format_modifiers_ccs;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d8930676..01352ef 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2063,6 +2063,8 @@ bool skl_plane_get_hw_state(struct intel_plane *plane);
 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, enum plane_id plane_id);
 bool intel_format_is_yuv(uint32_t format);
+bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
+			  enum pipe pipe, enum plane_id plane_id);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
-- 
2.7.4

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[PATCH v5 3/6] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

v11: Addressed review comments from Shashank Sharma

v12: Addressed review comments from Shashank Sharma
Made the condition in intel_sprite_plane_create
simple and easy to read as suggested.

v13: Adding reviewed by tag from Shashank Sharma
Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v14: Addressed review comments from Ville
Added skl_planar_formats to include NV12
and a check skl_plane_has_planar in sprite create
Added NV12 format to skl_mod_supported. These were
review comments from Kristian Høgsberg <hoegsberg@gmail.com>

v15: Added reviewed by from Juha-Pekka Heikkila

v16: Rebased the series

v17: Added all tiling under mod supported for NV12
Credits to Megha Aggarwal

v18: Added RB by Maarten and Kristian

Credits-to: Megha Aggarwal <megha.aggarwal@intel.com>
Credits-to: Kristian Høgsberg <hoegsberg@gmail.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index aa1dfaa..8b7947d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1253,6 +1253,19 @@ static uint32_t skl_plane_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static uint32_t skl_planar_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1350,6 +1363,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier)
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */
+	case DRM_FORMAT_NV12:
+		if (modifier == DRM_FORMAT_MOD_LINEAR ||
+		    modifier == I915_FORMAT_MOD_X_TILED ||
+		    modifier == I915_FORMAT_MOD_Y_TILED ||
+		    modifier == I915_FORMAT_MOD_Yf_TILED)
+			return true;
 	case DRM_FORMAT_C8:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
@@ -1446,8 +1465,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		intel_plane->disable_plane = skl_disable_plane;
 		intel_plane->get_hw_state = skl_plane_get_hw_state;
 
-		plane_formats = skl_plane_formats;
-		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		if (skl_plane_has_planar(dev_priv, pipe,
+					 PLANE_SPRITE0 + plane)) {
+			plane_formats = skl_planar_formats;
+			num_plane_formats = ARRAY_SIZE(skl_planar_formats);
+		} else {
+			plane_formats = skl_plane_formats;
+			num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		}
 
 		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
 			modifiers = skl_plane_format_modifiers_ccs;
-- 
2.7.4

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[PATCH] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable

v11: Addressed review comments from Shashank Sharma

v12: Adding Reviewed By from Shashank Sharma

v13: Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v14: Addressed review comments from Maarten.
Add checks for fb width height for NV12 and fail the fb
creation if check fails. Added reviewed by from
Juha-Pekka Heikkila

v15: Rebased the series

v16: Setting the minimum value during fb creating to 16
as per Bspec for NV12. Earlier minimum was expected
to be > 16. Now changed it to >=16.

v17: Adding restriction to framebuffer_init - the fb
width and height should be a multiplier of 4

v18: Added RB from Maarten. Included Maarten's review comments
Dont allow CCS formats for fb creation of NV12

v19: Review comments from Maarten addressed -
Removing BROXTON support for NV12 due to WA826

Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc9c424..356336c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14264,6 +14264,20 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_NV12:
+		if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
+		    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
+			DRM_DEBUG_KMS("RC not to be enabled with NV12\n");
+			goto err;
+		}
+		if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
+		    IS_BROXTON(dev_priv)) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+				      drm_get_format_name(mode_cmd->pixel_format,
+							  &format_name));
+			goto err;
+		}
+		break;
 	default:
 		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
@@ -14276,6 +14290,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 
 	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
 
+	if (fb->format->format == DRM_FORMAT_NV12 &&
+	    (fb->width < SKL_MIN_YUV_420_SRC_W ||
+	     fb->height < SKL_MIN_YUV_420_SRC_H ||
+	     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
+		DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
+		return -EINVAL;
+	}
+
 	for (i = 0; i < fb->format->num_planes; i++) {
 		u32 stride_alignment;
 
-- 
2.7.4

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[PATCH v5 5/6] drm/i915: Enable Display WA 0528

[Vidya Srinivas]

Possible hang with NV12 plane surface formats.
WA: When the plane source pixel format is NV12,
the CHICKEN_PIPESL_* register bit 22 must be set to 1
and the render decompression must not be enabled
on any of the planes in that pipe.

v2: removed unnecessary POSTING_READ

v3: Added RB from Maarten

v4: Removed support for NV12 for BROXTON

Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 641bf9e..3e1c26a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -505,9 +505,21 @@ static const struct intel_limit intel_limits_bxt = {
 };
 
 static void
+skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
+{
+	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+		return;
+
+	if (enable)
+		I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
+	else
+		I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
+}
+
+static void
 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 {
-	if (IS_SKYLAKE(dev_priv))
+	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 		return;
 
 	if (enable)
@@ -5205,8 +5217,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 
 	/* Display WA 827 */
 	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    !needs_nv12_wa(dev_priv, pipe_config))
+	    !needs_nv12_wa(dev_priv, pipe_config)) {
 		skl_wa_clkgate(dev_priv, crtc->pipe, false);
+		skl_wa_528(dev_priv, crtc->pipe, false);
+	}
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5243,8 +5257,10 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 
 	/* Display WA 827 */
 	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    needs_nv12_wa(dev_priv, pipe_config))
+	    needs_nv12_wa(dev_priv, pipe_config)) {
 		skl_wa_clkgate(dev_priv, crtc->pipe, true);
+		skl_wa_528(dev_priv, crtc->pipe, true);
+	}
 
 	/*
 	 * Vblank time updates from the shadow to live plane control register
-- 
2.7.4

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[PATCH v5 6/6] drm/i915: Add skl_check_nv12_surface for NV12

[Vidya Srinivas]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

We skip src trunction/adjustments for
NV12 case and handle the sizes directly.
Without this, pipe fifo underruns are seen on APL/KBL.

v2: For NV12, making the src coordinates multiplier of 4

v3: Moving all the src coords handling code for NV12
to skl_check_nv12_surface

v4: Added RB from Mika

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 39 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 15 ++++++++++----
 2 files changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e1c26a..dcbc70d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3118,6 +3118,42 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
+static int
+skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
+		       struct intel_plane_state *plane_state)
+{
+	int crtc_x2 = plane_state->base.crtc_x + plane_state->base.crtc_w;
+	int crtc_y2 = plane_state->base.crtc_y + plane_state->base.crtc_h;
+
+	if (((plane_state->base.src_x >> 16) % 4) != 0 ||
+	    ((plane_state->base.src_y >> 16) % 4) != 0 ||
+	    ((plane_state->base.src_w >> 16) % 4) != 0 ||
+	    ((plane_state->base.src_h >> 16) % 4) != 0) {
+		DRM_DEBUG_KMS("src coords must be multiple of 4 for NV12\n");
+		return -EINVAL;
+	}
+
+	/* Clipping would cause a 1-3 pixel gap at the edge of the screen? */
+	if ((crtc_x2 > crtc_state->pipe_src_w && crtc_state->pipe_src_w % 4) ||
+	    (crtc_y2 > crtc_state->pipe_src_h && crtc_state->pipe_src_h % 4)) {
+		DRM_DEBUG_KMS("It's not possible to clip %u,%u to %u,%u\n",
+			      crtc_x2, crtc_y2,
+			      crtc_state->pipe_src_w, crtc_state->pipe_src_h);
+		return -EINVAL;
+	}
+
+	plane_state->base.src.x1 =
+		DIV_ROUND_CLOSEST(plane_state->base.src.x1, 1 << 18) << 18;
+	plane_state->base.src.x2 =
+		DIV_ROUND_CLOSEST(plane_state->base.src.x2, 1 << 18) << 18;
+	plane_state->base.src.y1 =
+		DIV_ROUND_CLOSEST(plane_state->base.src.y1, 1 << 18) << 18;
+	plane_state->base.src.y2 =
+		DIV_ROUND_CLOSEST(plane_state->base.src.y2, 1 << 18) << 18;
+
+	return 0;
+}
+
 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
@@ -3201,6 +3237,9 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
 	 * the main surface setup depends on it.
 	 */
 	if (fb->format->format == DRM_FORMAT_NV12) {
+		ret = skl_check_nv12_surface(crtc_state, plane_state);
+		if (ret)
+			return ret;
 		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8b7947d..f9985fb 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1035,10 +1035,17 @@ intel_check_sprite_plane(struct intel_plane *plane,
 			return vscale;
 		}
 
-		/* Make the source viewport size an exact multiple of the scaling factors. */
-		drm_rect_adjust_size(src,
-				     drm_rect_width(dst) * hscale - drm_rect_width(src),
-				     drm_rect_height(dst) * vscale - drm_rect_height(src));
+		if (fb->format->format != DRM_FORMAT_NV12) {
+			/*
+			 * Make the source viewport size
+			 * an exact multiple of the scaling factors
+			 */
+			drm_rect_adjust_size(src,
+					     (drm_rect_width(dst) * hscale -
+					      drm_rect_width(src)),
+					     (drm_rect_height(dst) * vscale -
+					      drm_rect_height(src)));
+		}
 
 		drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 				    state->base.rotation);
-- 
2.7.4

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Re: [PATCH] drm/i915: Add NV12 support to intel_framebuffer_init

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 10094 bytes --]

Hi Chandra,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17-rc1 next-20180420]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Vidya-Srinivas/drm-i915-Add-NV12-support-to-intel_framebuffer_init/20180420-184309
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x014-201815 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_display.c: In function 'intel_framebuffer_init':
>> drivers/gpu/drm/i915/intel_display.c:14142:19: error: 'SKL_MIN_YUV_420_SRC_W' undeclared (first use in this function); did you mean 'SKL_MIN_SRC_W'?
         (fb->width < SKL_MIN_YUV_420_SRC_W ||
                      ^~~~~~~~~~~~~~~~~~~~~
                      SKL_MIN_SRC_W
   drivers/gpu/drm/i915/intel_display.c:14142:19: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_display.c:14143:20: error: 'SKL_MIN_YUV_420_SRC_H' undeclared (first use in this function); did you mean 'SKL_MIN_YUV_420_SRC_W'?
          fb->height < SKL_MIN_YUV_420_SRC_H ||
                       ^~~~~~~~~~~~~~~~~~~~~
                       SKL_MIN_YUV_420_SRC_W
   make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1
   make[4]: Target '__build' not remade because of errors.

vim +14142 drivers/gpu/drm/i915/intel_display.c

 13968	
 13969	static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 13970					  struct drm_i915_gem_object *obj,
 13971					  struct drm_mode_fb_cmd2 *mode_cmd)
 13972	{
 13973		struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 13974		struct drm_framebuffer *fb = &intel_fb->base;
 13975		struct drm_format_name_buf format_name;
 13976		u32 pitch_limit;
 13977		unsigned int tiling, stride;
 13978		int ret = -EINVAL;
 13979		int i;
 13980	
 13981		i915_gem_object_lock(obj);
 13982		obj->framebuffer_references++;
 13983		tiling = i915_gem_object_get_tiling(obj);
 13984		stride = i915_gem_object_get_stride(obj);
 13985		i915_gem_object_unlock(obj);
 13986	
 13987		if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
 13988			/*
 13989			 * If there's a fence, enforce that
 13990			 * the fb modifier and tiling mode match.
 13991			 */
 13992			if (tiling != I915_TILING_NONE &&
 13993			    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 13994				DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
 13995				goto err;
 13996			}
 13997		} else {
 13998			if (tiling == I915_TILING_X) {
 13999				mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
 14000			} else if (tiling == I915_TILING_Y) {
 14001				DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
 14002				goto err;
 14003			}
 14004		}
 14005	
 14006		/* Passed in modifier sanity checking. */
 14007		switch (mode_cmd->modifier[0]) {
 14008		case I915_FORMAT_MOD_Y_TILED_CCS:
 14009		case I915_FORMAT_MOD_Yf_TILED_CCS:
 14010			switch (mode_cmd->pixel_format) {
 14011			case DRM_FORMAT_XBGR8888:
 14012			case DRM_FORMAT_ABGR8888:
 14013			case DRM_FORMAT_XRGB8888:
 14014			case DRM_FORMAT_ARGB8888:
 14015				break;
 14016			default:
 14017				DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
 14018				goto err;
 14019			}
 14020			/* fall through */
 14021		case I915_FORMAT_MOD_Y_TILED:
 14022		case I915_FORMAT_MOD_Yf_TILED:
 14023			if (INTEL_GEN(dev_priv) < 9) {
 14024				DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
 14025					      mode_cmd->modifier[0]);
 14026				goto err;
 14027			}
 14028		case DRM_FORMAT_MOD_LINEAR:
 14029		case I915_FORMAT_MOD_X_TILED:
 14030			break;
 14031		default:
 14032			DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
 14033				      mode_cmd->modifier[0]);
 14034			goto err;
 14035		}
 14036	
 14037		/*
 14038		 * gen2/3 display engine uses the fence if present,
 14039		 * so the tiling mode must match the fb modifier exactly.
 14040		 */
 14041		if (INTEL_GEN(dev_priv) < 4 &&
 14042		    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 14043			DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
 14044			goto err;
 14045		}
 14046	
 14047		pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
 14048						   mode_cmd->pixel_format);
 14049		if (mode_cmd->pitches[0] > pitch_limit) {
 14050			DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
 14051				      mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
 14052				      "tiled" : "linear",
 14053				      mode_cmd->pitches[0], pitch_limit);
 14054			goto err;
 14055		}
 14056	
 14057		/*
 14058		 * If there's a fence, enforce that
 14059		 * the fb pitch and fence stride match.
 14060		 */
 14061		if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
 14062			DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
 14063				      mode_cmd->pitches[0], stride);
 14064			goto err;
 14065		}
 14066	
 14067		/* Reject formats not supported by any plane early. */
 14068		switch (mode_cmd->pixel_format) {
 14069		case DRM_FORMAT_C8:
 14070		case DRM_FORMAT_RGB565:
 14071		case DRM_FORMAT_XRGB8888:
 14072		case DRM_FORMAT_ARGB8888:
 14073			break;
 14074		case DRM_FORMAT_XRGB1555:
 14075			if (INTEL_GEN(dev_priv) > 3) {
 14076				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14077					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14078				goto err;
 14079			}
 14080			break;
 14081		case DRM_FORMAT_ABGR8888:
 14082			if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 14083			    INTEL_GEN(dev_priv) < 9) {
 14084				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14085					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14086				goto err;
 14087			}
 14088			break;
 14089		case DRM_FORMAT_XBGR8888:
 14090		case DRM_FORMAT_XRGB2101010:
 14091		case DRM_FORMAT_XBGR2101010:
 14092			if (INTEL_GEN(dev_priv) < 4) {
 14093				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14094					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14095				goto err;
 14096			}
 14097			break;
 14098		case DRM_FORMAT_ABGR2101010:
 14099			if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
 14100				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14101					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14102				goto err;
 14103			}
 14104			break;
 14105		case DRM_FORMAT_YUYV:
 14106		case DRM_FORMAT_UYVY:
 14107		case DRM_FORMAT_YVYU:
 14108		case DRM_FORMAT_VYUY:
 14109			if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
 14110				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14111					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14112				goto err;
 14113			}
 14114			break;
 14115		case DRM_FORMAT_NV12:
 14116			if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
 14117			    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
 14118				DRM_DEBUG_KMS("RC not to be enabled with NV12\n");
 14119				goto err;
 14120			}
 14121			if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
 14122			    IS_BROXTON(dev_priv)) {
 14123				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14124					      drm_get_format_name(mode_cmd->pixel_format,
 14125								  &format_name));
 14126				goto err;
 14127			}
 14128			break;
 14129		default:
 14130			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14131				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14132			goto err;
 14133		}
 14134	
 14135		/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
 14136		if (mode_cmd->offsets[0] != 0)
 14137			goto err;
 14138	
 14139		drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
 14140	
 14141		if (fb->format->format == DRM_FORMAT_NV12 &&
 14142		    (fb->width < SKL_MIN_YUV_420_SRC_W ||
 14143		     fb->height < SKL_MIN_YUV_420_SRC_H ||
 14144		     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
 14145			DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
 14146			return -EINVAL;
 14147		}
 14148	
 14149		for (i = 0; i < fb->format->num_planes; i++) {
 14150			u32 stride_alignment;
 14151	
 14152			if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
 14153				DRM_DEBUG_KMS("bad plane %d handle\n", i);
 14154				goto err;
 14155			}
 14156	
 14157			stride_alignment = intel_fb_stride_alignment(fb, i);
 14158	
 14159			/*
 14160			 * Display WA #0531: skl,bxt,kbl,glk
 14161			 *
 14162			 * Render decompression and plane width > 3840
 14163			 * combined with horizontal panning requires the
 14164			 * plane stride to be a multiple of 4. We'll just
 14165			 * require the entire fb to accommodate that to avoid
 14166			 * potential runtime errors at plane configuration time.
 14167			 */
 14168			if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
 14169			    (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 14170			     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
 14171				stride_alignment *= 4;
 14172	
 14173			if (fb->pitches[i] & (stride_alignment - 1)) {
 14174				DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
 14175					      i, fb->pitches[i], stride_alignment);
 14176				goto err;
 14177			}
 14178		}
 14179	
 14180		intel_fb->obj = obj;
 14181	
 14182		ret = intel_fill_fb_info(dev_priv, fb);
 14183		if (ret)
 14184			goto err;
 14185	
 14186		ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
 14187		if (ret) {
 14188			DRM_ERROR("framebuffer init failed %d\n", ret);
 14189			goto err;
 14190		}
 14191	
 14192		return 0;
 14193	
 14194	err:
 14195		i915_gem_object_lock(obj);
 14196		obj->framebuffer_references--;
 14197		i915_gem_object_unlock(obj);
 14198		return ret;
 14199	}
 14200	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 36036 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Add NV12 support to intel_framebuffer_init

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 9809 bytes --]

Hi Chandra,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.17-rc1 next-20180420]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Vidya-Srinivas/drm-i915-Add-NV12-support-to-intel_framebuffer_init/20180420-184309
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x0-04201646 (attached as .config)
compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_display.c: In function 'intel_framebuffer_init':
   drivers/gpu/drm/i915/intel_display.c:14142:19: error: 'SKL_MIN_YUV_420_SRC_W' undeclared (first use in this function)
         (fb->width < SKL_MIN_YUV_420_SRC_W ||
                      ^
   drivers/gpu/drm/i915/intel_display.c:14142:19: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_display.c:14143:20: error: 'SKL_MIN_YUV_420_SRC_H' undeclared (first use in this function)
          fb->height < SKL_MIN_YUV_420_SRC_H ||
                       ^

vim +/SKL_MIN_YUV_420_SRC_H +14143 drivers/gpu/drm/i915/intel_display.c

 13968	
 13969	static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 13970					  struct drm_i915_gem_object *obj,
 13971					  struct drm_mode_fb_cmd2 *mode_cmd)
 13972	{
 13973		struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 13974		struct drm_framebuffer *fb = &intel_fb->base;
 13975		struct drm_format_name_buf format_name;
 13976		u32 pitch_limit;
 13977		unsigned int tiling, stride;
 13978		int ret = -EINVAL;
 13979		int i;
 13980	
 13981		i915_gem_object_lock(obj);
 13982		obj->framebuffer_references++;
 13983		tiling = i915_gem_object_get_tiling(obj);
 13984		stride = i915_gem_object_get_stride(obj);
 13985		i915_gem_object_unlock(obj);
 13986	
 13987		if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
 13988			/*
 13989			 * If there's a fence, enforce that
 13990			 * the fb modifier and tiling mode match.
 13991			 */
 13992			if (tiling != I915_TILING_NONE &&
 13993			    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 13994				DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
 13995				goto err;
 13996			}
 13997		} else {
 13998			if (tiling == I915_TILING_X) {
 13999				mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
 14000			} else if (tiling == I915_TILING_Y) {
 14001				DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
 14002				goto err;
 14003			}
 14004		}
 14005	
 14006		/* Passed in modifier sanity checking. */
 14007		switch (mode_cmd->modifier[0]) {
 14008		case I915_FORMAT_MOD_Y_TILED_CCS:
 14009		case I915_FORMAT_MOD_Yf_TILED_CCS:
 14010			switch (mode_cmd->pixel_format) {
 14011			case DRM_FORMAT_XBGR8888:
 14012			case DRM_FORMAT_ABGR8888:
 14013			case DRM_FORMAT_XRGB8888:
 14014			case DRM_FORMAT_ARGB8888:
 14015				break;
 14016			default:
 14017				DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
 14018				goto err;
 14019			}
 14020			/* fall through */
 14021		case I915_FORMAT_MOD_Y_TILED:
 14022		case I915_FORMAT_MOD_Yf_TILED:
 14023			if (INTEL_GEN(dev_priv) < 9) {
 14024				DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
 14025					      mode_cmd->modifier[0]);
 14026				goto err;
 14027			}
 14028		case DRM_FORMAT_MOD_LINEAR:
 14029		case I915_FORMAT_MOD_X_TILED:
 14030			break;
 14031		default:
 14032			DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
 14033				      mode_cmd->modifier[0]);
 14034			goto err;
 14035		}
 14036	
 14037		/*
 14038		 * gen2/3 display engine uses the fence if present,
 14039		 * so the tiling mode must match the fb modifier exactly.
 14040		 */
 14041		if (INTEL_GEN(dev_priv) < 4 &&
 14042		    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 14043			DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
 14044			goto err;
 14045		}
 14046	
 14047		pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
 14048						   mode_cmd->pixel_format);
 14049		if (mode_cmd->pitches[0] > pitch_limit) {
 14050			DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
 14051				      mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
 14052				      "tiled" : "linear",
 14053				      mode_cmd->pitches[0], pitch_limit);
 14054			goto err;
 14055		}
 14056	
 14057		/*
 14058		 * If there's a fence, enforce that
 14059		 * the fb pitch and fence stride match.
 14060		 */
 14061		if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
 14062			DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
 14063				      mode_cmd->pitches[0], stride);
 14064			goto err;
 14065		}
 14066	
 14067		/* Reject formats not supported by any plane early. */
 14068		switch (mode_cmd->pixel_format) {
 14069		case DRM_FORMAT_C8:
 14070		case DRM_FORMAT_RGB565:
 14071		case DRM_FORMAT_XRGB8888:
 14072		case DRM_FORMAT_ARGB8888:
 14073			break;
 14074		case DRM_FORMAT_XRGB1555:
 14075			if (INTEL_GEN(dev_priv) > 3) {
 14076				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14077					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14078				goto err;
 14079			}
 14080			break;
 14081		case DRM_FORMAT_ABGR8888:
 14082			if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 14083			    INTEL_GEN(dev_priv) < 9) {
 14084				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14085					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14086				goto err;
 14087			}
 14088			break;
 14089		case DRM_FORMAT_XBGR8888:
 14090		case DRM_FORMAT_XRGB2101010:
 14091		case DRM_FORMAT_XBGR2101010:
 14092			if (INTEL_GEN(dev_priv) < 4) {
 14093				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14094					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14095				goto err;
 14096			}
 14097			break;
 14098		case DRM_FORMAT_ABGR2101010:
 14099			if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
 14100				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14101					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14102				goto err;
 14103			}
 14104			break;
 14105		case DRM_FORMAT_YUYV:
 14106		case DRM_FORMAT_UYVY:
 14107		case DRM_FORMAT_YVYU:
 14108		case DRM_FORMAT_VYUY:
 14109			if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
 14110				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14111					      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14112				goto err;
 14113			}
 14114			break;
 14115		case DRM_FORMAT_NV12:
 14116			if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
 14117			    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
 14118				DRM_DEBUG_KMS("RC not to be enabled with NV12\n");
 14119				goto err;
 14120			}
 14121			if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
 14122			    IS_BROXTON(dev_priv)) {
 14123				DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14124					      drm_get_format_name(mode_cmd->pixel_format,
 14125								  &format_name));
 14126				goto err;
 14127			}
 14128			break;
 14129		default:
 14130			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 14131				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 14132			goto err;
 14133		}
 14134	
 14135		/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
 14136		if (mode_cmd->offsets[0] != 0)
 14137			goto err;
 14138	
 14139		drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
 14140	
 14141		if (fb->format->format == DRM_FORMAT_NV12 &&
 14142		    (fb->width < SKL_MIN_YUV_420_SRC_W ||
 14143		     fb->height < SKL_MIN_YUV_420_SRC_H ||
 14144		     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
 14145			DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
 14146			return -EINVAL;
 14147		}
 14148	
 14149		for (i = 0; i < fb->format->num_planes; i++) {
 14150			u32 stride_alignment;
 14151	
 14152			if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
 14153				DRM_DEBUG_KMS("bad plane %d handle\n", i);
 14154				goto err;
 14155			}
 14156	
 14157			stride_alignment = intel_fb_stride_alignment(fb, i);
 14158	
 14159			/*
 14160			 * Display WA #0531: skl,bxt,kbl,glk
 14161			 *
 14162			 * Render decompression and plane width > 3840
 14163			 * combined with horizontal panning requires the
 14164			 * plane stride to be a multiple of 4. We'll just
 14165			 * require the entire fb to accommodate that to avoid
 14166			 * potential runtime errors at plane configuration time.
 14167			 */
 14168			if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
 14169			    (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 14170			     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
 14171				stride_alignment *= 4;
 14172	
 14173			if (fb->pitches[i] & (stride_alignment - 1)) {
 14174				DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
 14175					      i, fb->pitches[i], stride_alignment);
 14176				goto err;
 14177			}
 14178		}
 14179	
 14180		intel_fb->obj = obj;
 14181	
 14182		ret = intel_fill_fb_info(dev_priv, fb);
 14183		if (ret)
 14184			goto err;
 14185	
 14186		ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
 14187		if (ret) {
 14188			DRM_ERROR("framebuffer init failed %d\n", ret);
 14189			goto err;
 14190		}
 14191	
 14192		return 0;
 14193	
 14194	err:
 14195		i915_gem_object_lock(obj);
 14196		obj->framebuffer_references--;
 14197		i915_gem_object_unlock(obj);
 14198		return ret;
 14199	}
 14200	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH v5 6/6] drm/i915: Add skl_check_nv12_surface for NV12

[Maarten Lankhorst]

Op 19-04-18 om 12:22 schreef Vidya Srinivas:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> We skip src trunction/adjustments for
> NV12 case and handle the sizes directly.
> Without this, pipe fifo underruns are seen on APL/KBL.
>
> v2: For NV12, making the src coordinates multiplier of 4
>
> v3: Moving all the src coords handling code for NV12
> to skl_check_nv12_surface
>
> v4: Added RB from Mika
>
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 39 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_sprite.c  | 15 ++++++++++----
>  2 files changed, 50 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3e1c26a..dcbc70d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3118,6 +3118,42 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
>  	return 0;
>  }
>  
> +static int
> +skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
> +		       struct intel_plane_state *plane_state)
> +{
> +	int crtc_x2 = plane_state->base.crtc_x + plane_state->base.crtc_w;
> +	int crtc_y2 = plane_state->base.crtc_y + plane_state->base.crtc_h;
> +
> +	if (((plane_state->base.src_x >> 16) % 4) != 0 ||
> +	    ((plane_state->base.src_y >> 16) % 4) != 0 ||
> +	    ((plane_state->base.src_w >> 16) % 4) != 0 ||
> +	    ((plane_state->base.src_h >> 16) % 4) != 0) {
> +		DRM_DEBUG_KMS("src coords must be multiple of 4 for NV12\n");
> +		return -EINVAL;
> +	}
> +
> +	/* Clipping would cause a 1-3 pixel gap at the edge of the screen? */
> +	if ((crtc_x2 > crtc_state->pipe_src_w && crtc_state->pipe_src_w % 4) ||
> +	    (crtc_y2 > crtc_state->pipe_src_h && crtc_state->pipe_src_h % 4)) {
> +		DRM_DEBUG_KMS("It's not possible to clip %u,%u to %u,%u\n",
> +			      crtc_x2, crtc_y2,
> +			      crtc_state->pipe_src_w, crtc_state->pipe_src_h);
> +		return -EINVAL;
> +	}
> +
> +	plane_state->base.src.x1 =
> +		DIV_ROUND_CLOSEST(plane_state->base.src.x1, 1 << 18) << 18;
> +	plane_state->base.src.x2 =
> +		DIV_ROUND_CLOSEST(plane_state->base.src.x2, 1 << 18) << 18;
> +	plane_state->base.src.y1 =
> +		DIV_ROUND_CLOSEST(plane_state->base.src.y1, 1 << 18) << 18;
> +	plane_state->base.src.y2 =
> +		DIV_ROUND_CLOSEST(plane_state->base.src.y2, 1 << 18) << 18;
> +
> +	return 0;
> +}
> +
>  static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
>  {
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
> @@ -3201,6 +3237,9 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
>  	 * the main surface setup depends on it.
>  	 */
>  	if (fb->format->format == DRM_FORMAT_NV12) {
> +		ret = skl_check_nv12_surface(crtc_state, plane_state);
> +		if (ret)
> +			return ret;
>  		ret = skl_check_nv12_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
Can this series be rebased on top of drm-tip? The changes to check_sprite_plane are interfering with this now.

Ideally in this order, for not breaking bisect:
1. [v5] drm/i915: Enable display workaround 827 for all planes, v2. <https://patchwork.freedesktop.org/patch/217887/>
2. [v5] drm/i915: Enable Display WA 0528 <https://patchwork.freedesktop.org/patch/217889/>
3. [v5] drm/i915: Add skl_check_nv12_surface for NV12 <https://patchwork.freedesktop.org/patch/217888/>
4. [v5] drm/i915: Add NV12 support to intel_framebuffer_init <https://patchwork.freedesktop.org/patch/217886/>
5. [v5] drm/i915: Add NV12 as supported format for primary plane <https://patchwork.freedesktop.org/patch/217884/>
6. [v5] drm/i915: Add NV12 as supported format for sprite plane <https://patchwork.freedesktop.org/patch/217885/>
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[PATCH v5 3/6] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

v11: Addressed review comments from Shashank Sharma

v12: Addressed review comments from Shashank Sharma
Made the condition in intel_sprite_plane_create
simple and easy to read as suggested.

v13: Adding reviewed by tag from Shashank Sharma
Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v14: Addressed review comments from Ville
Added skl_planar_formats to include NV12
and a check skl_plane_has_planar in sprite create
Added NV12 format to skl_mod_supported. These were
review comments from Kristian Høgsberg <hoegsberg@gmail.com>

v15: Added reviewed by from Juha-Pekka Heikkila

v16: Rebased the series

v17: Added all tiling under mod supported for NV12
Credits to Megha Aggarwal

v18: Added RB by Maarten and Kristian

Credits-to: Megha Aggarwal <megha.aggarwal@intel.com>
Credits-to: Kristian Høgsberg <hoegsberg@gmail.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index aa1dfaa..8b7947d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1253,6 +1253,19 @@ static uint32_t skl_plane_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static uint32_t skl_planar_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1350,6 +1363,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier)
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */
+	case DRM_FORMAT_NV12:
+		if (modifier == DRM_FORMAT_MOD_LINEAR ||
+		    modifier == I915_FORMAT_MOD_X_TILED ||
+		    modifier == I915_FORMAT_MOD_Y_TILED ||
+		    modifier == I915_FORMAT_MOD_Yf_TILED)
+			return true;
 	case DRM_FORMAT_C8:
 		if (modifier == DRM_FORMAT_MOD_LINEAR ||
 		    modifier == I915_FORMAT_MOD_X_TILED ||
@@ -1446,8 +1465,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		intel_plane->disable_plane = skl_disable_plane;
 		intel_plane->get_hw_state = skl_plane_get_hw_state;
 
-		plane_formats = skl_plane_formats;
-		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		if (skl_plane_has_planar(dev_priv, pipe,
+					 PLANE_SPRITE0 + plane)) {
+			plane_formats = skl_planar_formats;
+			num_plane_formats = ARRAY_SIZE(skl_planar_formats);
+		} else {
+			plane_formats = skl_plane_formats;
+			num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		}
 
 		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
 			modifiers = skl_plane_format_modifiers_ccs;
-- 
2.7.4

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