Bug#894995: rdma-core: Please add support for new architecture "riscv64" (RISC-V 64 bits little-endian)

Bug#894995: rdma-core: Please add support for new architecture "riscv64" (RISC-V 64 bits little-endian)

[Benjamin Drung]

Hi,

Thanks for reporting this bug.

Am Freitag, den 06.04.2018, 02:24 +0200 schrieb Manuel A. Fernandez
Montecelo:
> Source: rdma-core
> Version: 17.1-1
> Severity: normal
> Tags: patch
> User: debian-riscv@lists.debian.org
> Usertags: riscv64
> 
> Hello,
> 
> The current version of this package doesn't build for the riscv64
> port.
> 
> First it fails to be considered to build (due to missing valgrind)
> and, when
> fixing that problem, FBTFS, because of missing files (see at bottom).

I'll apply that part of the patch.

> I applied the same fix as for many other arches, which is to add the
> arch to the
> list of NO_COHERENT_DMA_ARCHS in debian/rules.
> 
> I am not sure if support could be added at a later date, but for the
> time being,
> seems to be the best way to get it working -- I don't know enough
> details of the
> architecture or the assembly language to get the necessary
> incantations in
> place.

RISC-V has a FENCE instruction and the A extension (which is part of
the G instruction set) provides atomic memory operations. So the
architecture should provide coherent DMA support. To enable support,
util/udma_barrier.h needs to be adjusted. I am including
linux-rdma@vger.kernel.org in the loop for help.

Bug#894995: rdma-core: Please add support for new architecture "riscv64" (RISC-V 64 bits little-endian)

[Jason Gunthorpe]

On Thu, Apr 19, 2018 at 02:00:18PM +0200, Benjamin Drung wrote:
> > I applied the same fix as for many other arches, which is to add the
> > arch to the
> > list of NO_COHERENT_DMA_ARCHS in debian/rules.
> > 
> > I am not sure if support could be added at a later date, but for the
> > time being,
> > seems to be the best way to get it working -- I don't know enough
> > details of the
> > architecture or the assembly language to get the necessary
> > incantations in
> > place.
> 
> RISC-V has a FENCE instruction and the A extension (which is part of
> the G instruction set) provides atomic memory operations. So the
> architecture should provide coherent DMA support. To enable support,
> util/udma_barrier.h needs to be adjusted. I am including
> linux-rdma@vger.kernel.org in the loop for help.

You can't tell from the instruction set if a chip is DMA coherent or
not. It depends how the cache's are designed, and if they have a
'snoop controller' or otherwise.

Generally if *any* DMA coherent implementations exist then we should
add the fences, otherwise better to just not compile the drivers that
have no chance of working.

Jason