From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9BvZ-0004jl-QT for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9BvY-0005Vq-Vu for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:53 -0400 Received: from smtp1.lauterbach.com ([62.154.241.196]:58206) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f9BvY-0005BP-EJ for qemu-devel@nongnu.org; Thu, 19 Apr 2018 11:56:52 -0400 Received: from unknown (HELO abo-VirtualBox.8.8.4.4) (Authenticated_SSL:abouassida@[41.224.44.126]) (envelope-sender ) by smtp1.lauterbach.com (qmail-ldap-1.03) with ECDHE-RSA-AES256-SHA encrypted SMTP for ; 19 Apr 2018 15:56:34 -0000 From: Abdallah Bouassida Date: Thu, 19 Apr 2018 16:56:24 +0100 Message-Id: <1524153386-3550-2-git-send-email-abdallah.bouassida@lauterbach.com> In-Reply-To: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> References: <1524153386-3550-1-git-send-email-abdallah.bouassida@lauterbach.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v6 1/3] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Cc: qemu-arm@nongnu.org, khaled.jmal@lauterbach.com, Abdallah Bouassida This is a preparation for the coming feature of creating dynamically an XML description for the ARM sysregs. A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML. This bit is enabled automatically when creating CP_ANY wildcard aliases. This bit could be enabled manually for any register we want to remove from the dynamic XML description. Signed-off-by: Abdallah Bouassida Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée --- target/arm/cpu.h | 3 ++- target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 19a0c03..436f675 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1815,10 +1815,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x30ff +#define ARM_CP_FLAG_MASK 0x70ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/helper.c b/target/arm/helper.c index dcb8476..799e322 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5664,7 +5664,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, if (((r->crm == CP_ANY) && crm != 0) || ((r->opc1 == CP_ANY) && opc1 != 0) || ((r->opc2 == CP_ANY) && opc2 != 0)) { - r2->type |= ARM_CP_ALIAS; + r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; } /* Check that raw accesses are either forbidden or handled. Note that -- 2.7.4