[PATCH v4 00/22] Workarounds for Icelake

[PATCH v4 00/22] Workarounds for Icelake

[Oscar Mateo]

List of GT workarounds for Icelake that we have been carrying in internal.
Can we get eyes on these please?

Oscar Mateo (22):
  drm/i915/icl: Introduce initial Icelake Workarounds
  drm/i915/icl: Enable Sampler DFR
  drm/i915/icl: WaGAPZPriorityScheme
  drm/i915/icl: WaL3BankAddressHashing
  drm/i915/icl: WaModifyGamTlbPartitioning
  drm/i915/icl: WaDisableCleanEvicts
  drm/i915/icl: WaCL2SFHalfMaxAlloc
  drm/i915/icl: WaDisCtxReload
  drm/i915/icl: Wa_1405779004
  drm/i915/icl: Wa_1406680159 and Wa_2201832410
  drm/i915/icl: Wa_1604302699
  drm/i915/icl: Wa_1406838659
  drm/i915/icl: WaForwardProgressSoftReset
  drm/i915/icl: WaDisableImprovedTdlClkGating
  drm/i915/icl: WaEnableStateCacheRedirectToCS
  drm/i915/icl: Wa_2006665173
  drm/i915/icl: WaEnableFloatBlendOptimization
  drm/i915/icl: WaSendPushConstantsFromMMIO
  drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
  drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
  drm/i915/icl: WaAllowUmdWriteTRTTRootTable
  drm/i915/icl: WaAllowUMDToModifySamplerMode

 drivers/gpu/drm/i915/i915_drv.h          |   9 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c      |   4 +-
 drivers/gpu/drm/i915/i915_reg.h          |  85 +++++++++++++----
 drivers/gpu/drm/i915/intel_lrc.c         |   2 +
 drivers/gpu/drm/i915/intel_pm.c          |   4 +-
 drivers/gpu/drm/i915/intel_uncore.c      |   7 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 157 +++++++++++++++++++++++++++++++
 7 files changed, 245 insertions(+), 23 deletions(-)

-- 
1.9.1

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[PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
    comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
      drm/i915/icl: add icelake_init_clock_gating()
    from Paulo Zanoni <paulo.r.zanoni@intel.com>
  - Squashed with this patch:
      drm/i915/icl: WaForceEnableNonCoherent
    from Oscar Mateo <oscar.mateo@intel.com>
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
    applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
    to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck

Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++
 drivers/gpu/drm/i915/i915_gem_gtt.c      |  4 +--
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 drivers/gpu/drm/i915/intel_lrc.c         |  2 ++
 drivers/gpu/drm/i915/intel_pm.c          |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c      |  7 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
 7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0286911..1dc157f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
 	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0		0x0
+#define ICL_REVID_A2		0x1
+#define ICL_REVID_B0		0x3
+#define ICL_REVID_B2		0x4
+#define ICL_REVID_C0		0x5
+
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 	else if (IS_GEN9_LP(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0			_MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029901a..2d6572a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 		return -EINVAL;
 
 	switch (INTEL_GEN(engine->i915)) {
+	case 11:
+		return 0;
 	case 10:
 		wa_bb_fn[0] = gen10_init_indirectctx_bb;
 		wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..3b7d804 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d6e20f0..448293e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -139,7 +139,9 @@ enum ack_type {
 	 * in the hope that the original ack will be delivered along with
 	 * the fallback ack.
 	 *
-	 * This workaround is described in HSDES #1604254524
+	 * This workaround is described in HSDES #1604254524 and it's known as:
+	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+	 * although the name is a bit misleading.
 	 */
 
 	pass = 1;
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 11) {
 		int i;
 
-		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+		dev_priv->uncore.funcs.force_wake_get =
+			fw_domains_get_with_fallback;
 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 			       FORCEWAKE_RENDER_GEN9,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..3f00623 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+	/* Wa_1604370585:icl (pre-prod)
+	 * Formerly known as WaPushConstantDereferenceHoldDisable
+	 */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+				  PUSH_CONSTANT_DEREF_DISABLE);
+
+	/* WaForceEnableNonCoherent:icl
+	 * This is not the same workaround as in early Gen9 platforms, where
+	 * lacking this could cause system hangs, but coherency performance
+	 * overhead is high and only a few compute workloads really need it
+	 * (the register is whitelisted in hardware now, so UMDs can opt in
+	 * for coherency if they have a good reason).
+	 */
+	WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
+
+	return 0;
+}
+
 int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 {
 	int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		err = cfl_ctx_workarounds_init(dev_priv);
 	else if (IS_CANNONLAKE(dev_priv))
 		err = cnl_ctx_workarounds_init(dev_priv);
+	else if (IS_ICELAKE(dev_priv))
+		err = icl_ctx_workarounds_init(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 	if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 }
 
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+	/* This is not an Wa. Enable for better image quality */
+	I915_WRITE(_3D_CHICKEN3,
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+	/* WaInPlaceDecompressionHang:icl */
+	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+	/* WaPipelineFlushCoherentLines:icl */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		cfl_gt_workarounds_apply(dev_priv);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_gt_workarounds_apply(dev_priv);
+	else if (IS_ICELAKE(dev_priv))
+		icl_gt_workarounds_apply(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 }
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
 	whitelist_reg(w, GEN8_CS_CHICKEN1);
 }
 
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
 					 struct whitelist *w)
 {
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
 		cfl_whitelist_build(w);
 	else if (IS_CANNONLAKE(i915))
 		cnl_whitelist_build(w);
+	else if (IS_ICELAKE(i915))
+		icl_whitelist_build(w);
 	else
 		MISSING_CASE(INTEL_GEN(i915));
 
-- 
1.9.1

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[PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
 #define GEN8_GARBCNTL                   _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
+#define   DFR_DISABLE			(1 << 9)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3f00623..60a5b1d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+	/* This is not an Wa. Enable to reduce Sampler power */
+	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
 	/* WaInPlaceDecompressionHang:icl */
 	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
 					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-- 
1.9.1

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[PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

[Oscar Mateo]

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622

v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b7e6bc..a6b1f85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8215,8 +8215,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
-#define GEN8_GARBCNTL                   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL				_MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 60a5b1d..ffd27a1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -703,6 +703,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	/* WaPipelineFlushCoherentLines:icl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+	/* Wa_1405543622:icl
+	 * Formerly known as WaGAPZPriorityScheme
+	 */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo]

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
 drivers/gpu/drm/i915/intel_workarounds.c | 20 ++++++++++++++++----
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6b1f85..5637cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,12 @@ enum {
 #define GEN8_GARBCNTL				_MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
+
+#define GEN11_GLBLINVL				_MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 0)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x3f << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ffd27a1..83a53cc 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-	/* Wa_1405543622:icl
-	 * Formerly known as WaGAPZPriorityScheme
+	I915_WRITE(GEN8_GARBCNTL,
+		   /* Wa_1604223664:icl
+		    * Formerly known as WaL3BankAddressHashing
+		    */
+		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+		    GEN11_HASH_CTRL_EXCL_BIT0 |
+		    /* Wa_1405543622:icl
+		     * Formerly known as WaGAPZPriorityScheme
+		     */
+		    GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+	/* Wa_1604223664:icl
+	 * Formerly known as WaL3BankAddressHashing
 	 */
-	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+	I915_WRITE(GEN11_GLBLINVL,
+		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

[Oscar Mateo]

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5637cd7..fe35785 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8228,6 +8228,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
 
+#define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0			(1 << 0)
+#define   GEN11_HASH_CTRL_BIT4			(1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 83a53cc..e8d14a7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -721,6 +721,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_GLBLINVL,
 		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
 		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+	/* WaModifyGamTlbPartitioning:icl */
+	I915_WRITE(GEN11_GACB_PERF_CTRL,
+		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts

[Oscar Mateo]

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe35785..fea85ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7197,8 +7197,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
 #define GEN8_L3SQCREG4				_MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index e8d14a7..efa885c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_GACB_PERF_CTRL,
 		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
 		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+	/* Wa_1405733216:icl
+	 * Formerly known as WaDisableCleanEvicts
+	 */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Oscar Mateo]

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 4 ++++
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fea85ac..43fdd2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8234,6 +8234,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
 #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
 
+#define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index efa885c..a0fbcf7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -732,6 +732,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+	/* Wa_1405766107:icl
+	 * Formerly known as WaCL2SFHalfMaxAlloc
+	 */
+	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 08/22] drm/i915/icl: WaDisCtxReload

[Oscar Mateo]

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43fdd2e..161d04e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8238,6 +8238,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a0fbcf7..dd7f0bd 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
 				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
 				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+	/* Wa_220166154:icl
+	 * Formerly known as WaDisCtxReload
+	 */
+	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 09/22] drm/i915/icl: Wa_1405779004

[Oscar Mateo]

Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 161d04e..9ab5731 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
 #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS		(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index dd7f0bd..50d5507 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
 					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
+	/* Wa_1405779004:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+			    MSCUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 50d5507..2c792d7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
 			    MSCUNIT_CLKGATE_DIS));
+
+	/* Wa_1406680159:icl */
+	/* Wa_2201832410:icl (pre-prod, only until C0) */
+	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+		    GWUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 11/22] drm/i915/icl: Wa_1604302699

[Oscar Mateo]

Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ab5731..b462938 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,7 +7192,9 @@ enum {
 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
-#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+#define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
+#define  GEN7_WA_L3_CHICKEN_MODE		0x20000000
+#define  GEN11_I2M_WRITE_DISABLE		(1 << 28)
 
 #define GEN7_L3SQCREG4				_MMIO(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2c792d7..2364749 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -757,6 +757,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
 		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
 		    GWUNIT_CLKGATE_DIS));
+
+	/* Wa_1604302699:icl */
+	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+		    GEN11_I2M_WRITE_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 12/22] drm/i915/icl: Wa_1406838659

[Oscar Mateo]

Disable CGPSF unit clock gating to prevent an issue.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 13 ++++++++-----
 drivers/gpu/drm/i915/intel_workarounds.c |  6 ++++++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b462938..fc09b83 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3838,15 +3838,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
-#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
-#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
+#define   SARBUNIT_CLKGATE_DIS		(1 << 5)
+#define   RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define   MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS		(1 << 16)
+#define   GWUNIT_CLKGATE_DIS		(1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define   VFUNIT_CLKGATE_DIS		(1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS		(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2364749..a9868e9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -762,6 +762,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
 		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
 		    GEN11_I2M_WRITE_DISABLE));
+
+	/* Wa_1406838659:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+			    CGPSF_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

[Oscar Mateo]

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc09b83..cfb9b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9711,6 +9711,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
 
+#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
+#define   PMFLUSHDONE_LNEBLK		(1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a9868e9..beb98c6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -768,6 +768,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
 			    CGPSF_CLKGATE_DIS));
+
+	/* WaForwardProgressSoftReset:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(GEN10_SCRATCH_LNCF2,
+			   (I915_READ(GEN10_SCRATCH_LNCF2) |
+			    PMFLUSHDONE_LNICRSDROP |
+			    PMFLUSH_GAPL3UNBLOCK |
+			    PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating

[Oscar Mateo]

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only
v4:
  - Add spaces around '<<' (and fix the surrounding code as well)
  - Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfb9b0d..fca143b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8284,8 +8284,9 @@ enum {
 
 #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
-#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
-#define   PUSH_CONSTANT_DEREF_DISABLE	(1<<8)
+#define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
+#define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
 
 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index beb98c6..26a77da 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	 */
 	WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
 
+	/* Wa_2006611047:icl (pre-prod)
+	 * Formerly known as WaDisableImprovedTdlClkGating
+	 */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

[Oscar Mateo]

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fca143b..452e24d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7173,6 +7173,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
 
 #define GEN7_L3SQCREG1				_MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 26a77da..7ad9454 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -466,6 +466,10 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+	/* WaEnableStateCacheRedirectToCS:icl */
+	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 16/22] drm/i915/icl: Wa_2006665173

[Oscar Mateo]

Disable blend embellishment in RCC.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 18 +++++++++++-------
 drivers/gpu/drm/i915/intel_workarounds.c |  5 +++++
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 452e24d..71696dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7157,13 +7157,17 @@ enum {
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
-#define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION	(1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
+  #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1 << 10) | (1 << 26))
+  #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
+
+#define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
+  #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
+  #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
+  #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
+  #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
 
 #define HIZ_CHICKEN					_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7ad9454..6ca0958 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,11 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
 			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
 
+	/* Wa_2006665173:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization

[Oscar Mateo]

Enables blend optimization for floating point RTs

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 71696dc..127d2a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
 
+#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
+
 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT			16
 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 6ca0958..5abd531 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,6 +475,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
+	/* WaEnableFloatBlendOptimization:icl */
+	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO

[Oscar Mateo]

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the WA whitelist reg refactoring (Michel)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 5abd531..be49c12 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -899,6 +899,8 @@ static void cnl_whitelist_build(struct whitelist *w)
 
 static void icl_whitelist_build(struct whitelist *w)
 {
+	/* WaSendPushConstantsFromMMIO:icl */
+	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

[Oscar Mateo]

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index be49c12..ba2ba63 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -901,6 +901,9 @@ static void icl_whitelist_build(struct whitelist *w)
 {
 	/* WaSendPushConstantsFromMMIO:icl */
 	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+	/* WaAllowUMDToModifyHalfSliceChicken2:icl */
+	whitelist_reg(w, HALF_SLICE_CHICKEN2);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

[Oscar Mateo]

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ba2ba63..120e703 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -904,6 +904,9 @@ static void icl_whitelist_build(struct whitelist *w)
 
 	/* WaAllowUMDToModifyHalfSliceChicken2:icl */
 	whitelist_reg(w, HALF_SLICE_CHICKEN2);
+
+	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
+	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

[Oscar Mateo]

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 127d2a3..d008a70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8255,6 +8255,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 120e703..b32caf6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -907,6 +907,10 @@ static void icl_whitelist_build(struct whitelist *w)
 
 	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
 	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+	/* WaAllowUmdWriteTRTTRootTable:icl */
+	whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
+	whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

[Oscar Mateo]

Required for Bindless samplers.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: Rebased on top of the WA refactoring (Michel)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d008a70..3394cc0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8258,6 +8258,8 @@ enum {
 #define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
 
+#define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b32caf6..5965dae 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -911,6 +911,9 @@ static void icl_whitelist_build(struct whitelist *w)
 	/* WaAllowUmdWriteTRTTRootTable:icl */
 	whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
 	whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
+
+	/* WaAllowUMDToModifySamplerMode:icl */
+	whitelist_reg(w, GEN10_SAMPLER_MODE);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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Re: [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
> Disable GWL clock gating to prevent two different issues that
> might cause hangs.
> 
> Please notice that one of the issues is pre-production only.
> 
> v2: Rebased on top of the WA refactoring
> 
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 50d5507..2c792d7 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>  			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>  			    MSCUNIT_CLKGATE_DIS));
> +
> +	/* Wa_1406680159:icl */
> +	/* Wa_2201832410:icl (pre-prod, only until C0) */

what about adding the REVID checks?

but, well, why one is pre-prod and other is forever?

> +	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
> +		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
> +		    GWUNIT_CLKGATE_DIS));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
> 
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Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
> 
> v2: Wrong operation to clear the bit (Praveen)
> v3: Rebased on top of the WA refactoring
> 
> Cc: Praveen Paneri <praveen.paneri@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f2ee225..4b7e6bc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8218,6 +8218,9 @@ enum {
>  #define GEN8_GARBCNTL                   _MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>  
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> +#define   DFR_DISABLE			(1 << 9)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 3f00623..60a5b1d 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(_3D_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>  
> +	/* This is not an Wa. Enable to reduce Sampler power */

First of all it is strange that a feature is under a chicken bit,
but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
init clock gating function, or a new specific function called when it makes sense?

> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> +
>  	/* WaInPlaceDecompressionHang:icl */
>  	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>  					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
> On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
>> Disable GWL clock gating to prevent two different issues that
>> might cause hangs.
>>
>> Please notice that one of the issues is pre-production only.
>>
>> v2: Rebased on top of the WA refactoring
>>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index 50d5507..2c792d7 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>>   			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>>   			    MSCUNIT_CLKGATE_DIS));
>> +
>> +	/* Wa_1406680159:icl */
>> +	/* Wa_2201832410:icl (pre-prod, only until C0) */
> what about adding the REVID checks?
>
> but, well, why one is pre-prod and other is forever?

That's the thing: this is the same workaround for two different HW 
problems. One is fixed post-C0, but the other is not, so I cannot add 
REVID checks :(

>
>> +	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
>> +		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
>> +		    GWUNIT_CLKGATE_DIS));
>>   }
>>   
>>   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
>> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
>> power by dynamically changing its clock frequency in low-throughput
>> conditions. This patches enables it by default on Gen11.
>>
>> v2: Wrong operation to clear the bit (Praveen)
>> v3: Rebased on top of the WA refactoring
>>
>> Cc: Praveen Paneri <praveen.paneri@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>>   drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>>   2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index f2ee225..4b7e6bc 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8218,6 +8218,9 @@ enum {
>>   #define GEN8_GARBCNTL                   _MMIO(0xB004)
>>   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>>   
>> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>> +#define   DFR_DISABLE			(1 << 9)
>> +
>>   /* IVYBRIDGE DPF */
>>   #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>>   #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index 3f00623..60a5b1d 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   	I915_WRITE(_3D_CHICKEN3,
>>   		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>>   
>> +	/* This is not an Wa. Enable to reduce Sampler power */
> First of all it is strange that a feature is under a chicken bit,

There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE

> but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
> init clock gating function, or a new specific function called when it makes sense?

I'm open to suggestions

>> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
>> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
>> +
>>   	/* WaInPlaceDecompressionHang:icl */
>>   	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>>   					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
> 
> 
> On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
> > > Disable GWL clock gating to prevent two different issues that
> > > might cause hangs.
> > > 
> > > Please notice that one of the issues is pre-production only.
> > > 
> > > v2: Rebased on top of the WA refactoring
> > > 
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> > >   1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> > > index 50d5507..2c792d7 100644
> > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > @@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> > >   		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> > >   			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> > >   			    MSCUNIT_CLKGATE_DIS));
> > > +
> > > +	/* Wa_1406680159:icl */
> > > +	/* Wa_2201832410:icl (pre-prod, only until C0) */
> > what about adding the REVID checks?
> > 
> > but, well, why one is pre-prod and other is forever?
> 
> That's the thing: this is the same workaround for two different HW problems.
> One is fixed post-C0, but the other is not, so I cannot add REVID checks :(

Oh of course... Makes sense. Thanks ;)

> 
> > 
> > > +	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
> > > +		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
> > > +		    GWUNIT_CLKGATE_DIS));
> > >   }
> > >   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
abf7b0421b03 drm/i915/icl: Introduce initial Icelake Workarounds
-:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#48: FILE: drivers/gpu/drm/i915/i915_drv.h:2471:
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 155 lines checked
5ee197f360ed drm/i915/icl: Enable Sampler DFR
64f72e593847 drm/i915/icl: WaGAPZPriorityScheme
363ae679b17f drm/i915/icl: WaL3BankAddressHashing
f4c1b4bb9090 drm/i915/icl: WaModifyGamTlbPartitioning
bd0addeea3e4 drm/i915/icl: WaDisableCleanEvicts
614afb61f95c drm/i915/icl: WaCL2SFHalfMaxAlloc
816ee27c52c2 drm/i915/icl: WaDisCtxReload
ed2ec7a07267 drm/i915/icl: Wa_1405779004
4adc5c7395a1 drm/i915/icl: Wa_1406680159 and Wa_2201832410
be63d1d1ad53 drm/i915/icl: Wa_1604302699
9702c4288bac drm/i915/icl: Wa_1406838659
c4772140f55f drm/i915/icl: WaForwardProgressSoftReset
7ddbeb426ced drm/i915/icl: WaDisableImprovedTdlClkGating
d397ada30a53 drm/i915/icl: WaEnableStateCacheRedirectToCS
8e678b2a3d72 drm/i915/icl: Wa_2006665173
6416305b9e4a drm/i915/icl: WaEnableFloatBlendOptimization
1afd609b2026 drm/i915/icl: WaSendPushConstantsFromMMIO
cfbc51ef5c4a drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
a506e91880c4 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
3c8350e7a85b drm/i915/icl: WaAllowUmdWriteTRTTRootTable
b3e83155f633 drm/i915/icl: WaAllowUMDToModifySamplerMode

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✗ Fi.CI.SPARSE: warning for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Introduce initial Icelake Workarounds
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3656:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3665:16: warning: expression using sizeof(void)

Commit: drm/i915/icl: Enable Sampler DFR
Okay!

Commit: drm/i915/icl: WaGAPZPriorityScheme
Okay!

Commit: drm/i915/icl: WaL3BankAddressHashing
Okay!

Commit: drm/i915/icl: WaModifyGamTlbPartitioning
Okay!

Commit: drm/i915/icl: WaDisableCleanEvicts
Okay!

Commit: drm/i915/icl: WaCL2SFHalfMaxAlloc
Okay!

Commit: drm/i915/icl: WaDisCtxReload
Okay!

Commit: drm/i915/icl: Wa_1405779004
Okay!

Commit: drm/i915/icl: Wa_1406680159 and Wa_2201832410
Okay!

Commit: drm/i915/icl: Wa_1604302699
Okay!

Commit: drm/i915/icl: Wa_1406838659
Okay!

Commit: drm/i915/icl: WaForwardProgressSoftReset
Okay!

Commit: drm/i915/icl: WaDisableImprovedTdlClkGating
Okay!

Commit: drm/i915/icl: WaEnableStateCacheRedirectToCS
Okay!

Commit: drm/i915/icl: Wa_2006665173
Okay!

Commit: drm/i915/icl: WaEnableFloatBlendOptimization
Okay!

Commit: drm/i915/icl: WaSendPushConstantsFromMMIO
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
Okay!

Commit: drm/i915/icl: WaAllowUmdWriteTRTTRootTable
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifySamplerMode
Okay!

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✓ Fi.CI.BAT: success for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072 -> Patchwork_8768 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8768 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt@drv_module_reload@basic-no-display:
      fi-cnl-psr:         NOTRUN -> DMESG-WARN (fdo#105395) +2

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       PASS -> DMESG-WARN (fdo#105128)

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 33) ==

  Additional (2): fi-kbl-7560u fi-cnl-psr 
  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4072 -> Patchwork_8768

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8768: b3e83155f6333c0a9db115f82db0290028c52055 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

b3e83155f633 drm/i915/icl: WaAllowUMDToModifySamplerMode
3c8350e7a85b drm/i915/icl: WaAllowUmdWriteTRTTRootTable
a506e91880c4 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
cfbc51ef5c4a drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
1afd609b2026 drm/i915/icl: WaSendPushConstantsFromMMIO
6416305b9e4a drm/i915/icl: WaEnableFloatBlendOptimization
8e678b2a3d72 drm/i915/icl: Wa_2006665173
d397ada30a53 drm/i915/icl: WaEnableStateCacheRedirectToCS
7ddbeb426ced drm/i915/icl: WaDisableImprovedTdlClkGating
c4772140f55f drm/i915/icl: WaForwardProgressSoftReset
9702c4288bac drm/i915/icl: Wa_1406838659
be63d1d1ad53 drm/i915/icl: Wa_1604302699
4adc5c7395a1 drm/i915/icl: Wa_1406680159 and Wa_2201832410
ed2ec7a07267 drm/i915/icl: Wa_1405779004
816ee27c52c2 drm/i915/icl: WaDisCtxReload
614afb61f95c drm/i915/icl: WaCL2SFHalfMaxAlloc
bd0addeea3e4 drm/i915/icl: WaDisableCleanEvicts
f4c1b4bb9090 drm/i915/icl: WaModifyGamTlbPartitioning
363ae679b17f drm/i915/icl: WaL3BankAddressHashing
64f72e593847 drm/i915/icl: WaGAPZPriorityScheme
5ee197f360ed drm/i915/icl: Enable Sampler DFR
abf7b0421b03 drm/i915/icl: Introduce initial Icelake Workarounds

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8768/issues.html
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Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
> 
> 
> On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> > > Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> > > power by dynamically changing its clock frequency in low-throughput
> > > conditions. This patches enables it by default on Gen11.
> > > 
> > > v2: Wrong operation to clear the bit (Praveen)
> > > v3: Rebased on top of the WA refactoring
> > > 
> > > Cc: Praveen Paneri <praveen.paneri@intel.com>
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > > Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/i915_reg.h          | 3 +++
> > >   drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> > >   2 files changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index f2ee225..4b7e6bc 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8218,6 +8218,9 @@ enum {
> > >   #define GEN8_GARBCNTL                   _MMIO(0xB004)
> > >   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> > > +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> > > +#define   DFR_DISABLE			(1 << 9)
> > > +
> > >   /* IVYBRIDGE DPF */
> > >   #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> > >   #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> > > index 3f00623..60a5b1d 100644
> > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> > >   	I915_WRITE(_3D_CHICKEN3,
> > >   		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > > +	/* This is not an Wa. Enable to reduce Sampler power */
> > First of all it is strange that a feature is under a chicken bit,
> 
> There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE

Oh, true!

Actually that never got same question from me because that
function is called init clock gating, although this function nowadays
is basically workarounds related to clock gatings :/)

> 
> > but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
> > init clock gating function, or a new specific function called when it makes sense?
> 
> I'm open to suggestions

moving to clock gating is an option?
or needs to be called from context?

> 
> > > +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> > > +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> > > +
> > >   	/* WaInPlaceDecompressionHang:icl */
> > >   	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> > >   					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
> On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
>>
>> On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
>>> On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
>>>> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
>>>> power by dynamically changing its clock frequency in low-throughput
>>>> conditions. This patches enables it by default on Gen11.
>>>>
>>>> v2: Wrong operation to clear the bit (Praveen)
>>>> v3: Rebased on top of the WA refactoring
>>>>
>>>> Cc: Praveen Paneri <praveen.paneri@intel.com>
>>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>>>> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>>>>    drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>>>>    2 files changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index f2ee225..4b7e6bc 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -8218,6 +8218,9 @@ enum {
>>>>    #define GEN8_GARBCNTL                   _MMIO(0xB004)
>>>>    #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>>>> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>>>> +#define   DFR_DISABLE			(1 << 9)
>>>> +
>>>>    /* IVYBRIDGE DPF */
>>>>    #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>>>>    #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
>>>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>>>> index 3f00623..60a5b1d 100644
>>>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>>>> @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>>>    	I915_WRITE(_3D_CHICKEN3,
>>>>    		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>>>> +	/* This is not an Wa. Enable to reduce Sampler power */
>>> First of all it is strange that a feature is under a chicken bit,
>> There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE
> Oh, true!
>
> Actually that never got same question from me because that
> function is called init clock gating, although this function nowadays
> is basically workarounds related to clock gatings :/)
>
>>> but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
>>> init clock gating function, or a new specific function called when it makes sense?
>> I'm open to suggestions
> moving to clock gating is an option?
> or needs to be called from context?

No, moving it to init_clock_gating is definitely an option. It is not 
truly related to clock gating, but at least it is related to Power 
Management... (the _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE thing is more 
difficult to swallow...)

>>>> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
>>>> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
>>>> +
>>>>    	/* WaInPlaceDecompressionHang:icl */
>>>>    	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>>>>    					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
>>>> -- 
>>>> 1.9.1
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 02:29:27PM -0700, Oscar Mateo wrote:
> 
> 
> On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
> > > 
> > > On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
> > > > On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
> > > > > Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> > > > > power by dynamically changing its clock frequency in low-throughput
> > > > > conditions. This patches enables it by default on Gen11.
> > > > > 
> > > > > v2: Wrong operation to clear the bit (Praveen)
> > > > > v3: Rebased on top of the WA refactoring
> > > > > 
> > > > > Cc: Praveen Paneri <praveen.paneri@intel.com>
> > > > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > > > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > > > > Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > > > ---
> > > > >    drivers/gpu/drm/i915/i915_reg.h          | 3 +++
> > > > >    drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> > > > >    2 files changed, 7 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index f2ee225..4b7e6bc 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -8218,6 +8218,9 @@ enum {
> > > > >    #define GEN8_GARBCNTL                   _MMIO(0xB004)
> > > > >    #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> > > > > +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> > > > > +#define   DFR_DISABLE			(1 << 9)
> > > > > +
> > > > >    /* IVYBRIDGE DPF */
> > > > >    #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> > > > >    #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> > > > > index 3f00623..60a5b1d 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > > > @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> > > > >    	I915_WRITE(_3D_CHICKEN3,
> > > > >    		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > > > > +	/* This is not an Wa. Enable to reduce Sampler power */
> > > > First of all it is strange that a feature is under a chicken bit,
> > > There is a precedent: _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE
> > Oh, true!
> > 
> > Actually that never got same question from me because that
> > function is called init clock gating, although this function nowadays
> > is basically workarounds related to clock gatings :/)
> > 
> > > > but if it is not an wa, but a PM feature, shouldn't we add it to some sort of
> > > > init clock gating function, or a new specific function called when it makes sense?
> > > I'm open to suggestions
> > moving to clock gating is an option?
> > or needs to be called from context?
> 
> No, moving it to init_clock_gating is definitely an option. It is not truly
> related to clock gating, but at least it is related to Power Management...
> (the _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE thing is more difficult to
> swallow...)

I agree hehe... my bad... :$

> 
> > > > > +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> > > > > +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> > > > > +
> > > > >    	/* WaInPlaceDecompressionHang:icl */
> > > > >    	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> > > > >    					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> > > > > -- 
> > > > > 1.9.1
> > > > > 
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✓ Fi.CI.IGT: success for Workarounds for Icelake

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake
URL   : https://patchwork.freedesktop.org/series/42055/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4072_full -> Patchwork_8768_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8768_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8768_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8768_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd1:
      shard-kbl:          SKIP -> PASS +1

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          PASS -> SKIP

    igt@kms_busy@extended-modeset-hang-oldfb-render-a:
      shard-glk:          PASS -> SKIP +76

    igt@kms_vblank@pipe-b-wait-forked-busy-hang:
      shard-glk:          SKIP -> PASS +104

    
== Known issues ==

  Here are the changes found in Patchwork_8768_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_schedule@wide-bsd2:
      shard-kbl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558)

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          PASS -> INCOMPLETE (fdo#106023, fdo#103665)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-hsw:          PASS -> FAIL (fdo#102887)

    igt@kms_flip@flip-vs-expired-vblank:
      shard-hsw:          PASS -> FAIL (fdo#105707)

    
    ==== Possible fixes ====

    igt@kms_flip@dpms-vs-vblank-race-interruptible:
      shard-glk:          FAIL (fdo#103060) -> PASS

    igt@kms_flip@plain-flip-fb-recreate:
      shard-hsw:          FAIL (fdo#100368) -> PASS
      shard-glk:          FAIL (fdo#100368) -> PASS +1

    igt@kms_sysfs_edid_timing:
      shard-apl:          WARN (fdo#100047) -> PASS

    igt@perf@blocking:
      shard-hsw:          FAIL (fdo#102252) -> PASS

    
  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023


== Participating hosts (6 -> 5) ==

  Missing    (1): shard-glkb 


== Build changes ==

    * Linux: CI_DRM_4072 -> Patchwork_8768

  CI_DRM_4072: b35e59e5c6a9cae11d5183d2bf9c5c99ceedbc7c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4442: 8168bb65d5e64d4df4e5d847d448bab2d2825d73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8768: b3e83155f6333c0a9db115f82db0290028c52055 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4442: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8768/shards.html
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Re: [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

On 04/20/2018 01:53 PM, Rodrigo Vivi wrote:
> On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
>>
>> On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
>>> On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
>>>> Disable GWL clock gating to prevent two different issues that
>>>> might cause hangs.
>>>>
>>>> Please notice that one of the issues is pre-production only.
>>>>
>>>> v2: Rebased on top of the WA refactoring
>>>>
>>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>>>>    1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>>>> index 50d5507..2c792d7 100644
>>>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>>>> @@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>>>    		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>>>>    			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>>>>    			    MSCUNIT_CLKGATE_DIS));
>>>> +
>>>> +	/* Wa_1406680159:icl */
>>>> +	/* Wa_2201832410:icl (pre-prod, only until C0) */
>>> what about adding the REVID checks?
>>>
>>> but, well, why one is pre-prod and other is forever?
>> That's the thing: this is the same workaround for two different HW problems.
>> One is fixed post-C0, but the other is not, so I cannot add REVID checks :(
> Oh of course... Makes sense. Thanks ;)

Good news: Wa_2201832410 has been officially merged with Wa_1406680159, 
so I can remove the confusing comment \o/

>>>> +	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
>>>> +		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
>>>> +		    GWUNIT_CLKGATE_DIS));
>>>>    }
>>>>    void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>>> -- 
>>>> 1.9.1
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Inherit workarounds from previous platforms that are still valid for
> Icelake.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
>   - Since it has been fixed already in upstream, removed the TODO
>     comment about WA_SET_BIT for WaInPlaceDecompressionHang.
>   - Squashed with this patch:
>       drm/i915/icl: add icelake_init_clock_gating()
>     from Paulo Zanoni <paulo.r.zanoni@intel.com>
>   - Squashed with this patch:
>       drm/i915/icl: WaForceEnableNonCoherent
>     from Oscar Mateo <oscar.mateo@intel.com>
>   - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
>     applies to B0 as well.
>   - WaPipeControlBefore3DStateSamplePattern WABB was being applied
>     to ICL incorrectly.
> v4:
>   - Wrap the commit message
>   - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++
>  drivers/gpu/drm/i915/i915_gem_gtt.c      |  4 +--
>  drivers/gpu/drm/i915/i915_reg.h          |  1 +
>  drivers/gpu/drm/i915/intel_lrc.c         |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c          |  4 ++-
>  drivers/gpu/drm/i915/intel_uncore.c      |  7 +++--
>  drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
>  7 files changed, 68 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0286911..1dc157f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_CNL_REVID(p, since, until) \
>  	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>  
> +#define ICL_REVID_A0		0x0
> +#define ICL_REVID_A2		0x1

Just noted that for some reason bspec puts A0 and A2 under
same revid. Bspec err?

> +#define ICL_REVID_B0		0x3
> +#define ICL_REVID_B2		0x4
> +#define ICL_REVID_C0		0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> +	(IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
>  /*
>   * The genX designation typically refers to the render engine, so render
>   * capability related checks should use IS_GEN, while display and other checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 21d72f6..221b873 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>  	 * called on driver load and after a GPU reset, so you can place
>  	 * workarounds here even if they get overwritten by GPU reset.
>  	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>  	if (IS_BROADWELL(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> -	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> +	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>  	else if (IS_GEN9_LP(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..f2ee225 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7203,6 +7203,7 @@ enum {
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				_MMIO(0x7300)
>  #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> +#define ICL_HDC_CHICKEN0			_MMIO(0xE5F4)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 029901a..2d6572a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  		return -EINVAL;
>  
>  	switch (INTEL_GEN(engine->i915)) {
> +	case 11:
> +		return 0;
>  	case 10:
>  		wa_bb_fn[0] = gen10_init_indirectctx_bb;
>  		wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4baab85..3b7d804 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>   */
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_CANNONLAKE(dev_priv))
> +	if (IS_ICELAKE(dev_priv))
> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>  	else if (IS_COFFEELAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d6e20f0..448293e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -139,7 +139,9 @@ enum ack_type {
>  	 * in the hope that the original ack will be delivered along with
>  	 * the fallback ack.
>  	 *
> -	 * This workaround is described in HSDES #1604254524
> +	 * This workaround is described in HSDES #1604254524 and it's known as:
> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> +	 * although the name is a bit misleading.

Just for the record:

When I implemented this there was recommendation to do both, delaying
for ack and then this method of using a reserver bit. My interpretation
was that the delay was used as a first weapon to combat the issue. And
then later, reserve bit method appeared.

I did not use WaRsForcewakeAddDelayForAck as I thought that this will be
named differently. And also I think this method is a superset,
making delaying irrelevant. As we fallback to reserve is we miss ack
so no need to delay before polling. And adding delay to hotpath should
be the last resort anyways.

I think this is the evolution of WaRsForcewakeAddDelayForAck
(v2) and there is no better name, we should keep it.

>  	 */
>  
>  	pass = 1;
> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) >= 11) {
>  		int i;
>  
> -		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> +		dev_priv->uncore.funcs.force_wake_get =
> +			fw_domains_get_with_fallback;
>  		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>  		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>  			       FORCEWAKE_RENDER_GEN9,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..3f00623 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> +{
> +	/* Wa_1604370585:icl (pre-prod)
> +	 * Formerly known as WaPushConstantDereferenceHoldDisable
> +	 */
> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> +		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> +				  PUSH_CONSTANT_DEREF_DISABLE);

Inherited from CNL and had to check if we have that on cnl. We do.

> +
> +	/* WaForceEnableNonCoherent:icl
> +	 * This is not the same workaround as in early Gen9 platforms, where
> +	 * lacking this could cause system hangs, but coherency performance
> +	 * overhead is high and only a few compute workloads really need it
> +	 * (the register is whitelisted in hardware now, so UMDs can opt in
> +	 * for coherency if they have a good reason).
> +	 */
> +	WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);

Right, but the register name should be ICL_HDC_MODE.

> +
> +	return 0;
> +}
> +
>  int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>  {
>  	int err = 0;
> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>  		err = cfl_ctx_workarounds_init(dev_priv);
>  	else if (IS_CANNONLAKE(dev_priv))
>  		err = cnl_ctx_workarounds_init(dev_priv);
> +	else if (IS_ICELAKE(dev_priv))
> +		err = icl_ctx_workarounds_init(dev_priv);
>  	else
>  		MISSING_CASE(INTEL_GEN(dev_priv));
>  	if (err)
> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
>  }
>  
> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> +{
> +	/* This is not an Wa. Enable for better image quality */
> +	I915_WRITE(_3D_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> +
> +	/* WaInPlaceDecompressionHang:icl */
> +	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> +					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> +
> +	/* WaPipelineFlushCoherentLines:icl */
> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));

Didn't find a HSDES entry for this. The workaround name and the reg/bit
matches tho.

But the real question in here is that do we need to set this through
indirect bb like we do with gen[8,9].

And just to note that cnl is missing this too. But that can be done
as a followup when we first figure out that should we use the indirect
bb for all >= gen8.

-Mika

> +}
> +
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  {
>  	if (INTEL_GEN(dev_priv) < 8)
> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		cfl_gt_workarounds_apply(dev_priv);
>  	else if (IS_CANNONLAKE(dev_priv))
>  		cnl_gt_workarounds_apply(dev_priv);
> +	else if (IS_ICELAKE(dev_priv))
> +		icl_gt_workarounds_apply(dev_priv);
>  	else
>  		MISSING_CASE(INTEL_GEN(dev_priv));
>  }
> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
>  	whitelist_reg(w, GEN8_CS_CHICKEN1);
>  }
>  
> +static void icl_whitelist_build(struct whitelist *w)
> +{
> +}
> +
>  static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>  					 struct whitelist *w)
>  {
> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>  		cfl_whitelist_build(w);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_whitelist_build(w);
> +	else if (IS_ICELAKE(i915))
> +		icl_whitelist_build(w);
>  	else
>  		MISSING_CASE(INTEL_GEN(i915));
>  
> -- 
> 1.9.1
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Re: [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> The default GAPZ arbitrer priority value at power-on has been found
> to be incorrect.
>
> v2: Now renamed to Wa_1405543622
>
> v3: Rebased on top of the WA refactoring
>

I have suggested that when implementing workarounds,
authors, for example, add

References: HSDES#1405542622, HSDES#1207131207

as a first tagline to ease up the review.
I do that again :) No need to resend,

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
>  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>  2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b7e6bc..a6b1f85 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8215,8 +8215,9 @@ enum {
>  #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
>  #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
>  
> -#define GEN8_GARBCNTL                   _MMIO(0xB004)
> -#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> +#define GEN8_GARBCNTL				_MMIO(0xB004)
> +#define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
> +#define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
>  
>  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>  #define   DFR_DISABLE			(1 << 9)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 60a5b1d..ffd27a1 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -703,6 +703,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	/* WaPipelineFlushCoherentLines:icl */
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> +
> +	/* Wa_1405543622:icl
> +	 * Formerly known as WaGAPZPriorityScheme
> +	 */
> +	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> +				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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Re: [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

[Oscar Mateo]

On 04/26/2018 08:27 AM, Mika Kuoppala wrote:
> Oscar Mateo <oscar.mateo@intel.com> writes:
>
>> The default GAPZ arbitrer priority value at power-on has been found
>> to be incorrect.
>>
>> v2: Now renamed to Wa_1405543622
>>
>> v3: Rebased on top of the WA refactoring
>>
> I have suggested that when implementing workarounds,
> authors, for example, add
>
> References: HSDES#1405542622, HSDES#1207131207

The thing is, nowadays, the name of the WA itself *is* the HSDES number 
(e.g. this is Wa_1405543622 because it is documented in 
HSDES#1405543622). At least for hardware workarounds. But I have no 
problem adding the "References" tag as well, as long as we have consensus.

> as a first tagline to ease up the review.
> I do that again :) No need to resend,
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

Thanks!

>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
>>   drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>>   2 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 4b7e6bc..a6b1f85 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8215,8 +8215,9 @@ enum {
>>   #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
>>   #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
>>   
>> -#define GEN8_GARBCNTL                   _MMIO(0xB004)
>> -#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>> +#define GEN8_GARBCNTL				_MMIO(0xB004)
>> +#define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
>> +#define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
>>   
>>   #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>>   #define   DFR_DISABLE			(1 << 9)
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index 60a5b1d..ffd27a1 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -703,6 +703,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   	/* WaPipelineFlushCoherentLines:icl */
>>   	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>>   				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>> +
>> +	/* Wa_1405543622:icl
>> +	 * Formerly known as WaGAPZPriorityScheme
>> +	 */
>> +	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
>> +				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
>>   }
>>   
>>   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> -- 
>> 1.9.1

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Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

On 04/26/2018 08:01 AM, Mika Kuoppala wrote:
> Oscar Mateo <oscar.mateo@intel.com> writes:
>
>> Inherit workarounds from previous platforms that are still valid for
>> Icelake.
>>
>> v2: GEN7_ROW_CHICKEN2 is masked
>> v3:
>>    - Since it has been fixed already in upstream, removed the TODO
>>      comment about WA_SET_BIT for WaInPlaceDecompressionHang.
>>    - Squashed with this patch:
>>        drm/i915/icl: add icelake_init_clock_gating()
>>      from Paulo Zanoni <paulo.r.zanoni@intel.com>
>>    - Squashed with this patch:
>>        drm/i915/icl: WaForceEnableNonCoherent
>>      from Oscar Mateo <oscar.mateo@intel.com>
>>    - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
>>      applies to B0 as well.
>>    - WaPipeControlBefore3DStateSamplePattern WABB was being applied
>>      to ICL incorrectly.
>> v4:
>>    - Wrap the commit message
>>    - s/dev_priv/p to please checkpatch
>> v5: Rebased on top of the WA refactoring
>> v6: Rebased on top of further whitelist registers refactoring (Michel)
>> v7: Added WaRsForcewakeAddDelayForAck
>>
>> Cc: Tomasz Lis <tomasz.lis@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++
>>   drivers/gpu/drm/i915/i915_gem_gtt.c      |  4 +--
>>   drivers/gpu/drm/i915/i915_reg.h          |  1 +
>>   drivers/gpu/drm/i915/intel_lrc.c         |  2 ++
>>   drivers/gpu/drm/i915/intel_pm.c          |  4 ++-
>>   drivers/gpu/drm/i915/intel_uncore.c      |  7 +++--
>>   drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
>>   7 files changed, 68 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 0286911..1dc157f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
>>   #define IS_CNL_REVID(p, since, until) \
>>   	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>>   
>> +#define ICL_REVID_A0		0x0
>> +#define ICL_REVID_A2		0x1
> Just noted that for some reason bspec puts A0 and A2 under
> same revid. Bspec err?

That's what I hope. I have opened a bug against the BSpec to be 100% sure.

>> +#define ICL_REVID_B0		0x3
>> +#define ICL_REVID_B2		0x4
>> +#define ICL_REVID_C0		0x5
>> +
>> +#define IS_ICL_REVID(p, since, until) \
>> +	(IS_ICELAKE(p) && IS_REVID(p, since, until))
>> +
>>   /*
>>    * The genX designation typically refers to the render engine, so render
>>    * capability related checks should use IS_GEN, while display and other checks
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 21d72f6..221b873 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>>   	 * called on driver load and after a GPU reset, so you can place
>>   	 * workarounds here even if they get overwritten by GPU reset.
>>   	 */
>> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
>> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>>   	if (IS_BROADWELL(dev_priv))
>>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>>   	else if (IS_CHERRYVIEW(dev_priv))
>>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
>> -	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
>> +	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
>>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>>   	else if (IS_GEN9_LP(dev_priv))
>>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fb10602..f2ee225 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7203,6 +7203,7 @@ enum {
>>   /* GEN8 chicken */
>>   #define HDC_CHICKEN0				_MMIO(0x7300)
>>   #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
>> +#define ICL_HDC_CHICKEN0			_MMIO(0xE5F4)
>>   #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
>>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 029901a..2d6572a 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1636,6 +1636,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>>   		return -EINVAL;
>>   
>>   	switch (INTEL_GEN(engine->i915)) {
>> +	case 11:
>> +		return 0;
>>   	case 10:
>>   		wa_bb_fn[0] = gen10_init_indirectctx_bb;
>>   		wa_bb_fn[1] = NULL;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4baab85..3b7d804 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -9123,7 +9123,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>>    */
>>   void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>>   {
>> -	if (IS_CANNONLAKE(dev_priv))
>> +	if (IS_ICELAKE(dev_priv))
>> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
>> +	else if (IS_CANNONLAKE(dev_priv))
>>   		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>>   	else if (IS_COFFEELAKE(dev_priv))
>>   		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index d6e20f0..448293e 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -139,7 +139,9 @@ enum ack_type {
>>   	 * in the hope that the original ack will be delivered along with
>>   	 * the fallback ack.
>>   	 *
>> -	 * This workaround is described in HSDES #1604254524
>> +	 * This workaround is described in HSDES #1604254524 and it's known as:
>> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
>> +	 * although the name is a bit misleading.
> Just for the record:
>
> When I implemented this there was recommendation to do both, delaying
> for ack and then this method of using a reserver bit. My interpretation
> was that the delay was used as a first weapon to combat the issue. And
> then later, reserve bit method appeared.
>
> I did not use WaRsForcewakeAddDelayForAck as I thought that this will be
> named differently. And also I think this method is a superset,
> making delaying irrelevant. As we fallback to reserve is we miss ack
> so no need to delay before polling. And adding delay to hotpath should
> be the last resort anyways.
>
> I think this is the evolution of WaRsForcewakeAddDelayForAck
> (v2) and there is no better name, we should keep it.

Yes, I read the mailing lists comments about this. AFAICT, there is no 
better name.

>>   	 */
>>   
>>   	pass = 1;
>> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>>   	if (INTEL_GEN(dev_priv) >= 11) {
>>   		int i;
>>   
>> -		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>> +		dev_priv->uncore.funcs.force_wake_get =
>> +			fw_domains_get_with_fallback;
>>   		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>>   		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>>   			       FORCEWAKE_RENDER_GEN9,
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index ec9d340..3f00623 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>>   	return 0;
>>   }
>>   
>> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> +{
>> +	/* Wa_1604370585:icl (pre-prod)
>> +	 * Formerly known as WaPushConstantDereferenceHoldDisable
>> +	 */
>> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
>> +		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> +				  PUSH_CONSTANT_DEREF_DISABLE);
> Inherited from CNL and had to check if we have that on cnl. We do.
>
>> +
>> +	/* WaForceEnableNonCoherent:icl
>> +	 * This is not the same workaround as in early Gen9 platforms, where
>> +	 * lacking this could cause system hangs, but coherency performance
>> +	 * overhead is high and only a few compute workloads really need it
>> +	 * (the register is whitelisted in hardware now, so UMDs can opt in
>> +	 * for coherency if they have a good reason).
>> +	 */
>> +	WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
> Right, but the register name should be ICL_HDC_MODE.

ACK

>> +
>> +	return 0;
>> +}
>> +
>>   int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>>   {
>>   	int err = 0;
>> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>>   		err = cfl_ctx_workarounds_init(dev_priv);
>>   	else if (IS_CANNONLAKE(dev_priv))
>>   		err = cnl_ctx_workarounds_init(dev_priv);
>> +	else if (IS_ICELAKE(dev_priv))
>> +		err = icl_ctx_workarounds_init(dev_priv);
>>   	else
>>   		MISSING_CASE(INTEL_GEN(dev_priv));
>>   	if (err)
>> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
>>   }
>>   
>> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> +{
>> +	/* This is not an Wa. Enable for better image quality */
>> +	I915_WRITE(_3D_CHICKEN3,
>> +		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>> +
>> +	/* WaInPlaceDecompressionHang:icl */
>> +	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>> +					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
>> +
>> +	/* WaPipelineFlushCoherentLines:icl */
>> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> Didn't find a HSDES entry for this. The workaround name and the reg/bit
> matches tho.
>
> But the real question in here is that do we need to set this through
> indirect bb like we do with gen[8,9].
>
> And just to note that cnl is missing this too. But that can be done
> as a followup when we first figure out that should we use the indirect
> bb for all >= gen8.
>
> -Mika

Hmmmm... looking at it more carefully: isn't that a slightly different 
WA: WaPipelineFlushCoherentLines (not needed starting CNL)?
This is equivalent to a different WA: WaOCLCoherentLineFlush.
But indeed, it seems to be required for CNL as well. In fact, I'm pretty 
sure I added it to this patch because I saw it in CNL. Did it get lost?

>> +}
>> +
>>   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   {
>>   	if (INTEL_GEN(dev_priv) < 8)
>> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   		cfl_gt_workarounds_apply(dev_priv);
>>   	else if (IS_CANNONLAKE(dev_priv))
>>   		cnl_gt_workarounds_apply(dev_priv);
>> +	else if (IS_ICELAKE(dev_priv))
>> +		icl_gt_workarounds_apply(dev_priv);
>>   	else
>>   		MISSING_CASE(INTEL_GEN(dev_priv));
>>   }
>> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
>>   	whitelist_reg(w, GEN8_CS_CHICKEN1);
>>   }
>>   
>> +static void icl_whitelist_build(struct whitelist *w)
>> +{
>> +}
>> +
>>   static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>>   					 struct whitelist *w)
>>   {
>> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>>   		cfl_whitelist_build(w);
>>   	else if (IS_CANNONLAKE(i915))
>>   		cnl_whitelist_build(w);
>> +	else if (IS_ICELAKE(i915))
>> +		icl_whitelist_build(w);
>>   	else
>>   		MISSING_CASE(INTEL_GEN(i915));
>>   
>> -- 
>> 1.9.1

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Re: [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Revert to an L3 non-hash model, for performance reasons.
>
> v2:
>   - Place the WA name above the actual change
>   - Improve the register naming
> v3:
>   - Rebased
>   - Renamed to Wa_1604223664
> v4: Rebased on top of the WA refactoring
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 20 ++++++++++++++++----
>  2 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a6b1f85..5637cd7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8218,6 +8218,12 @@ enum {
>  #define GEN8_GARBCNTL				_MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
>  #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
> +#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
> +#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
> +
> +#define GEN11_GLBLINVL				_MMIO(0xB404)
> +#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 0)

(1 << 5)

> +#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x3f << 5)

0x7f
-Mika

>  
>  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>  #define   DFR_DISABLE			(1 << 9)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ffd27a1..83a53cc 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>  
> -	/* Wa_1405543622:icl
> -	 * Formerly known as WaGAPZPriorityScheme
> +	I915_WRITE(GEN8_GARBCNTL,
> +		   /* Wa_1604223664:icl
> +		    * Formerly known as WaL3BankAddressHashing
> +		    */
> +		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
> +		    GEN11_HASH_CTRL_EXCL_BIT0 |
> +		    /* Wa_1405543622:icl
> +		     * Formerly known as WaGAPZPriorityScheme
> +		     */
> +		    GEN11_ARBITRATION_PRIO_ORDER_MASK));
> +
> +	/* Wa_1604223664:icl
> +	 * Formerly known as WaL3BankAddressHashing
>  	 */
> -	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> -				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
> +	I915_WRITE(GEN11_GLBLINVL,
> +		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
> +		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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Re: [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo Lozano]

On 5/2/2018 3:23 AM, Mika Kuoppala wrote:
> Oscar Mateo <oscar.mateo@intel.com> writes:
>
>> Revert to an L3 non-hash model, for performance reasons.
>>
>> v2:
>>    - Place the WA name above the actual change
>>    - Improve the register naming
>> v3:
>>    - Rebased
>>    - Renamed to Wa_1604223664
>> v4: Rebased on top of the WA refactoring
>>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
>>   drivers/gpu/drm/i915/intel_workarounds.c | 20 ++++++++++++++++----
>>   2 files changed, 22 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index a6b1f85..5637cd7 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8218,6 +8218,12 @@ enum {
>>   #define GEN8_GARBCNTL				_MMIO(0xB004)
>>   #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
>>   #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
>> +#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
>> +#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
>> +
>> +#define GEN11_GLBLINVL				_MMIO(0xB404)
>> +#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 0)
> (1 << 5)
>
>> +#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x3f << 5)
> 0x7f
> -Mika

Lordy! Thanks for spotting this. Also, I went back to the HSD looking 
for the source of the mistake and the WA has been updated with more 
steps, so I'll send a new version.

-- Oscar

>
>>   
>>   #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>>   #define   DFR_DISABLE			(1 << 9)
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index ffd27a1..83a53cc 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>>   	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>>   				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>>   
>> -	/* Wa_1405543622:icl
>> -	 * Formerly known as WaGAPZPriorityScheme
>> +	I915_WRITE(GEN8_GARBCNTL,
>> +		   /* Wa_1604223664:icl
>> +		    * Formerly known as WaL3BankAddressHashing
>> +		    */
>> +		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
>> +		    GEN11_HASH_CTRL_EXCL_BIT0 |
>> +		    /* Wa_1405543622:icl
>> +		     * Formerly known as WaGAPZPriorityScheme
>> +		     */
>> +		    GEN11_ARBITRATION_PRIO_ORDER_MASK));
>> +
>> +	/* Wa_1604223664:icl
>> +	 * Formerly known as WaL3BankAddressHashing
>>   	 */
>> -	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
>> -				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
>> +	I915_WRITE(GEN11_GLBLINVL,
>> +		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
>> +		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
>>   }
>>   
>>   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>> -- 
>> 1.9.1

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